JP2001086179A - Agc circuit and communication terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an AGC circuit by which a loop gain is changed between an initial acquisition time and a synchronization lock time of received data so as to keep a level of the received data to an optimum level at all times thereby decreasing the time up to synchronization establishment and to obtain a communication terminal provided with the AGC circuit. SOLUTION: This communication terminal is provided with a power calculation section 13 that samples a receive signal at a prescribed sample internal to calculate the power of the received signal data, a subtractor 14 that calculates a difference between a preset power threshold value and the calculated power, an accumulator 16 that integrates the calculated difference, stores it, selects a prescribed bit string and outputs the selected string as a gain adjustment signal of the received signal, and a sampling control section 18 that changes the sampling interval to obtain the power of the received signal between the initial acquisition and the synchronization locking of the received signal so as to control the sampling interval of the received signal by the power calculation section. The gain of a gain amplifier is adjusted on the basis of the gain adjustment signal from the accumulator to amplify the received signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AGC (Automatic Gain Control) circuit and a communication terminal provided with the AGC circuit, for example, a cordless telephone.

[0002]

2. Description of the Related Art In a communication system, an automatic gain control (AGC) circuit is used in order to stabilize fluctuations in a received signal due to fluctuations in electric field strength due to fading. In the AGC circuit, first, the power of each data string of the received signal by the receiver is obtained, and the power values thereof are added by an adding circuit to obtain the power of the received signal. The received power output from the addition circuit is input to the subtraction circuit,
The difference between the power to be set by the AGC circuit loop and the reference value is obtained. The difference obtained by the subtraction circuit is input to an integrator after being multiplied by a constant by a multiplication circuit for determining the gain of the loop. The integrator integrates the output of the multiplication circuit and forms an AGC loop such that the output of the subtraction circuit becomes zero. Further, to change the AGC loop gain, a circuit for that purpose is required, and the magnitude of the gain cannot be arbitrarily changed. When the reception level fluctuates, the loop gain of the carrier recovery circuit and the clock recovery circuit of the demodulator fluctuates, so that a stable demodulation operation cannot be performed, and an AGC operation is required to keep the amplitude constant.

FIG. 5 shows a configuration of a conventional AGC circuit. In the circuit configuration shown in FIG. 5, the quasi-synchronous demodulation circuit 21 includes a burst modulation wave signal (IF input signal) transmitted intermittently.
, And quasi-synchronous demodulation using orthogonal carrier signals substantially equal to the carrier frequency to convert the signals into two-series analog signals. The A / D conversion circuits 22 and 23 convert the output signal from the quasi-synchronous demodulation circuit 21 into a digital data string of a plurality of bits, and these digital data strings are input to the multiplier circuit 24 and multiplied. And demodulation circuit 31 and squaring circuits 25 and 26.

The squaring circuits 25 and 26 square the output of the multiplier circuit 24 to obtain the power of each data string. The power of each data string from the squaring circuits 25 and 26 is added by the adding circuit 27, and as a result, the power of the received signal output from the multiplier circuit 24 is obtained. The subtraction circuit 28 having received the output received power from the addition circuit 27 obtains the difference between the power to be set by the AGC loop and the reference value 1.
The difference obtained by the subtraction circuit 28 is multiplied by a constant k serving as a loop gain in a multiplication circuit 29 that determines the gain of the loop, and is then input to an integration circuit 30. The integration circuit 30
An AGC loop is configured so that the output of the multiplication circuit 29 is integrated, the multiplier circuit 24 is driven, and the output of the subtraction circuit 28 becomes zero.

[0005] The response speed of such an AGC loop is determined by the loop gain k. The larger the loop gain k, the faster the response speed of the loop, and the smaller the loop gain, the slower the response speed. However, to respond to a burst signal, it is generally necessary to increase the response speed of the loop. However, increasing the loop response is equivalent to increasing the loop bandwidth. For this reason, the amplitude fluctuation component of the signal passing through the loop and the noise component superimposed on the received signal also pass through the loop, and are added to the received signal by the multiplier circuit 24, thereby deteriorating the signal quality.
For this reason, there is a limit in responding to a burst signal at high speed.

[0006] From such a viewpoint, in the configuration shown in FIG.
The loop has a high-speed response characteristic, and after the high-speed response, the AGC loop band is minimized and the influence of loop noise is eliminated.

The area determination circuit 18 determines the level by comparing the output signal of the subtraction circuit 28 with the reference value 2 and the reference value 3, and converts the signal into a three-state signal. This area determination circuit 1
8, the input signal from the subtraction circuit 28 becomes the reference value 2, 3
Is determined as shown in FIG. here,
C1 and C2 are 2-bit signals of the output signal of the area determination circuit 18. The reference value 2 is set larger than the reference value 3.

That is, when the output signal of the subtraction circuit 28 is larger than the reference value 2,
1 is set to 0, the output code C2 is set to 0, and when the output signal of the subtraction circuit 28 is smaller than the reference value 3, the output code C1 is set to 1, the output code C2 is set to 0, and the output signal of the subtraction circuit 28 is set to the reference value. When the value is between the value 2 and the reference value 3, the output code C1 is set to 0 and the output code C2 is set to 1.

The selection circuit 19 receives the output signal of the subtraction circuit 28 as an input, and selects one of the loop constants K1, K2, and K3 for the input codes C1 and C2 as shown in FIG. These loop constants K1, K2, K3 are K1≫
The relationship K2 ≧ K3 is set. As shown in FIG. 7, when the input code C1 is 0 and the input code C2 is 0, the selection circuit 19 selects the loop constant K1, and when the input code C1 is 0 and the input code C2 is Is 1, the loop constant K2 is selected, and the input code C1 is 1
If the input code C2 is 0, a loop constant K3 is selected.

As a result, the selection circuit 19 is provided with a subtraction circuit 28
Is larger than the reference value 2, the loop constant K1
Is selected, and when the output signal of the subtraction circuit 28 is smaller than the reference value 3, the loop gain K3 is selected.
Is a value between the reference value 2 and the reference value 3, the loop constant K2 is selected. The signal selected by the selection circuit 19 is input to a multiplication circuit 29 that determines the gain of the AGC loop.

When a signal is received for the first time, the received power is small because at most the noise component existing on the transmission line is received before the signal arrives. Therefore, the addition circuit 2
The value appearing at 7 is smaller than the reference value 3 and the output of the subtraction circuit 28 becomes a negative value. If the output level of the subtraction circuit 28 is equal to or less than the reference value 3, the area determination circuit 18 using the reference values 2 and 3 outputs C1 = 1 and C2 = 0 as shown in FIG.

At this time, assuming that the selection circuit 19 makes a selection as shown in FIG. 7, a loop constant K3 is input to the multiplication circuit 29. As described above, K1 to K3 are K1
If there is a relationship of ≫K2 ≧ K3, the AGC loop is kept at the minimum band. Since the output signal of the multiplying circuit 29 is a negative value (the input is small) even if K3 is a small value, the input of the integrating circuit 30 is set so that the multiplier circuit 24 has the maximum gain in order to increase the input signal. Control.

In a voice communication or the like, when a call is first started, a communication channel is designated by a signaling signal, and then actual communication is started. In this case, the value of the integration circuit 30 can be set to a value that maximizes the gain of the multiplier circuit 24 by using a reset signal connected to the integration circuit 30 of FIG.

When a signal is received, since the multiplier circuit 24 is set to the maximum gain in the addition circuit 27 indicating the received power, a large voltage is generated and the output of the subtraction circuit 28 becomes a large positive value. . If this level exceeds the reference value 2 by the logic shown in FIG. 6, the areas are determined as C1 = 0 and C2 = 0,
By controlling the selection circuit 19, K1 is selected according to FIG.
Since this K1 has a large value, the AGC loop becomes a high-speed loop after being input to the multiplication circuit 29.

Accordingly, when the loop responding to the input signal at high speed responds at high speed, the signal power input to the demodulation circuit 31 by the multiplier circuit 24 rapidly matches the reference value. Is a small value as an absolute value. If this signal is lower than the reference value 2 of the area determination circuit 18 and larger than K3, the output code is C1 = 0, C2 = 1.
And the selection circuit 19 is controlled to select the loop constant K2. At this time, since K2 is a sufficiently small value as compared with K1, the noise in the AGC loop also has a sufficiently small value, and the signal deterioration is suppressed to a minimum. Therefore, when high-speed synchronization is required, the bandwidth of the AGC loop becomes large, and once the AGC loop is pulled in, the bandwidth of the AGC loop becomes small and signal deterioration is minimized.

Next, consider the case where the reception burst has disappeared. When the received signal disappears, the output of the subtraction circuit 28 is kept at a negative value. In this case, in many cases, the output of the subtraction circuit 28 is equal to or less than the reference value 3, and the selection circuit 19
3 is input to the multiplication circuit 29. Since K3 is a sufficiently small value, only a very small value is supplied to the integrator 30 following the multiplier 29, and the value of the integrator 30 is long (compared to the interval of the voice activation signal burst). It is kept almost constant over time. Therefore, the gain of the multiplier circuit 24 is maintained at substantially the same value as when there is a burst signal.

For this reason, when the next signal is received, the gain of the multiplier circuit 24 is kept almost ideal, so that the time required for the next pull-in becomes extremely short. When the input signal is larger than the entire burst, the loop constant K1 is selected so that the AGC loop responds at a high speed as described above. However, when the input signal is smaller than the previous burst, the loop constant K1 is not changed. Can take a long time.
In a system such as voice activation, since the transmitting station is the same station, the level difference has little effect on the subsequent demodulator.

[0018]

In a communication system, how to synchronize immediately at the start of communication is one of the important performances. Another important performance factor is how stable the synchronization can be maintained after the synchronization is established.

The AGC circuit plays an important role in satisfying these conditions. That is, the signal received by the receiving unit is affected by fading or the like depending on the communication environment, and the received power constantly fluctuates. In order to perform demodulation with few reception errors, it is necessary to always maintain an optimal signal level for the communication system used. In particular, during the initial synchronization period until the synchronization is established, it is necessary to quickly convert the received signal level to an optimum level and shorten the time until the synchronization is established.

The present invention has been made in view of the above points, and it is possible to always maintain the signal level of received data at an optimum level by changing the loop gain between the time of initial capture of received data and the time of maintaining synchronization. It is an object of the present invention to provide an AGC circuit capable of shortening the time until synchronization is established and a communication terminal including the AGC circuit.

[0021]

In order to achieve the above object, an AGC circuit according to the present invention provides a power supply for sampling a received signal at predetermined sampling intervals and calculating a power value of the sampled received signal data. Value calculation means,
A difference calculating means for calculating a difference between a preset power threshold value and a power value calculated by the power value calculating means; and a predetermined bit string which integrates and holds the value of the difference calculated by the difference calculating means and holds a predetermined bit string. Accumulating means for selecting and outputting as a gain adjustment signal of the received signal, and changing the sampling interval for obtaining the power of the received signal between the time of initial supplementation of the received signal and the time of synchronizing, by changing the sampling interval of the received signal by the power value calculating means. The apparatus includes sampling control means for controlling a sample interval, and a gain amplifier for adjusting a gain based on a gain adjustment signal from the accumulating means to amplify a received signal.

According to such a configuration, the loop gain can be changed between the time of the initial capture of the received data and the time of the synchronization holding, so that the signal level of the received data can always be kept at the optimum level. AGC circuit capable of shortening the time of the AGC can be obtained.

The power value calculating means includes an absolute value calculating section for calculating an absolute value of a digital signal converted into an in-phase signal and a quadrature signal of a received signal in accordance with a sampling interval from the sampling control means; And a power value calculating unit for obtaining a power value of the received signal data based on an output from the unit.

According to such a configuration, the power value of the received signal data can be obtained with high accuracy.

The accumulator includes an accumulator, and an adder for providing, as an input to the accumulator, a value obtained by adding a value of the difference calculated by the difference calculator and an output of the accumulator. , A predetermined bit string is selected as a gain adjustment signal for the received signal.

According to such a configuration, when a certain bit string is extracted from the accumulator, the AGC signal has a large control amount when the sample interval is short, and conversely, a small control amount when the sample interval is long. Thereby, AG
The loop gain of the C circuit can be arbitrarily changed at high speed.

Further, the communication terminal according to the present invention performs time-division of one line, allocates a time zone to transmission and reception, and alternately switches between transmission and reception in the allocated time zone to perform bi-directional communication. A communication terminal comprising a system circuit and a reception system circuit, wherein the reception system circuit performs initial capture of reception data by the reception system circuit that decodes reception data based on a reception baseband signal demodulated from reception signal data received from an antenna. A synchronization determination circuit for determining a synchronization holding state, and a gain adjustment signal in which a loop gain is changed by changing a sample interval of reception data between an initial capture of reception data and a synchronization holding time determined by the synchronization determination circuit. An AGC circuit, wherein the reception system circuit amplifies and outputs received data based on a gain adjustment signal from the AGC circuit. It is.

According to such a configuration, the loop gain is changed between the time of the initial capture of the reception data and the time of the synchronization holding, so that the signal level of the reception data can always be kept at the optimum level, and the time until the synchronization is established. A communication terminal that can reduce the time can be obtained.

Further, the AGC circuit outputs a gain control signal having a large control amount by shortening the sampling interval of the reception data at the time of initial capture of the reception data, and reduces the sampling interval of the reception data at the time of maintaining the synchronization of the reception data. It is characterized by outputting a gain control signal with a long and small control amount.

According to such a configuration, the loop gain can be rapidly increased at the time of the initial supplement, and the loop gain can be rapidly reduced during the synchronization holding.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of the signal receiving unit according to the present embodiment. FIG.
In the configuration of the signal receiving section shown in (1), data received by the antenna 1 is amplified by the low noise amplifier 2 and the signal level increases. Then, the mixers 3 and 4 and the 90 ° phase shifter 5
By mixing the mutually orthogonal frequencies (sinωt, cosωt) having the same frequency as the carrier frequency with the output of the low-noise amplifier 2, the received data can be in-phase,
The signals are down-converted into quadrature (I, Q) intermediate frequency regions.

The in-phase and quadrature signals down-converted by the mixers 3 and 4 are converted to signal levels optimal for the demodulator by gain amplifiers 6 and 7 controlled by an AGC circuit described later. Thereafter, the in-phase and quadrature analog signals (I, Q) are converted into digital signals by the A / D converter. The converted digital signal is sent to a demodulator and an AGC circuit based on the demodulation method of the receiving system.

FIG. 2 is a block diagram showing a configuration of the AGC circuit according to the present embodiment. As shown in FIG. 2, the in-phase and quadrature signals (I, Q) entering the AGC circuit are:
The signals are converted into digital signals by the A / D converters 10 and 11. Then, in order to obtain the power value of each data, the absolute value of the received signal is calculated by the absolute value calculating unit 12, and the power value of the received signal data is further calculated by the power value calculating unit 13 using the following approximate expression. Ask.

Max ｛| I |, | Q |｝ + ／ × Min
｛| I |, | Q |｝

Note that Max ｛| I |, | Q |｝ and Min ｛|
I | and | Q |｝ indicate that the larger or smaller of | I | and | Q | is selected, respectively.

Then, the difference between the power threshold value, which is the optimum signal level for the demodulator, and the power value obtained as described above is obtained by the subtractor 14 serving as difference calculating means. As a result, the value of the obtained difference is determined by the gain amplifiers 6 and 6 shown in FIG.
7 is a control amount for increasing / decreasing the output. The difference between the reception data obtained by the subtractor 14 and the threshold value is integrated for an appropriate time by an adder 15 and an accumulator 16 serving as accumulating means, and the integrated difference value is stored in the accumulator 1.
6 is held. An appropriate bit string is selected from the accumulator 16 and transmitted as an AGC signal (gain adjustment signal). Finally, the analog signal is converted by the D / A converter 17 and output to the gain amplifiers 6 and 7 shown in FIG.

By the way, in the AGC circuit shown in FIG. 2, the value integrated in the accumulator 16 changes by changing the data sampling interval in the process of performing the above processing. That is, in the received data under the same conditions, if the sampling interval is short during a certain integration period, the accumulator 1
The integrated value is reflected up to the upper 6 bits, while if the sample interval is long, it is reflected only in the lower bits. As a result, when a predetermined bit string is extracted, a large control amount is obtained when the sample interval is short as an AGC signal, and a small control amount is obtained when the sample interval is long. With this, AGC
The loop gain of the circuit can be arbitrarily changed. In the AGC circuit shown in FIG. 2, a sampling control unit 18 which inputs a detection signal at the time of initial supplementation and at the time of synchronism holding of received data from a synchronization determination circuit (not shown) and controls a sampling interval is used by the absolute value calculation unit 12 to control the sampling interval. Is calculated, the value integrated in the accumulator 16 changes, and A
The control amount of the GC signal (gain adjustment signal) changes.

Next, FIG. 3 shows an AGC according to this embodiment.
The relationship between the transmission and reception data at the communication terminals T1 and T2 provided with the circuit and the cycle for resetting the adder 15 shown in FIG. 2 will be described. Here, the communication terminals T1 and T2 are provided with a transmission system circuit that performs time-division of one line, allocates a time zone to transmission and reception, and alternately switches between transmission and reception in the allocated time zone to perform two-way communication. TDD with receiving system circuit
(Time Division Duplex) The terminal is controlled, for example, used as a cordless telephone.

When the communication terminal T2 receives received data for the first time, that is, at the time of initial synchronization, it is desired to quickly adjust to the optimum signal level and establish synchronization. When the difference between the power and the power threshold is large, the value integrated by the accumulator 16 becomes a large value. That is, even the upper bits are reflected. The adder reset shown in the figure indicates that the adder 15 is cleared to 0, and at this time, the gain adjustment voltages input to the gain amplifiers 6 and 7 are updated.

Once synchronization is achieved by the operation of the AGC circuit as described above, the communication system enters a synchronization holding state. At this time, if the signal level changes due to short-term noise or the like, if the AGC circuit reacts due to the noise, the level of almost noise-free signals also changes, and in the worst case, synchronization loss occurs. Would. In order to avoid such a situation, it is necessary to reduce the loop gain of the AGC circuit. For this purpose, a long sample interval is used. When the sample interval is long, the integrated value is not reflected in the upper bits of the accumulator 16 and the integrated value is reflected in the lower bits as compared with the case where the sample interval is short. As a result, the loop gain of the AGC circuit is reduced, and stable synchronization can be maintained.

Further, FIG. 4 shows a communication terminal having a transmission system circuit and a reception system circuit by TDD control for performing bidirectional communication by switching between transmission and reception alternately and having the AGC circuit shown in FIG. 2 in the reception system circuit. 1 shows a schematic configuration diagram of a certain cordless telephone. Here, the configuration of the master unit and the configuration of the slave unit have substantially the same configuration. In the following, only the configuration of the master unit will be described.

That is, the cordless telephone as a communication terminal shown in FIG. 4 is a known TDD (Time Division Dupl
ex) In addition to the configuration of the transmission system circuit and the reception system circuit under control, the keypad, the LCD unit 45, and the control unit 46, reception based on the reception baseband signal demodulated from the reception signal data received from the antenna 38. A despreading unit 40 of a receiving circuit for decoding data; a synchronization determining circuit 43 for determining whether to initially capture received data and to hold synchronization when decoding the received data by the despreading unit 40; 43
And an AGC circuit 44 that outputs a gain adjustment signal in which the loop gain is changed by changing the sample interval of the received data between the time of the initial capture of the received data and the time of maintaining the synchronization determined by the above. The gain of a built-in gain amplifier is adjusted based on a gain adjustment signal from the AGC circuit 44 to amplify received data. The control section 46 has a function of controlling communication protocol processing and a TDD control function, and although not shown in the figure, is connected to a transmission system circuit and a reception system circuit that are TDD controlled.

First, the operation of the transmission system circuit will be described.
An analog audio signal input from the microphone 31 is converted into digital data by an A / D converter built in the audio codec 32 to be a digital audio signal. The digital audio signal is converted by the audio encoding unit incorporated in the audio codec 32 into audio encoded data in which one superframe period is 2 msec. Here, the audio encoded data is 5 bits as one word. In other words, voice encoding is performed using 40 kbps ADPCM (Adaptive Differentia).
l Pulse Code Modulation) Performs encoding processing. Also,
The speech encoded data output from the speech encoding is reconfigured so that 6 bits become one word together with the 1-bit error detection code, and output to the TDD unit 33.

The TDD section 33 includes the audio codec 32
Speech coded data with error detection code output from
TDD for each frame, that is, every 96 bits
Output to the frame assembling unit 34 at an appropriate time during the transmission timing. The frame assembly part 34
The preamble information, the base information, the control information, and the guard bit are added to the audio information input from the TDD unit 33,
One transmission frame is configured. Here, the preamble information is all 1, the base is fixed at 1, and the guard bit is also all 1.
Information. The control information is a data string set by the control unit 46 that controls the communication protocol processing of the telephone. Then, after performing differential PSK processing on the configured one frame information, the information is output to the spread modulation unit 35.

The spread modulator 35 spreads the input data based on the spread code sequence specified in advance by the controller 46, generates a transmission baseband signal,
Hand over to The quadrature modulation unit 36 mixes the input transmission baseband signal with the carrier output from the carrier generation circuit 47 and transmits / receives the signal by a pin diode.
It is delivered to the receiving switch 37. Send / receive switch 3
7 is a quadrature modulation unit 3 according to the TDD transmission timing.
6 is delivered to an antenna 38, where it is emitted into the air. Here, the frequency channel number of the carrier output from the carrier generation circuit 47 is specified by the control unit 46.

Next, the operation of the receiving system circuit will be described.
The received signal input from the antenna 38 is input to the transmission / reception changeover switch 37 and is delivered to the quadrature demodulation unit 39 according to the reception timing of the TDD unit 33. The quadrature demodulation unit 39 demodulates the received baseband signal by performing a mixing calculation of the carrier wave output from the carrier wave generation circuit 47 and the received received data, and inputs the demodulated baseband signal to the despreading unit 40.

The despreading section 40 decodes the received data using a matched filter, a dot and cross calculation means, and outputs the decoded data to the frame decomposition section 41. Frame disassembly unit 4
In step 1, the information is decomposed into control information and audio information, and each is passed to the control unit 46 and the TDD unit 33. The TDD unit 33
Voice information that is transferred in bursts in frame units according to the reception timing is stored in a built-in FIFO (First In First
Out) The data is temporarily stored in a memory or the like, converted into a data stream at a constant speed, and output to the audio codec 32.

In the audio codec 32, the TDD unit 3
The speech coded data with the error detection code output from 3 is delivered to a built-in error detection circuit, performs error detection for every 6 bits per word, and is delivered to a built-in speech decoder.
The speech decoder incorporates 5 bits of speech signal words when no error is detected for the speech codewords sequentially delivered and no error is detected earlier in the frame to which the speech codeword belongs. The digital signal is transferred to a digital-to-analog (D / A) converter and converted into an analog audio signal. If an error is detected, the corresponding speech codeword and speech codewords subsequent to the speech codeword in a frame including the speech codeword are discarded, and the speaker 42 is set to a mute state.

Here, when the despreading section 40 decodes the received data, the synchronization determination circuit 43 determines whether the received data is to be initially captured or to hold the synchronization, and outputs a detection signal to the AGC circuit 44. The AGC circuit 44 has the configuration shown in FIG. 2 and, based on the detection signal from the synchronization determination circuit 43, quickly adjusts the optimal signal level during the initial capture of the received data as described above. To establish synchronization, output a gain control signal with a large control amount by shortening the data sampling interval. Once the synchronization is established and the synchronization holding state is entered, the received data sampling is performed to maintain stable synchronization. By increasing the interval, a gain control signal with a small control amount is output to the despreading unit 40. Thereby, the despreading unit 4
A value of 0 can always provide the optimum level of received data.

[0050]

As described above, according to the present invention, the signal level of the received data can be always kept at the optimum level by changing the loop gain between the time of the initial acquisition of the received data and the time of maintaining the synchronization. AGC that can shorten the time until synchronization is established, has high-speed response of the AGC loop at the time of initial acquisition, and reduces the gain of the AGC loop during synchronization maintenance to eliminate the effects of loop noise and secure stable communication. Circuit and its A
A communication terminal having a GC circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a signal receiving unit used in an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an AGC circuit according to the embodiment of the present invention.

3 is an explanatory diagram showing a relationship between transmission and reception data in communication terminals T1 and T2 provided with an AGC circuit according to an embodiment of the present invention, and a cycle for resetting an adder 15 shown in FIG.

FIG. 4 is a block diagram showing a configuration of a cordless telephone as a communication terminal according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional AGC circuit.

6 is an explanatory diagram of an input / output relationship of an area determination circuit 18 in FIG.

7 is an explanatory diagram of an input / output relationship of the selection circuit 19 in FIG.

[Explanation of symbols]

 10, 11 A / D converter 12 Absolute value calculation unit 13 Power value calculation unit 14 Subtractor 15 Adder 16 Accumulator 17 D / A converter 18 Sampling control unit 31 Microphone 32 Audio codec 33 TDD unit 34 Frame assembling unit 35 Diffusion Modulator 36 Quadrature modulator 37 Transmit / receive switch 38 Antenna 39 Quadrature demodulator 40 Despreader 41 Frame decomposer 42 Speaker 43 Synchronization determination circuit 44 AGC circuit 45 Keypad and LCD 46 Control unit 47 Carrier generation circuit

Claims (5)

[Claims] 1. A power value calculating means for performing data sampling of a received signal at a predetermined sampling interval to calculate a power value of sampled received signal data, and a power threshold value set in advance and calculated by the power value calculating means. Difference calculating means for calculating a difference from the calculated power value, and accumulating means for integrating and holding the value of the difference calculated by the difference calculating means, selecting a predetermined bit string, and outputting the selected bit string as a gain adjustment signal of the received signal. A sampling control unit that controls a sampling interval of the reception signal by the power value calculation unit by changing a sampling interval for obtaining the power of the reception signal between the time of the initial supplement of the reception signal and the time of the synchronization holding; and A gain amplifier for adjusting the gain based on the gain adjustment signal and amplifying the received signal.
GC circuit. 2. The AGC circuit according to claim 1, wherein said power value calculation means calculates an absolute value of a digital signal converted into an in-phase and quadrature signal of a received signal according to a sample interval from said sampling control means. An AGC circuit comprising: an absolute value calculation unit; and a power value calculation unit that calculates a power value of received signal data based on an output from the absolute value calculation unit. 3. The AGC circuit according to claim 1, wherein said accumulating means adds a value obtained by adding an accumulator, a difference value calculated by said difference calculating means, and an output of said accumulator to said accumulator. An AGC circuit comprising: an adder for providing a predetermined bit string from the accumulator as a gain adjustment signal for a received signal. 4. A transmission circuit and a reception circuit for performing time-division of one line, allocating a time zone to transmission and reception, and alternately switching between transmission and reception in the allocated time zone to perform bidirectional communication. A communication terminal that decodes received data based on a received baseband signal demodulated from received signal data received from an antenna, and that determines whether to initially acquire received data and to maintain synchronization by the receiving system circuit. A determination circuit for outputting a gain adjustment signal in which a loop gain is changed by changing a sample interval of the reception data at the time of initial capture and at the time of synchronization hold of the reception data determined by the synchronization determination circuit;
A communication terminal, comprising: a GC circuit; wherein the reception system circuit amplifies and outputs received data based on a gain adjustment signal from the AGC circuit. 5. The communication terminal according to claim 4, wherein the AGC circuit outputs a gain control signal having a large control amount by shortening a sampling interval of the reception data at the time of initial capture of the reception data. A communication terminal for outputting a gain control signal having a small control amount by increasing a sampling interval of received data when synchronization is maintained.