JP2001085691A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a current driving capability even when a channel length is identical. SOLUTION: The channel region of a MIS-type semiconductor element is divided into at least two sections in a channel width direction by an isolating and insulating film 12 whose surface is situated in a position lower than the surface of protruding parts. In addition, first regions near steps between recessed parts and the protruding parts are provided, and second regions which correspond to the protruding parts in the first regions are provided. A virtual semiconductor element is assumed in such a way that the total sum of widths in the channel width direction of the recessed parts is designated as Gt, that the total sum of widths in the channel width direction of the protruding parts is designated as Wt, that the current density of a current flowing to the channel region is equal to the current density of a current flowing to the second regions of the MIS-type semiconductor element and that the total current flowing to the channel region is equal to the total current flowing to the channel region of the MIS-type semiconductor element. When the virtual channel width of the virtual semiconductor element is designated as Wi, it is arranged that Wi-Wt> Gt is established.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of increasing the current of a MIS type semiconductor device.

[0002]

2. Description of the Related Art As the integration of LSIs increases, the load on wiring and the like increases. Therefore, it is desired to improve the current driving capability of MIS transistors. In order to increase the current driving capability, the channel length L of the MIS transistor may be reduced, or the channel width W of the MIS transistor may be increased.

However, in order to reduce the channel length, it is necessary to develop high-performance lithography technology, low-acceleration ion implantation technology, highly controlled impurity activation technology, and the like. Cost is required. Further, when the channel width is increased, the area occupied by the transistor increases, which leads to an increase in the chip area.

[0004]

As described above, with the increasing integration of LSIs, it is desired to improve the current driving capability of the MIS transistor. However, in order to reduce the channel length of the transistor, advanced technical development has been required. However, when the channel length of the transistor is increased, there is a problem that the area occupied by the transistor increases.

The present invention has been made to solve the above-mentioned conventional problems, and has as its object to provide a semiconductor device capable of increasing the current driving capability even when the channel length is the same.

[0006]

According to the present invention, there is provided a semiconductor substrate having a concave portion on a surface and a convex portion formed in the concave portion, a gate formed on a channel region of the convex portion via a gate insulating film. A semiconductor device including an MIS type semiconductor element having an electrode and source and drain regions formed so as to sandwich the channel region, wherein a channel region of the MIS type semiconductor element has the M
The IS-type semiconductor device is formed over a protrusion adjacent to the IS-type semiconductor element in the channel width direction, and the upper surface of the protrusion is located higher than the upper surface of the isolation insulating film formed in the recess.

According to the present invention, there is provided a gate electrode formed via a gate insulating film on a channel region of a semiconductor substrate having a concave portion and a convex portion formed on a surface thereof, and a source and a drain formed so as to sandwich the channel region. MI having a region
A semiconductor device having an S-type semiconductor element, wherein the MI
The channel region of the S-type semiconductor element is divided into at least two or more sections in the channel width direction by an isolation insulating film formed in the concave portion and having an upper surface located at a position lower than the upper surface of the convex portion. A first region in the vicinity of a step between the first region and the second region, and a second region corresponding to the first region. The total width of the concave portions in the channel width direction is Gt,
The total width of the protrusions in the channel width direction is Wt, the channel length is equal to the channel length of the MIS type semiconductor device, and the current density of the current flowing through the channel region is Mt.
The total current flowing in the channel region is equal to the current density of the current flowing in the second region of the IS-type semiconductor device and is equal to the MI.
Assuming a virtual semiconductor element equivalent to the total current flowing in the channel region of the S-type semiconductor element, and Wi is the virtual channel width of the virtual semiconductor element, Wi−Wt> G
It is characterized in that it is configured to be t.

It is preferable that the upper surface of the isolation insulating film is formed at a position deeper than the depth of the source and drain regions near the gate electrode.

According to the present invention, since the channel region is divided by the isolation insulating film whose upper surface is located at a position lower than the upper surface of the protrusion, the current flowing through the channel region near the step between the recess and the protrusion is reduced. The current density increases. Assuming a virtual semiconductor element in consideration of an increase in current near the step, the virtual channel width of the virtual semiconductor element is Wi, the total width of the recess in the channel width direction is Gt,
When the total width of the protrusions in the channel width direction is Wt,
By configuring so that Wi−Wt> Gt, the current driving capability can be increased as compared with the conventional element without increasing the element occupation area.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

First, the basic principle of the present invention will be described with reference to FIG. FIG. 1A is a plan view showing a MIS transistor and a planar configuration around the MIS transistor.
FIG. 2B is a cross-sectional view along the line BB in FIG.

1A and 1B, 11 is a semiconductor substrate (silicon substrate or the like), 12 is an element isolation insulating film having an STI structure, 13 is a gate insulating film, 14 is a gate electrode,
Reference numerals 15 and 16 indicate source and drain regions.

As shown in the figure, the element region of the MIS transistor is formed in a convex portion (the width of the convex portion in the channel width direction is W) on the surface of the semiconductor substrate 11, and is formed in a concave portion around the element region. The film 12 is formed such that its upper surface is lower than the upper surface of the projection.

Since the upper surface of the element isolation insulating film 12 is lower than the upper surface of the convex portion, a channel is also formed in the step region between the convex portion and the concave portion, and the current density increases near the corner of the convex portion due to electric field concentration. Such a phenomenon that the current density increases near the corner is conventionally known.

FIG. 1C shows the current density Id per unit channel width between the source and the drain of the MIS transistor described above. The width of the region (first region) where the current density per unit channel width is increased in the vicinity of the step is Wc. Further, the current density per unit channel width in a region (second region) between the first regions where there is no increase in current density is defined as Idf.

Here, the current amount Ic in the first region near the step is:

[0017]

(Equation 1)

## EQU1 ## That is, when the first region is replaced with a structure equivalent to that of the second region, it is expressed in terms of how much the effective (virtual) channel width increases.

FIG. 2 illustrates the concept of the above equation. As shown in FIG. 2A, the increase ΔI in the amount of current in the first region is ΔI = αWc · Idf, and a virtual region in which a channel region is formed only by a structure equivalent to that in the second region. In the transistor (FIG. 2B), the channel width is 2
This means that αWc has increased.

Therefore, the total current I of the MIS transistor shown in FIG. 1 (equal to the total current of the virtual transistor shown in FIG. 2) is I = 2Ic + (W−2Wc) Idf = (2αWc + W) Idf It is expressed as

Based on the above, a preferred embodiment of the present invention will be described below with reference to FIG.

FIG. 3A is a plan view showing a MIS type semiconductor device according to the present embodiment and a plan view of the periphery thereof, FIG. 3B is a sectional view taken along the line BB of FIG. FIG.
FIG. 3C is a cross-sectional view taken along the line CC of FIG.

In FIG. 3, reference numeral 11 denotes a semiconductor substrate (silicon substrate or the like), 12 denotes an element isolation insulating film having an STI structure,
Is a gate insulating film, 14 is a gate electrode, 15a and 16a
Are source and drain regions (extension regions) containing relatively low concentration impurities, 15b and 16b are source and drain regions containing relatively high concentration impurities, and 17 is formed on the side wall of the gate electrode 14. 4 shows a side wall insulating film.

As shown in FIG. 3, a plurality of protrusions (the number of protrusions is n and the width in the channel width direction of each protrusion is W) are formed on the surface of the semiconductor substrate 11. An element isolation insulating film 12 is formed in a concave portion around the convex portion (the width of the concave portion in the channel width direction is G), and the upper surface of the element isolating insulating film 12 is lower than the upper surface of the convex portion. Further, the element isolation insulating film 12
In order to maximize the current density at the corner of the step region, the upper surface is formed at a position where the upper surface is deeper than the depth near the gate electrode 14 of the source and drain regions 15a and 16a. That is, the element isolation insulating film 12
Is formed such that its upper surface is deeper than the depth of the extension region.

Thus, the example shown in FIG. 3 has a structure in which a plurality of the structures shown in FIG. 1 are arranged in the channel width direction. A channel is formed in the step portion region, and each channel is divided into n in the channel width direction by an element isolation insulating film 12 formed in a concave portion.

In the above description and the following description, for convenience,
Although the entire insulating film surrounding the convex portion is described as an element isolation insulating film 12, a region between adjacent convex portions functions as an insulating film for separating a channel region in the same device.

The respective current densities of the respective channel regions divided by the element isolation insulating film 12 are as shown in FIG. Therefore, similarly to the example described above, the width of the region (first region) where the current density per unit channel width is increased near the step portion is Wc,
A region between the first regions where the current density does not increase (second region
Assuming that the current density per unit channel width in the region (I) is Idf, each current amount I in each channel region is expressed as I = (2αWc + W) Idf. Therefore, the total current It flowing between the source and the drain of the MIS type semiconductor device shown in FIG. 3 is expressed as It = n (2αWc + W) Idf.

Here, the total width of the concave portions in the channel width direction is Gt (= (n-1) G), and the total width of the convex portions in the channel width direction is Wt (= nW). The channel length L is equal to the channel length of the MIS semiconductor device shown in FIG. 3, and the current density of the current flowing in the channel region (current density is constant in the channel width direction) shown in FIG. Density (Idf) of the current flowing in the second region of
Assuming a virtual semiconductor device (virtual semiconductor device) having the same total current and flowing in the channel region as the total current flowing in the channel region of the MIS type semiconductor device shown in FIG. Let Wi be the virtual channel width.

At this time, the total amount of current flowing through the channel region of the virtual semiconductor device (ie, the total current It flowing through the channel region of the MIS type semiconductor device shown in FIG. 3) is: It = Wi · Idf = n (2αWc + W) Idf.

On the other hand, as a semiconductor element (comparative semiconductor element) to be compared with the MIS semiconductor element shown in FIG. 3, the channel length is equal to the channel length of the MIS semiconductor element shown in FIG. 3 (only the channel region is not divided by the concave portion), and the channel width of the MIS semiconductor device shown in FIG. 3 is equal to the second region of the MIS semiconductor device shown in FIG. Assume a semiconductor element equal to the element width Wr (= Wt + Gt) in the direction.

At this time, the total amount of current Ir flowing through the channel region of the comparative semiconductor device is as follows: Ir = Wr · Idf = (Wt + Gt) Idf

The condition that the total amount of current flowing in the channel region of the MIS type semiconductor device shown in FIG. 3 is larger than the total amount of current flowing in the channel region of the comparative semiconductor device, It (= Wi · Idf)> Ir (= ( Wt + Gt) Idf). Therefore, Wi · Idf> (Wt + Gt) Idf, and the above condition is expressed as Wi−Wt> Gt.

Further, Wi, Wt and Gt are as follows: Wi = n (2αWc + W) Wt = nW Gt = (n−1) G Therefore, the above-mentioned condition is as follows: n · 2αWc> (n−1) G expressed.

The inventor of the present application obtained typical values of α and Wc by simulation. Channel length L = 0.
1 μm, the gate insulating film thickness Tox = 2.7 nm, and the roundness of the corner at the step was 30 nm in radius. At this time,
The value of α was about 4 and the value of Wc was about 30 nm. Therefore, when the number of divisions n is large, the width G of the concave portion is set to 24
By setting the thickness to about 0 nm or less, the amount of current can be increased as compared with a comparative semiconductor element having the same element occupation area.

In the example shown in FIG. 3, the respective convex portions 20 are separated from each other by the isolation insulating film 12, but the adjacent convex portions may be connected at one or more locations. Good. That is, it is only necessary that the respective channel regions formed in the adjacent protrusions are separated by the separation insulating film formed in the recesses, and the respective protrusions 20 do not necessarily need to be completely separated. In the example of FIG. 3, each of the source regions 15 and each of the drain regions that are separately formed in the example of FIG. 3 are connected to each other by connecting the adjacent convex portions in an appropriate region other than between the adjacent channel regions. , A common source region and a common drain region. By making the source region and the drain region common, it is possible to easily draw out the electrodes from these regions.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist thereof.

[0037]

According to the present invention, the channel region is divided into a plurality of sections by the isolation insulating film, and the width of the recess in which the isolation insulating film is formed in the channel width direction is set to a certain value or less. Without increasing the occupied area, the current driving capability can be increased as compared with the conventional device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic principle of the present invention.

FIG. 2 is a diagram showing an increase in an effective channel width in the device shown in FIG. 1;

FIG. 3 is a diagram showing a preferred embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Element isolation insulating film 13 ... Gate insulating film 14 ... Gate electrode 15, 15a, 15b ... Source region 16, 16a, 16b ... Drain region 17 ... Side wall insulating film 20 ... Convex part

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F040 EC19 EC22 EC24 EE03 EE04 EF02 EK05 FA03 5F048 AA08 AC01 BA01 BB01 BB20 BC06 BD07 BG14

Claims (3)

[Claims] 1. A semiconductor device having a concave portion on a surface and a convex portion formed in the concave portion, a gate electrode formed on a channel region of the convex portion via a gate insulating film on a semiconductor substrate, and sandwiching the channel region. And a source and drain region formed as described above, wherein a channel region of the MIS semiconductor device has a channel region in a channel width direction of the MIS semiconductor device with the recess interposed therebetween. A semiconductor device, wherein the upper surface of the protrusion is formed at a position higher than the upper surface of the isolation insulating film formed in the recess. 2. A gate electrode formed on a channel region of a semiconductor substrate having a concave portion and a convex portion formed on a surface thereof via a gate insulating film, and source and drain regions formed to sandwich the channel region. Wherein the channel region of the MIS semiconductor element is formed by an isolation insulating film formed in the recess and having an upper surface located at a position lower than the upper surface of the projection. At least 2 in channel width direction
A second region divided into the above sections and corresponding to the first region near the step between the concave portion and the convex portion and the convex portion between the first regions.
The total length of the concave portions in the channel width direction is Gt, the total width of the convex portions in the channel width direction is Wt, the channel length is equal to the channel length of the MIS type semiconductor element, and The current density of the current flowing in the channel region is equal to the current density of the current flowing in the second region of the MIS type semiconductor device;
Further, assuming a virtual semiconductor device in which the total current flowing in the channel region is equal to the total current flowing in the channel region of the MIS type semiconductor device, and when the virtual channel width of the virtual semiconductor device is Wi, , Wi-Wt> Gt. 3. The device according to claim 1, wherein an upper surface of the isolation insulating film is formed at a position deeper than a depth of the source and drain regions near the gate electrode. Semiconductor device.