CN116632050A - Semiconductor device, forming method thereof and memory - Google Patents

Semiconductor device, forming method thereof and memory Download PDF

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Publication number
CN116632050A
CN116632050A CN202310466245.2A CN202310466245A CN116632050A CN 116632050 A CN116632050 A CN 116632050A CN 202310466245 A CN202310466245 A CN 202310466245A CN 116632050 A CN116632050 A CN 116632050A
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China
Prior art keywords
gate
insulating layer
channel structure
substrate
gate insulating
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Chinese (zh)
Inventor
顾婷婷
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310466245.2A priority Critical patent/CN116632050A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The embodiment of the disclosure provides a semiconductor device, a forming method thereof and a memory, wherein the semiconductor device comprises: a substrate; a first gate structure located on the substrate; a channel structure covering at least a top surface of the first gate structure and including at least one U-shaped opening facing the first direction; the second grid structure is positioned on the channel structure and is symmetrically arranged with the first grid structure along the first direction; wherein at least one of the first gate structure and the second gate structure is located within the U-shaped opening; the first direction is a thickness direction of the substrate.

Description

Semiconductor device, forming method thereof and memory
Technical Field
The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor device, a method of forming the same, and a memory.
Background
The channel structure in the double-gate transistor is generally planar, and the two gate structures are respectively located at the upper side and the lower side of the channel structure, so that although the space utilization rate of each structure in the transistor is high, the volume of the transistor is difficult to further reduce, the contact area between the gate structure and the channel structure is small, and thus, the control capability of the gate structure is weak, and the miniaturization of the semiconductor device is difficult to realize.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a semiconductor device, a method for forming the same, and a memory.
In a first aspect, embodiments of the present disclosure provide a semiconductor device, including:
a substrate;
a first gate structure located on the substrate;
a channel structure covering at least a top surface of the first gate structure and including at least one U-shaped opening toward a first direction;
a second gate structure located on the channel structure and symmetrically arranged with the first gate structure along the first direction; wherein at least one of the first gate structure and the second gate structure is located within the U-shaped opening; the first direction is a thickness direction of the substrate.
In some embodiments, the channel structure includes one of the U-shaped openings;
the first grid structure is arranged on the inner side or the outer side of the U-shaped opening along the first direction, and the second grid structure is arranged on the other side of the U-shaped opening along the first direction.
In some embodiments, the U-shaped opening is oriented toward the substrate;
the first gate structure comprises a first gate conductive layer on the surface of the substrate and a first gate insulating layer covering the top surface and the side surfaces of the first gate conductive layer; the channel structure covers the top surface and the side surface of the first gate insulating layer;
The second gate structure comprises a second gate insulating layer positioned on the surface of the channel structure and a second gate conducting layer positioned on the surface of the second gate insulating layer, wherein the second gate insulating layer is of a linear type or a U-shaped, and an opening of the second gate insulating layer of the U-shaped is away from the substrate.
In some embodiments, the U-shaped opening faces away from the substrate;
the first gate structure comprises a first gate conductive layer positioned in the substrate or on the surface of the substrate and a first gate insulating layer positioned on the surface of the first gate conductive layer; the channel structure covers the top surface of the first gate insulating layer;
the second gate structure includes a second gate insulating layer on an inner surface of the channel structure, and a second gate conductive layer on a surface of the second gate insulating layer.
In some embodiments, the channel structure comprises two of the U-shaped openings;
the first grid structure and the second grid structure are symmetrically arranged in the two U-shaped openings.
In some embodiments, the first gate structure includes a first gate conductive layer on a surface of the substrate, and a first gate insulating layer covering a top surface and sides of the first gate conductive layer; the channel structure covers the top surface and the side surface of the first gate insulating layer;
The second gate structure includes a second gate insulating layer on an inner surface of the channel structure, and a second gate conductive layer on a surface of the second gate insulating layer.
In some embodiments, the semiconductor device further comprises: a source electrode and a drain electrode;
the source electrode and the drain electrode are respectively positioned at two ends of the channel structure along the second direction; the second direction is the length direction of the channel structure.
In a second aspect, embodiments of the present disclosure provide a method for forming a semiconductor device, including:
providing a substrate;
forming a first gate structure on the substrate;
forming a channel structure at least on a top surface of the first gate structure; the channel structure has at least one U-shaped opening facing a first direction;
forming a second gate structure on the channel structure, wherein the second gate structure is symmetrically arranged with the first gate structure along the first direction; wherein at least one of the first gate structure and the second gate structure is located within the U-shaped opening; the first direction is a thickness direction of the substrate.
In some embodiments, forming a first gate structure on the substrate includes:
Forming a first gate conductive layer on the surface or inside the substrate;
forming a first gate insulating layer covering at least a top surface of the first gate conductive layer; the first gate conductive layer and the first gate insulating layer constitute the first gate structure.
In some embodiments, the forming a channel structure at least on a top surface of the first gate structure includes:
forming the channel structure on the top surface of the first gate insulating layer; the channel structure includes a U-shaped opening facing away from the substrate.
In some embodiments, the first gate insulating layer also covers sidewalls of the first gate conductive layer; forming a channel structure at least on a top surface of the first gate structure, comprising:
forming the channel structure on the side wall and the top surface of the first gate insulating layer; the channel structure comprises one U-shaped opening facing the substrate or two U-shaped openings facing the first direction.
In some embodiments, forming a second gate structure on the channel structure, the second gate structure being symmetrically disposed with the first gate structure along the first direction, includes:
forming a second gate insulating layer on a top surface or an inner surface of the channel structure;
Forming a second gate conductive layer on the surface of the second gate insulating layer; the second gate conductive layer and the second gate insulating layer constitute the second gate structure.
In some embodiments, before or after forming the channel structure, the method further comprises:
forming a source electrode and a drain electrode positioned at two ends of the channel structure along the second direction; the second direction is the length direction of the channel structure.
In a third aspect, embodiments of the present disclosure provide a memory, comprising: the semiconductor device described in the above embodiment.
The embodiment of the disclosure provides a semiconductor device, a forming method thereof and a memory, wherein the semiconductor device comprises: a substrate; a first gate structure located on the substrate; a channel structure covering at least a top surface of the first gate structure and including at least one U-shaped opening facing the first direction; the second grid structure is positioned on the channel structure and is symmetrically arranged with the first grid structure along the first direction; wherein at least one of the first gate structure and the second gate structure is located within the U-shaped opening. Because the channel structure at least comprises a U-shaped opening, and at least one grid electrode is arranged in the U-shaped opening, by changing the shape of the channel structure, the contact area of the grid electrode and the channel can be increased, the control capability of the grid electrode is improved, and the channel structure and the grid electrode structure can be arranged on the same layer, so that the size of the double-grid transistor can be reduced, and the semiconductor device is miniaturized.
Drawings
In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.
Fig. 1 to 6 are schematic structural views of a semiconductor device provided in an embodiment of the present disclosure;
fig. 7 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the disclosure;
fig. 8 to 19 are schematic structural views of a semiconductor device in a process of forming the semiconductor device according to the embodiments of the present disclosure;
fig. 20 to 22 are schematic structural views of another semiconductor device in the process of forming the semiconductor device according to the embodiments of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The channel structure in the double-gate transistor is generally planar, and the two gate structures are respectively located at the upper side and the lower side of the channel structure, so that although the space utilization rate of each structure in the transistor is high, the volume of the transistor is difficult to further reduce, the contact area between the gate structure and the channel structure is small, and thus, the control capability of the gate structure is weak, and the miniaturization of the semiconductor device is difficult to realize.
Based on this, the semiconductor device, the forming method thereof and the memory provided by the embodiment of the disclosure, wherein the semiconductor device comprises: a substrate; a first gate structure located on the substrate; a channel structure covering at least a top surface of the first gate structure and including at least one U-shaped opening facing the first direction; the second grid structure is positioned on the channel structure and is symmetrically arranged with the first grid structure along the first direction; wherein at least one of the first gate structure and the second gate structure is located within the U-shaped opening. Because the channel structure at least comprises a U-shaped opening, and at least one grid electrode is arranged in the U-shaped opening, by changing the shape of the channel structure, the contact area of the grid electrode and the channel can be increased, the control capability of the grid electrode is improved, and the channel structure and the grid electrode structure can be arranged on the same layer, so that the size of the double-grid transistor can be reduced, and the semiconductor device is miniaturized.
Hereinafter, a semiconductor device and a method of forming the same in embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Before describing the embodiments of the present disclosure, three directions describing the three-dimensional structure that may be used in the following embodiments are defined, and may include X-axis, Y-axis, and Z-axis directions, for example, in a cartesian coordinate system. The thickness direction of the substrate is defined as a first direction. In the planar direction of the substrate, two directions intersecting each other (e.g., perpendicular to each other) are defined as a second direction and a third direction, for example, a length direction of the channel structure may be defined as the second direction. Here, the first direction may be, for example, an X-axis direction, the second direction may be, for example, a Y-axis direction, and the third direction may be, for example, a Z-axis direction.
Fig. 1 to 6 are schematic structural diagrams of a semiconductor device 100 according to an embodiment of the present disclosure, and as shown in fig. 1 to 6, the semiconductor device 100 includes: a substrate 110; a first gate structure 120 on the substrate 110; a channel structure 130 covering at least a top surface of the first gate structure 120 and including at least one U-shaped opening toward the X-axis direction; the second gate structure 140 is located on the channel structure 130 and is symmetrically arranged with the first gate structure 120 along the X-axis direction; wherein at least one of the first gate structure 120 and the second gate structure 140 is located within the U-shaped opening.
The substrate 110 may be a silicon substrate, a Germanium substrate, a silicon-On-Insulator (Silicon On Insulator, SOI) substrate, a Germanium-On-Insulator (GOI) substrate, or the like; the substrate 110 may also include other elemental or compound semiconductors such as gallium arsenide, indium phosphide, or silicon carbide, among others. In other embodiments, the substrate 110 may also be an ion doped substrate, such as a P-doped substrate or an N-doped substrate.
The first gate structure 120 and the second gate structure 140 are respectively and symmetrically disposed on two sides of the channel structure 130 along the X-axis direction. The first gate structure 120 includes a first gate conductiveLayer 121, and a first gate insulating layer 122 on the surface of first gate conductive layer 121. The second gate structure 140 includes a second gate insulating layer 141, and a second gate conductive layer 142 on a surface of the second gate insulating layer 141. The first gate insulating layer 122 and the second gate insulating layer 141 may be made of a high dielectric constant (HK) material such as hafnium oxide (HfO), or other suitable material such as silicon oxide 2 ) Hafnium silicon oxide (HfSiO) 2 ) Zirconium oxide (ZrO) 2 ) And alumina (Al) 2 O 3 ) The method comprises the steps of carrying out a first treatment on the surface of the The first gate conductive layer 121 and the second gate conductive layer 142 may be made of any material having good conductivity, for example, any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).
It should be noted that the transistor of the semiconductor device 100 in the embodiment of the disclosure is an oxide thin film transistor, and it is understood that the material of the channel structure 130 may include a metal oxide, for example, indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO). In other embodiments, the transistors of semiconductor device 100 may also be conventional silicon-based transistors or other types of transistors.
In some embodiments, referring to fig. 1 to 6, the semiconductor device 100 further includes: a source 151 and a drain 152; the source electrode 151 and the drain electrode 152 are respectively located at both ends of the channel structure 130 in the Y-axis direction.
It should be noted that, in fig. 1 to 5, the top surfaces of the source 151 and the drain 152 are flush with the surface of the channel structure 130, i.e., the dimensions of the source 151 and the drain 152 are the same as those of the channel structure 130 in the X-axis direction; the bottom surface of the channel structure 130 in fig. 6 may also be beyond the bottom surface of the source 151 and drain 152, i.e., the dimensions of the source 151 and drain 152 in the X-axis direction are smaller than the dimensions of the channel structure 130 in the X-axis direction. In other embodiments, the top surfaces of the source 151 and drain 152 may also extend beyond the surface of the channel structure 130.
It should be further noted that, the surface of the source 151 and the drain 152 being flush with the surface of the channel structure 130 means that: the bottom and top surfaces of the source 151 and drain 152 are flush with the bottom and top surfaces of the channel structure 130.
In the embodiment of the disclosure, the channel structure at least comprises a U-shaped opening, and at least one gate is arranged inside the U-shaped opening, so that the channel structure and the gate structure positioned inside the channel structure are arranged on the same layer by changing the shape of the channel structure, thereby reducing the volume of the double-gate transistor and being beneficial to the miniaturization of the semiconductor device.
In addition, since the channel structure 130 has at least one U-shaped opening, i.e., the channel structure 130 is U-shaped or H-shaped, the contact area between the gate insulating layer and the channel structure 130 can be increased, so that the control capability of the transistor gate in the semiconductor device 100 can be improved, and the performance of the semiconductor device can be improved.
In some embodiments, referring to fig. 1 to 6, the channel structure 130 includes one U-shaped opening (i.e., U-shaped) facing the X-axis direction or two U-shaped openings (i.e., H-shaped) facing the X-axis direction; the channel structure 130 in fig. 1 to 4 is U-shaped, and the channel structure 130 in fig. 5 and 6 is H-shaped. Specifically, the channel structure 130 in fig. 1 and 2 has one U-shaped opening towards the substrate 110, the channel structure 130 in fig. 3 and 4 has one U-shaped opening away from the substrate 110, the channel structure 130 in fig. 5 and 6 has one U-shaped opening towards the substrate 110 and one U-shaped opening away from the substrate 110, i.e. the channel structure 130 in fig. 5 and 6 has two U-shaped openings.
In some embodiments, when the channel structure 130 includes a U-shaped opening, the first gate structure 120 is disposed on the inner side or the outer side of the U-shaped opening along the X-axis direction, and the second gate structure 140 is disposed on the other side of the U-shaped opening along the X-axis direction.
In some embodiments, with continued reference to fig. 1 and 2, the u-shaped opening is oriented toward the substrate 110; the first gate structure 120 includes a first gate conductive layer 121 on a surface of the substrate 110, and a first gate insulating layer 122 covering a top surface and sides of the first gate conductive layer 121; the channel structure 130 covers the top surface and sides of the first gate insulating layer 122; the second gate structure 140 includes a second gate insulating layer 141 located on a surface of the channel structure 130, and a second gate conductive layer 142 located on a surface of the second gate insulating layer 141, where the second gate insulating layer 141 is linear (as shown in fig. 1) or U-shaped (as shown in fig. 2), and an opening of the U-shaped second gate insulating layer 141 faces away from the substrate 110.
Specifically, referring to fig. 1, the first gate structure 120 is disposed inside the U-shaped opening of the channel structure 130, and the second gate structure 140 is disposed outside the U-shaped opening of the channel structure 130; the first gate insulating layer 122 is located on the inner side surface of the channel structure 130, that is, the first gate insulating layer 122 has a U-shaped opening facing the substrate, and the first gate conductive layer 121 is located inside the U-shaped opening of the first gate insulating layer 122 and fills the U-shaped opening of the first gate insulating layer 122; the second gate insulating layer 141 covers the top surface of the channel structure 130, and the second gate insulating layer 141 is linear, and the second gate conductive layer 142 is located on the surface of the second gate insulating layer 141.
Referring to fig. 2, the first gate structure 120 is disposed inside the U-shaped opening of the channel structure 130, and the second gate structure 140 is disposed outside the U-shaped opening of the channel structure 130; the first gate insulating layer 122 is located on the inner surface of the channel structure 130, that is, the first gate insulating layer 122 has a U-shaped opening facing the substrate 110, and the first gate conductive layer 121 is located inside the U-shaped opening of the first gate insulating layer 122 and fills the U-shaped opening of the first gate insulating layer 122; the second gate insulating layer 141 is located on the outer top surface of the channel structure 130, and the second gate insulating layer 141 has a U-shaped opening facing away from the substrate 110; the second gate conductive layer 142 is located inside the U-shaped opening of the second gate insulating layer 141 and fills the U-shaped opening of the second gate insulating layer 141.
In some embodiments, referring still to fig. 2, the semiconductor device 100 further includes a dielectric layer 160 on the surface of the source 151 and the drain 152 and between two adjacent transistors. It should be noted that in the embodiment of the present disclosure, only one transistor is shown, and only the dielectric layer 160 on the surfaces of the source 151 and the drain 152 is shown.
In some embodiments, please continue to refer to fig. 3 and 4,U type openings facing away from the substrate 110; the first gate structure 120 includes a first gate conductive layer 121 located in the substrate 110 (as shown in fig. 3) or on the surface of the substrate 110 (as shown in fig. 4), and a first gate insulating layer 122 located on the surface of the first gate conductive layer 121; the channel structure 130 covers the top surface of the first gate insulating layer 122; the second gate structure 140 includes a second gate insulating layer 141 on an inner surface of the channel structure 130, and a second gate conductive layer 142 on a surface of the second gate insulating layer 141.
Specifically, referring to fig. 3, the first gate structure 120 is disposed outside the U-shaped opening of the channel structure 130, and the second gate structure 140 is disposed inside the U-shaped opening of the channel structure 130; the first gate conductive layer 121 is located in the substrate 110, and the first gate insulating layer 122 covers at least a surface of the first gate conductive layer 121; the channel structure 130 covers the top surface of the first gate insulating layer 122; the second gate insulating layer 141 is located on the inner surface of the channel structure 130, i.e. the second gate insulating layer 141 has a U-shaped opening facing away from the substrate 110, and the second gate conductive layer 142 is located inside the U-shaped opening of the second gate insulating layer 141 and fills the U-shaped opening of the second gate insulating layer 141.
Note that, the channel structure 130 covering the top surface of the first gate insulating layer 122 means that: the channel structure 130 covers the first gate insulating layer 122 on the surface of the first gate conductive layer 121.
Referring to fig. 4, the first gate structure 120 is disposed outside the U-shaped opening of the channel structure 130, and the second gate structure 140 is disposed inside the U-shaped opening of the channel structure 130; the first gate insulating layer 122 is located on the outer surface of the channel structure 130, and the first gate insulating layer 122 has a U-shaped opening facing the substrate 110; the first gate conductive layer 121 is located inside the U-shaped opening of the first gate insulating layer 122 and fills the U-shaped opening of the second gate insulating layer 141; the second gate insulating layer 141 is located on the inner surface of the channel structure 130, i.e. the second gate insulating layer 141 has a U-shaped opening facing away from the substrate, and the second gate conductive layer 142 is located inside the U-shaped opening of the second gate insulating layer 141 and fills the U-shaped opening of the second gate insulating layer 141.
In some embodiments, referring still to fig. 4, semiconductor device 100 further includes a dielectric layer 160 between source 151 and substrate 110, drain 152 and substrate 110, and between two adjacent transistors.
In some embodiments, referring to fig. 5 and 6, the channel structure 130 includes two U-shaped openings; the first gate structure 120 and the second gate structure 140 are symmetrically disposed inside the two U-shaped openings.
In some embodiments, referring to fig. 5 and 6, the first gate structure 120 includes a first gate conductive layer 121 on a surface of the substrate 110, and a first gate insulating layer 122 covering a top surface and sides of the first gate conductive layer 121; the channel structure 130 covers the top surface and sides of the first gate insulating layer 122; the second gate structure 140 includes a second gate insulating layer 141 on an inner surface of the channel structure 130, and a second gate conductive layer 142 on a surface of the second gate insulating layer 141.
Specifically, referring to fig. 5, the first gate structure 120 and the second gate structure 140 are both located inside the U-shaped opening of the channel structure 130, and the channel structure 130 is located on the surface of the substrate 110. The first gate insulating layer 122 is at least located on the inner side surface of the channel structure 130 facing the U-shaped opening of the substrate 110, i.e. the first gate insulating layer 122 also has a U-shaped opening facing the substrate 110, and the first gate conductive layer 121 is located inside the U-shaped opening of the first gate insulating layer 122 and fills the U-shaped opening of the first gate insulating layer 122; the second gate insulating layer 141 is located on an inner side surface of the channel structure 130 facing away from the U-shaped opening of the substrate 110, i.e. the second gate insulating layer 141 also has a U-shaped opening facing away from the substrate 110, and the second gate conductive layer 142 is located inside the U-shaped opening of the second gate insulating layer 141 and fills the U-shaped opening of the second gate insulating layer 141.
With continued reference to fig. 5, the dimensions of the source 151 and the drain 152 in the X-axis direction are equal to the dimensions of the channel structure 130 in the X-axis direction, so that the source 151 and the drain 152 have a larger contact area with the channel structure 130, and the contact resistance is reduced.
With continued reference to fig. 6, the first gate structure 120 and the second gate structure 140 are both located inside the U-shaped opening of the channel structure 130, and the first gate structure 120 and a portion of the channel structure 130 are located in the substrate 110. The first gate insulating layer 122 is at least located on the inner side surface of the channel structure 130 facing the U-shaped opening of the substrate 110, i.e. the first gate insulating layer 122 also has a U-shaped opening facing the substrate 110, and the first gate conductive layer 121 is located inside the U-shaped opening of the first gate insulating layer 122 and fills the U-shaped opening of the first gate insulating layer 122; the second gate insulating layer 141 is located on an inner side surface of the channel structure 130 facing away from the U-shaped opening of the substrate 110, i.e. the second gate insulating layer 141 also has a U-shaped opening facing away from the substrate 110, and the second gate conductive layer 142 is located inside the U-shaped opening of the second gate insulating layer 141 and fills the U-shaped opening of the second gate insulating layer 141.
With continued reference to fig. 6, the source 151 and the drain 152 are respectively located at two ends of the channel structure 130 along the Y-axis direction, and the dimensions of the source 151 and the drain 152 along the X-axis direction are smaller than those of the channel structure 130 along the X-axis direction.
Since the first gate structure 120 and the partial channel structure 130 are located in the substrate 110, the total height of the transistor in the X-axis direction can be reduced, thereby realizing miniaturization of the semiconductor device.
Fig. 7 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure, and fig. 8 to 19 are schematic structural diagrams during the formation of the semiconductor device according to an embodiment of the present disclosure, where fig. 8 to 13 correspond to the formation of the semiconductor device 100 in fig. 1 according to an embodiment of the present disclosure; fig. 15 to 19 correspond to a forming process of the semiconductor device 100 in fig. 3 according to the embodiment of the present disclosure.
As shown in fig. 7, the method of forming the semiconductor device 100 includes the steps of: step S101 to step S104.
First, referring to fig. 7 and 8, step S101 is performed to provide a substrate 110.
Next, referring to fig. 7 to 9, in step S102, a first gate structure 120 is formed on the substrate 110.
In some embodiments, step S102 may include: forming a first gate conductive layer 121 on the surface or inside of the substrate 110; forming a first gate insulating layer 122 covering at least a top surface of the first gate conductive layer 121; the first gate conductive layer 121 and the first gate insulating layer 122 constitute the first gate structure 120.
In practice, a first gate conductive material may be deposited on the surface of the substrate 110 to form a first gate conductive layer 121 as shown in fig. 8, and a first gate insulating material may be deposited on the surface of the first gate conductive layer 121 and the surface of the substrate 110 to form a first gate insulating layer 122 having a U-shaped opening facing the substrate 110, where the first gate conductive layer 121 and the first gate insulating layer 122 form a first gate structure 120 as shown in fig. 9.
In other embodiments, the substrate 110 may be etched to form an etched opening (not shown) filled with a first gate conductive material to form a first gate conductive layer 121 embedded in the substrate 110 (as shown in fig. 15), and a top surface of the first gate conductive layer 121 may be flush with a top surface of the substrate 110. Next, a first gate insulating layer 122 as shown in fig. 16 is formed on the top surfaces of the substrate 110 and the first gate conductive layer 121. Wherein the first gate conductive layer 121 and the first gate insulating layer 122 constitute the first gate structure 120 as shown in fig. 16.
It should be noted that, in the embodiment of the present disclosure, the effective area in the first gate insulating layer 122 is only located at the portion contacting the first gate conductive layer 121, so that the forming steps of the semiconductor device are simplified, and the first gate insulating layer 122 located on the surface of the substrate 110 is not removed in the embodiment of the present disclosure. In other embodiments, the first gate insulating layer 122 located on the surface of the substrate 110 may also be removed.
Next, referring to fig. 7, 10 to 12, step S103 is performed to form a channel structure 130 at least on the top surface of the first gate structure 120; the channel structure 130 has at least one U-shaped opening facing the X-axis direction.
In some embodiments, step S103 may include: forming a channel structure 130 on sidewalls and a top surface of the first gate insulating layer 122; the channel structure 130 includes one U-shaped opening toward the substrate 110 or two U-shaped openings toward the X-axis direction.
In practice, channel material is deposited on the top surface and sidewalls of the first gate insulation layer 122, forming an initial channel structure 130a as shown in fig. 10; the initial channel structure 130a is etched, and the initial channel structure 130a located outside the effective region of the first gate insulating layer 122 is removed, forming a U-shaped channel structure 130 as shown in fig. 11, wherein the channel material may be IGZO.
In some embodiments, referring to fig. 11 and 12, after forming the channel structure 130, the method for forming the semiconductor device 100 further includes: the source 151 and the drain 152 are formed at both ends of the channel structure 130 in the Y-axis direction.
In implementation, a source-drain material is deposited on the surfaces of the channel structure 130 and the first gate insulating layer 122, so as to form an initial source-drain 150a as shown in fig. 11; the initial source drain 150a is etched back until the top surface of the channel structure 130 is exposed, forming a source 151 and a drain 152 as shown in fig. 12. The source/drain electrode material may be any suitable metal material.
It should be noted that the surfaces of the source 151 and the drain 152 may be flush with the top surface of the channel structure 130 (as shown in fig. 12) or may extend beyond the top surface of the channel structure 130.
In other embodiments, after forming the source electrode 151 and the drain electrode 152, the forming method of the semiconductor device 100 further includes: a dielectric layer 160 is formed between adjacent two transistors at the top surfaces of the source 151 and drain 152 as shown in fig. 14. In this way, the second gate structure 140 as shown in fig. 2 may be subsequently formed. The material of the dielectric layer 160 may be any suitable material, for example, silicon oxide, silicon nitride, or silicon oxynitride.
In some embodiments, the step S103 may include: forming a channel structure 130 on a top surface of the first gate insulating layer 122; channel structure 130 includes a U-shaped opening facing away from substrate 110.
In implementation, first, a source/drain material is deposited to cover the surface of the first gate insulating layer 122, and an initial source/drain 150a is formed as shown in fig. 17. The initial source/drain 150a is etched to form an etched recess and source 151 and drain 152 as shown in fig. 18. Next, an initial channel structure 130a is formed to cover at least the surfaces of the source electrode 151, the drain electrode 152, and the top surface of the first gate insulating layer 122 (as shown in fig. 18); the initial channel structure 130a on the top surfaces of the source 151 and drain 152 is removed, forming the channel structure 130 as shown in fig. 19. Wherein the channel structure 130 has at least one U-shaped opening facing away from the substrate. In this way, the second gate structure 140 as shown in fig. 3 and 4 may be formed.
Finally, referring to fig. 7 and 13, step S104 is performed to form a second gate structure 140 disposed symmetrically to the first gate structure 120 along the X-axis direction on the channel structure 130; wherein at least one of the first gate structure 120 and the second gate structure 140 is located within the U-shaped opening.
In some embodiments, forming the second gate structure 140 symmetrically disposed with the first gate structure 120 along the X-axis direction on the channel structure 130 includes: forming a second gate insulating layer 141 on a top surface or an inner surface of the channel structure 130; forming a second gate conductive layer 142 on a surface of the second gate insulating layer 141; the second gate conductive layer 142 and the second gate insulating layer 141 constitute the second gate structure 140.
In implementation, a second gate insulating material is deposited on the exposed surfaces of the source electrode 151, the drain electrode 152 and the channel structure 130 to form a linear second gate insulating layer 141 as shown in fig. 13, a second gate conductive material is deposited on the surface of the second gate insulating layer 141 to form a second gate conductive layer 142 as shown in fig. 13, and the second gate insulating layer 141 and the second gate conductive layer 142 form the second gate structure 140.
It should be noted that, in other embodiments, if the dielectric layer 160 (as shown in fig. 19) located on the top surfaces of the source 151 and the drain 152 and between the adjacent two transistors is formed, a second gate insulating material may be deposited on the exposed surfaces of the dielectric layer 160 and the channel structure 130 to form a U-shaped second gate insulating layer 141, and a second gate conductive layer 142 may be formed in the U-shaped second gate insulating layer 141 (as will be understood with reference to fig. 2).
In some embodiments, when forming the semiconductor structure shown in fig. 3 or 4, after forming the channel structure, a second gate insulating material is deposited on the exposed surfaces of the source electrode 151, the drain electrode 152, and the channel structure 130, forming a U-shaped second gate insulating layer 141 as shown in fig. 3 or 4, a second gate conductive material is deposited inside the U-shaped second gate insulating layer 141, forming a second gate conductive layer 142, and the second gate insulating layer 141 and the second gate conductive layer 142 constitute the second gate structure 140 as shown in fig. 3 or 4.
Note that the effective region in the second gate insulating layer 141 is only located at a portion in contact with the channel structure 130, and thus, in order to simplify the formation steps of the semiconductor device, the second gate insulating layer 141 located at the top surfaces of the source and drain electrodes 151 and 152 is not removed in the embodiments of the present disclosure, for saving costs.
In the embodiments of the present disclosure, the first gate insulating material and the second gate insulating material may be formed of a high dielectric constant material or other suitable materials such as silicon oxide, and the high dielectric constant material may include hafnium oxide, hafnium silicon oxide, zirconium oxide and aluminum oxide; the first gate conductive material and the second gate conductive material may be any material with good conductivity, for example, any one of titanium, titanium nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper.
It should be noted that, the semiconductor device formed in the embodiment of the present disclosure is similar to the semiconductor device in the above embodiment, and for the technical features that are not disclosed in detail in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and a detailed description is omitted here.
The semiconductor device formed by the method for forming the semiconductor device provided by the embodiment of the disclosure has the channel structure with the U-shaped opening, and the grid electrode is arranged in the U-shaped opening, so that the contact area of the grid electrode and the channel can be increased, the control capability of the grid electrode is improved, the channel structure and the grid electrode structure positioned in the channel structure are arranged in the same layer, the size of the double-grid transistor can be reduced, and further the miniaturization of the semiconductor device is facilitated.
The embodiment of the present disclosure further provides another method for forming a semiconductor device, please refer to fig. 7, 20 to 22 for a detailed description of the forming process of the semiconductor device 100 in fig. 6.
First, referring to fig. 7 and 20, step S101 is performed to provide a substrate 110.
Next, referring to fig. 7, 20 and 21, in step S102, a first gate structure 120 is formed on the substrate 110.
In some embodiments, step S102 may include: forming a first gate conductive layer 121 outside or inside the substrate 110; forming a first gate insulating layer 122 covering a top surface of the first gate conductive layer 121; the first gate conductive layer 121 and the first gate insulating layer 122 constitute the first gate structure 120. Wherein the first gate conductive layer 121 may be buried in the substrate 110.
In practice, the substrate 110 may be etched to form an etched opening, and the etched opening is filled with a first gate conductive material to form a first gate conductive layer 121 (as shown in fig. 20) embedded in the substrate 110, where a top surface of the first gate conductive layer 121 is lower than a top surface of the substrate 110, and a gap is formed between a sidewall of the first gate conductive layer 121 and the substrate 10; a first gate insulating layer 122 as shown in fig. 21 is formed on the sidewall and top surface of the first gate conductive layer 121, wherein the first gate conductive layer 121 and the first gate insulating layer 122 constitute a first gate structure 120 as shown in fig. 21.
In other embodiments, the first gate structure may be formed on the surface of the substrate, and the specific travel process is understood with reference to the above embodiments, which is not described herein again.
Next, referring to fig. 7, 21 and 22, step S103 is performed to form a channel structure 130 at least on the top surface of the first gate structure 120; the channel structure 130 has at least one U-shaped opening facing the X-axis direction.
The embodiment of the present disclosure is described taking the case that the channel structure 130 has two U-shaped openings toward the X-axis direction, that is, the channel structure 130 is H-shaped.
In practice, first, a U-shaped channel structure 130b as shown in fig. 21 is formed between the first gate insulating layer 122 and the substrate 110.
Next, referring to fig. 22, after forming the U-shaped channel structure 130b, the forming method of the semiconductor device 100 further includes: the source electrode 151 and the drain electrode 152 are formed on the surface of the substrate 110 in the X-axis direction.
Finally, a channel material is deposited on the top surface of the first gate insulating layer 122 and on the sidewalls of the source 151 and drain 152, forming a U-shaped channel structure 130c as shown in fig. 22. The U-shaped channel structure 130b and the U-shaped channel structure 130c constitute an H-shaped channel structure 130 as shown in fig. 22.
Finally, referring to fig. 7 and 6, step S104 is performed to form a second gate structure 140 disposed symmetrically to the first gate structure 120 along the X-axis direction on the channel structure 130; wherein at least one of the first gate structure 120 and the second gate structure 140 is located within the U-shaped opening.
In practice, a second gate insulating material is deposited on the exposed surface of the channel structure 130 (i.e., the inner side surface of the U-shaped channel structure 130 c), forming a U-shaped second gate insulating layer 141 as shown in fig. 6, and a second gate conductive material is deposited inside the U-shaped second gate insulating layer 141, forming a second gate conductive layer 142, where the second gate insulating layer 141 and the second gate conductive layer 142 form a second gate structure 140 as shown in fig. 6.
It should be further noted that, the semiconductor device formed in the embodiment of the present disclosure is similar to the semiconductor device in the above embodiment, and for the technical features that are not disclosed in detail in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and a detailed description is omitted here.
The semiconductor device formed by the method for forming the semiconductor device provided by the embodiment of the disclosure has the channel structure with the two U-shaped openings, and the two grids are respectively arranged in the U-shaped openings, so that the contact area of the grid and the channel can be increased, the control capability of the grid can be improved, and the channel structure and the grid structure can be arranged on the same layer by changing the shape of the channel structure, thereby reducing the volume of the double-grid transistor and being beneficial to the miniaturization of the semiconductor device.
In addition, the embodiments of the present disclosure further provide a memory, please continue to refer to fig. 1 to 6, the memory includes the semiconductor device 100 in the above embodiments, the semiconductor device 100 includes: a substrate 110; a first gate structure 120 on the substrate 110; a channel structure 130 covering at least a top surface of the first gate structure 120 and including at least one U-shaped opening toward the X-axis direction; the second gate structure 140 is located on the channel structure 130 and is symmetrically arranged with the first gate structure 120 along the X-axis direction; wherein at least one of the first gate structure 120 and the second gate structure 140 is located within the U-shaped opening.
In some embodiments, the memory may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), and for DRAM, it may not only conform to the memory specifications of Double Data Rate (DDR), DDR2, DDR3, DDR4, DDR5, etc., but also conform to the memory specifications of low power Double Data Rate SDRAM (Low Power Double Data Rate SDRAM, LPDDR), LPDDR2, LPDDR3, LPDDR4, LPDDR5, etc., without any limitation herein.
In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.
Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.
The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
a first gate structure located on the substrate;
a channel structure covering at least a top surface of the first gate structure and including at least one U-shaped opening toward a first direction;
a second gate structure located on the channel structure and symmetrically arranged with the first gate structure along the first direction; wherein at least one of the first gate structure and the second gate structure is located within the U-shaped opening; the first direction is a thickness direction of the substrate.
2. The semiconductor device of claim 1, wherein said channel structure comprises one of said U-shaped openings;
the first grid structure is arranged on the inner side or the outer side of the U-shaped opening along the first direction, and the second grid structure is arranged on the other side of the U-shaped opening along the first direction.
3. The semiconductor device of claim 2, wherein the U-shaped opening is oriented toward the substrate;
the first gate structure comprises a first gate conductive layer on the surface of the substrate and a first gate insulating layer covering the top surface and the side surfaces of the first gate conductive layer; the channel structure covers the top surface and the side surface of the first gate insulating layer;
the second gate structure comprises a second gate insulating layer positioned on the surface of the channel structure and a second gate conducting layer positioned on the surface of the second gate insulating layer, wherein the second gate insulating layer is of a linear type or a U-shaped, and an opening of the second gate insulating layer of the U-shaped is away from the substrate.
4. The semiconductor device of claim 2, wherein the U-shaped opening faces away from the substrate;
the first gate structure comprises a first gate conductive layer positioned in the substrate or on the surface of the substrate and a first gate insulating layer positioned on the surface of the first gate conductive layer; the channel structure covers the top surface of the first gate insulating layer;
the second gate structure includes a second gate insulating layer on an inner surface of the channel structure, and a second gate conductive layer on a surface of the second gate insulating layer.
5. The semiconductor device of claim 2, wherein the channel structure comprises two of the U-shaped openings;
the first grid structure and the second grid structure are symmetrically arranged inside the two U-shaped openings,
the first gate structure comprises a first gate conductive layer on the surface of the substrate and a first gate insulating layer covering the top surface and the side surfaces of the first gate conductive layer; the channel structure covers the top surface and the side surface of the first gate insulating layer;
the second gate structure includes a second gate insulating layer on an inner surface of the channel structure, and a second gate conductive layer on a surface of the second gate insulating layer.
6. A method of forming a semiconductor device, the method comprising:
providing a substrate;
forming a first gate structure on the substrate;
forming a channel structure at least on a top surface of the first gate structure; the channel structure has at least one U-shaped opening facing a first direction;
forming a second gate structure on the channel structure, wherein the second gate structure is symmetrically arranged with the first gate structure along the first direction; wherein at least one of the first gate structure and the second gate structure is located within the U-shaped opening; the first direction is a thickness direction of the substrate.
7. The method of claim 6, wherein forming a first gate structure on the substrate comprises:
forming a first gate conductive layer on the surface or inside the substrate;
forming a first gate insulating layer covering at least a top surface of the first gate conductive layer; the first gate conductive layer and the first gate insulating layer constitute the first gate structure,
forming a channel structure at least on a top surface of the first gate structure, comprising:
forming the channel structure on the top surface of the first gate insulating layer; the channel structure includes a U-shaped opening facing away from the substrate.
8. The method of claim 7, wherein the first gate insulating layer also covers sidewalls of the first gate conductive layer; forming a channel structure at least on a top surface of the first gate structure, comprising:
forming the channel structure on the side wall and the top surface of the first gate insulating layer; the channel structure comprises one U-shaped opening facing the substrate or two U-shaped openings facing the first direction.
9. The method of claim 7 or 8, wherein forming a second gate structure on the channel structure that is symmetrically disposed with respect to the first gate structure along the first direction, comprises:
Forming a second gate insulating layer on a top surface or an inner surface of the channel structure;
forming a second gate conductive layer on the surface of the second gate insulating layer; the second gate conductive layer and the second gate insulating layer constitute the second gate structure.
10. A memory comprising the semiconductor device according to any one of claims 1 to 5.
CN202310466245.2A 2023-04-26 2023-04-26 Semiconductor device, forming method thereof and memory Pending CN116632050A (en)

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CN202310466245.2A CN116632050A (en) 2023-04-26 2023-04-26 Semiconductor device, forming method thereof and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310466245.2A CN116632050A (en) 2023-04-26 2023-04-26 Semiconductor device, forming method thereof and memory

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CN116632050A true CN116632050A (en) 2023-08-22

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