JP2001085484A - Method of evaluating trap of semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evaluate, at room temperature, the level of a deep trap existing in a wide band gap semiconductor. SOLUTION: C-V measurement is performed using a C-V measuring apparatus 10, while irradiating a semiconductor sample 15 with a single-wavelength light 18 produced by spectral diffraction of the light from a white light source, and the level of a deep trap is evaluated from the measurement result. According to this method, the level of a deep trap can be evaluated even at room temperature, and this can also be utilized for the evaluation aiming at performance improvement of the semiconductor device, using a wide band gap.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a trap level of a semiconductor, and more particularly to a method for evaluating a trap level density existing at a deep level in a wide band gap semiconductor having a forbidden band of 2.0 eV or more. The present invention relates to a trap evaluation method suitable for the above.

[0002]

2. Description of the Related Art MOSFETs using silicon carbide (SiC)
In forming a structure (hereinafter, referred to as a silicon carbide MOS structure), if an oxide film is formed by thermal oxidation, carbon remains inside the oxide film and at the interface between the oxide film and silicon carbide. Reoxidation Annealing, LA Lipkin et
al., Material Science Forum Vols. 264-268 shows that the reoxidation heat treatment has the effect of reducing the fixed charge density and the interface state density of the p-type silicon carbide MOS structure. According to the study of the present inventors, the effect of this re-oxidation heat treatment was found to be due to the fact that the residual carbon existing inside the oxide film and at the interface between the oxide film and silicon carbide was significantly reduced. Also, the re-oxidation heat treatment that was effective for the p-type silicon carbide MOS structure has no effect in the n-type silicon carbide MOS structure, and is a treatment for increasing the number of electron traps. It has been found that the cause is SiNx, which is a bonding state between nitrogen as a dopant and silicon.

[0003] Accordingly, the present applicant has proposed an M
Japanese Patent Application No. 11-140681 filed an OSFET that realizes a reduction in the trap level at the MOS interface and a high reliability of the gate oxide film. That, SiNx structure described above, since with respect to an O ₂ atmosphere is extremely unstable, by after reoxidation heat treatment heat treatment is performed in an O ₂ atmosphere to remove the SiNx structure as an electron trap. As a result of this treatment, the interface state density was on the order of 10 ¹⁰ cm ^-2 eV ^-1 , and the life of the oxide film was greatly extended.

As described above, by performing the re-oxidation heat treatment after the thermal oxidation and the heat treatment in the O ₂ atmosphere, the interface state of the n-type silicon carbide MOS structure can be extremely improved. In this case, as the evaluation method, CV measurement, conductance method, or the like can be used. However, in these measurement methods, since traps existing at energy that can be thermally excited are evaluated, only traps at a shallow level from the conduction band or valence band to about 0.6 eV can be evaluated in room temperature measurement. It is.

In order to evaluate a deep level trap,
In order to make deep-level traps capable of being thermally excited,
It is necessary to keep a sample having a MOS structure in a high temperature state. For example, in the case of silicon carbide, the sample temperature is set to 200 ° C.
It is necessary to do above.

However, in this case, a current due to heat release and a tunnel current for tunneling through an oxide film become large, and accurate evaluation cannot be performed by the above-described measuring method using electrical characteristics.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an evaluation method capable of evaluating deep-level traps at room temperature.

[0008]

In order to achieve the above object, the invention according to claim 1 is characterized in that trapped carriers are excited by light irradiation to evaluate a trap level of a semiconductor.

By irradiating light, carriers of deep level traps can be excited, so that deep level traps can be evaluated even at room temperature.

The invention according to claim 2 is characterized in that CV measurement is performed while irradiating a semiconductor having an internal capacitance with light, and the trap level is evaluated based on the measurement result.

In the present invention, irradiation of light excites the carriers of the traps at a deep level, thereby causing C-
It is characterized in that the trap level is evaluated by performing V measurement.

In this case, specifically, the carrier trapped at a deep level is temporarily determined as a fixed charge density based on the measurement result of the CV measurement as in the invention according to the third aspect, and is determined by light irradiation. The amount of change can be evaluated as a trap density due to a deep level.

In the CV measurement, a DC voltage is applied to one electrode formed on the semiconductor in a state where the semiconductor is irradiated with light, and the DC voltage is applied to the semiconductor. It can be performed by changing the voltage. In this case, it is preferable to apply an AC voltage to the other electrode formed on the semiconductor as in the invention described in claim 5.

It is preferable that the above-mentioned light is light of a single wavelength, and the light is as follows.
As in the invention according to claim 7, light after using a white light as a light source and using a spectroscope can be used.

Further, it is desirable that the photon energy of the light be smaller than the forbidden band of the semiconductor as in the invention described in claim 8.

The trap evaluation method according to each of the above-mentioned claims is particularly effective when applied to a semiconductor having a forbidden band of 2.0 eV or more as in the ninth invention.

It is to be noted that, as the above-mentioned semiconductor, claim 9
, Pn, pn
Having a junction, having a Schottky junction, having a hetero junction, having a semiconductor substrate made of silicon carbide, having a semiconductor substrate made of gallium nitride, having a heterojunction of silicon carbide having different crystal systems And a material having a heterojunction between gallium nitride and aluminum nitride.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 1 shows a trap evaluation apparatus for evaluating traps of a wide band gap semiconductor. A capacitance (capacitance) with respect to an applied voltage of a semiconductor sample (hereinafter, simply referred to as a sample) 15 is measured using a CV measuring device 10. The capacity measurement includes a quasi-static capacity (hereinafter referred to as CQ) using only the DC power supply 12 and a Hi-Frequency capacity (hereinafter referred to as CH) using the AC power supply 13 together.

In the measuring method according to this embodiment, CQ is mainly measured. For detection of CQ and CH, an integrator 11 to which a reference signal 14 is input from an AC power supply 13 is used.
The capacity is detected from the integrated value of the direct current and the alternating current.
At the time of measuring CQ and CH, the sample 15 is irradiated with the single-wavelength light 18. As the single-wavelength light 18, a white light source represented by a tungsten lamp, which is separated by a spectroscope, can be used.

Hereinafter, the principle of evaluation when the silicon carbide MOS structure shown in FIG. 2 is used as sample 15 for which trap evaluation can be performed by this measurement will be described. The silicon carbide MOS structure shown in FIG. 2 has an n-type 4H-SiC substrate 20.
An oxide film 21 is formed thereon by thermal oxidation, a gate electrode 24 is formed thereon, and an ohmic electrode 23 is formed on the back surface of the substrate 20.

FIG. 3 shows the behavior of the trapped carriers when the silicon carbide MOS structure is irradiated with single-wavelength light of wavelength λ. A single-wavelength light having a wavelength λ has E (λ) =
Since it has the energy of 1239.9 / λ (eV), the single-wavelength light 18 is irradiated from the oxide film 21 side in the MOS lateral structure, so that the conduction band and the valence band move inward from the conduction band and the valence band. , E (λ) are excited. Naturally, when E (λ) is smaller than the energy of the band gap, an excitable energy band exists in the band gap, and therefore, in an ideal sample, there is no carrier actually excited (exciton). Some excited states may exist, such as, but in these excited states, electron-hole pairs exist,
Since it does not contribute as a current, it does not appear in the evaluation according to the present invention).

As described above, in the band diagram shown in FIG. 3, carriers excited by irradiation with the single-wavelength light 18 having the wavelength λ are trapped by trap levels (such as structural traps and traps due to crystal defects). Carriers (electrons, holes). By fixing the wavelength of the single-wavelength light 18 to λ, the energy of E (λ) is automatically fixed, and only electrons or holes trapped in the excitable region in FIG. 3 are excited.

In this embodiment, CV measurement is performed while irradiating the single wavelength light 18. Specifically, a DC voltage is applied from the DC power supply 12 to one electrode 23 of the sample 15, and an AC voltage is applied from the AC power supply 13 to the other electrode 24.
Then, while the portion having the internal capacitance is continuously irradiated from the oxide film 21 side to the single-wavelength light 18, the magnitude of the DC voltage is changed, and the DC current and the AC current flowing according to the change in the DC voltage are changed. Detection is performed using the integrator 11, and the internal capacity of the sample 15 is detected from the detected current value.

Here, by continuously irradiating the single-wavelength light 18, even if the sample 15 is under any bias by the DC power supply 12, electrons and holes in a region corresponding to E (λ) are excited. Continue to be. In other words, the same effect as in the normal thermally excited state can be achieved, and unlike the case where the temperature of the sample is high, the energy of the trap to be excited is specified very accurately because the excitation is performed by light of a specific wavelength. can do. This is because in the case of thermal excitation, the energy to be excited has an uncertainty of about kT (k is Boltzmann's constant, T is temperature expressed in Kelvin).

FIG. 4 shows the definition of the notation of the interface state density and the fixed charge density in the silicon carbide MOS structure. In the MOS structure, the fixed charge densities of the positive and negative charges are N
(+) And N (-). The interface state densities of deep levels of positive and negative charges (about 0.5 eV or more from the conduction band and the valence band) are defined as n (+) and n (−), respectively. in this case,
The apparent fixed charge before irradiating the single-wavelength light 18 is
Expression 1 is obtained, and apparent fixed charges held in the depletion region and the accumulation region are expressed by Expressions 2 and 3.

[0027]

## EQU1 ## Apparent fixed charge in initial state = N
(+) + N (+)-N (-)-n (-)

[0028]

## EQU2 ## Apparent fixed charge in depletion region = N
(+) + N (+)-N (-)-n (-) (λ)

[0029]

## EQU3 ## Apparent fixed charge in the accumulation region = N
(+) + N (+) (λ) −N (−) − n (−) Here, n (−) (λ) and n (+) (λ) represent the single wavelength light 18 having the wavelength λ, respectively. It indicates the interface state density remaining at the interface when the irradiation is performed.

FIG. 5 shows the behavior of trapped electrons and holes when the single-wavelength light 18 is irradiated with a constant gate voltage applied. When the single-wavelength light 18 is irradiated, both electrons and holes are excited.

Here, the electrons excited in the depletion region are discharged to the substrate 20 side by the electric field of the depletion layer, but the excited holes are regenerated by the electric field of the depletion layer to SiO ₂ / Si.
It is attracted to the C interface and is trapped at the interface. Also,
When a gate voltage is applied to the accumulation region, the trap that has discharged electrons due to the electrons accumulated at the interface traps the electrons again.

On the other hand, holes exhibit different behavior from electrons. Holes excited by single-wavelength light irradiation in the accumulation region are discharged to the substrate 20 side, and electrons remain the same until the state of being trapped at the interface is maintained, but a gate voltage is applied to the depletion region. In such a case, it is almost negligible that the trap that has discharged holes recaptures holes. This is because the n-type substrate has a very low probability of generating holes (and has no source / drain electrodes), and the carrier concentration is higher than that of Si (in a thermal equilibrium state).

[0033]

## EQU4 ## Hole concentration in 4HSiC = hole concentration of Si ×
｛Exp (-Eg4HSiC / kT) / exp (-Eg
Si / kT)｝ ² (ie, n-type 4 in a thermal equilibrium state at room temperature)
The hole concentration in H-SiC is about 1 / 10-1 / 75 of that of Si.
This is because holes are not induced even in the depletion region. Here, in Equation 4, Eg4HSiC is 4H
-SiC band gap (3.25 eV), EgSi
Is the band gap of Si (1.12 eV), and the effective mass of holes is approximately the same for SiC and Si. Thus, when holes are excited and ejected by irradiation of the single wavelength light 18, the trap remains empty. That is, a memory effect is obtained. However, when light having an energy larger than the band gap is irradiated, the hole concentration deviates from the thermal equilibrium state of Expression 4 and the hole concentration is greatly increased, so that the holes are trapped by the trap to erase the memory effect.

FIGS. 6 and 7 are conceptual diagrams showing changes in the irradiation light wavelength and the threshold voltage (the voltage of the DC power supply 12 when the state changes from the depleted state to the initial state) in consideration of the above considerations. Show.

FIG. 6 shows the change of the threshold voltage in the scanning direction of the gate voltage during the CV measurement. When scanning is performed from the depletion side, that is, when the DC voltage applied to the ohmic electrode 23 is reduced and the gate voltage is relatively increased, as shown in FIG. The emission of holes generated by the measurement from the device is inherent as a memory effect.

On the other hand, when scanning is performed from the storage side, that is, when the DC voltage applied to the ohmic electrode 23 is increased and the gate voltage is relatively decreased, FIG.
, It is represented as a function of only n (+) (λ).

FIG. 7 shows the details of changes in the wavelength of irradiation light and the threshold voltage when scanning is performed from the depletion region to the accumulation region. When n (−) (λ)> n (+) (λ) and the interface state density is monotonically distributed in the depth direction (substrate thickness direction), the change is shown in the upper left, and the interface state in the depth direction is shown. The change when the inflection point exists in the density distribution is shown in the lower left. Also, n (−) (λ) <n (+) (λ)
The upper right shows the change when the interface state density is monotonically distributed in the depth direction, and the lower right shows the change when the inflection point exists in the interface state density distribution in the depth direction. .

FIGS. 6 and 7 show actual measurement results.
N (+), n (+), N
(−) And n (−) can all be determined.

Next, the results of specific measurements will be described. As the SiC substrate 20 in the sample 15, an n-type 4H—SiC doped with nitrogen (having an n− layer / n + layer structure) was used. As the oxidation conditions for forming the oxide film 21, only two types of thermal oxidation at 1080 ° C., thermal oxidation and low-temperature reoxidation heat treatment were used. The thermal oxidation was performed for 5 hours by a pyrogenetic method using a mixed gas of H ₂ + O ₂ (H ₂ : O ₂ = 4: 3) as a raw material. The low-temperature reoxidation heat treatment was performed at 950 ° C. for 3 hours in the same atmosphere as the thermal oxidation. In all samples, the thickness of the oxide film 21 is about 40 nm. The gate electrode 24 is made of Al (0.5 μm thick).
m) is applied to ni (0.5
μm) heat treatment at 1000 ° C. for 30 minutes after deposition,
In order to reduce the contact resistance with the stage, Au (about 50
nm) evaporated.

Using the trap evaluation apparatus shown in FIG. 1, the C-V
The threshold voltage V and the capacitance C are measured using the measuring device 10,
The fixed charge density was determined by the formula of Q = C · V.

FIG. 8 shows a change in the fixed charge density with respect to the wavelength of the irradiation light. In the figure, Qass indicates the fixed charge density when scanning from the accumulation side, and Qdss indicates the fixed charge density when scanning from the depletion side. Further, dark1 in the figure shows the results of measurement in the dark state before light irradiation, and dark2 shows the results of the CV measurement with the wavelength changed from 800 nm to 300 nm, followed by measurement in the dark state again.

In the case of only thermal oxidation, as shown in FIG.
It can be seen that the positive fixed charge density is about × 10 ¹¹ cm ⁻² . On the other hand, after the re-oxidation heat treatment, it can be confirmed from FIG. 8B that the fixed charge density is 10 ¹¹ cm ⁻² or less within the measurement error. From this result, it can be seen that the residual carbon segregated at the interface by the re-oxidation heat treatment can be significantly reduced, and the fixed charge due to the residual carbon can be reduced.

Since electrons are majority carriers in a MOS structure using n-type SiC, if the interface state obtained from CV measurement is considered to be an electron trap, the threshold voltage becomes lower when scanning from the accumulation side. Move in the negative direction. Therefore,
It is considered that the difference in threshold voltage between when scanning from the accumulation side and when scanning from the depletion side corresponds to the interface state density. As is apparent from FIG. 8, the interface state density is large only by thermal oxidation, and the interface state density can be significantly reduced by the re-oxidation heat treatment.

From the above experimental results, this evaluation method can measure the trap level in the energy region, which cannot be measured by the conventional technique, and uses a wide band gap semiconductor having a forbidden band of 2.0 eV or more. This is an important evaluation tool in improving the quality of the equipment.

In the above description, the MO of silicon carbide
Although applied to the S structure, as a semiconductor device,
The present invention can be applied to any structure having a capacity inside the sample. For example, the present invention can be applied to a structure having a pn junction, a Schottky junction, a hetero junction, a hetero junction of silicon carbide having different crystal systems, a hetero junction of gallium nitride and aluminum nitride, and the like. Further, as a semiconductor, other semiconductors such as gallium nitride can be applied in addition to silicon carbide.

[Brief description of the drawings]

FIG. 1 is a diagram showing a trap measuring apparatus for a wide band gap semiconductor.

FIG. 2 is a diagram showing a cross-sectional structure of a sample used for measurement.

FIG. 3 is a diagram showing the behavior of carriers trapped at a MOS interface by irradiation with single-wavelength light.

FIG. 4 is a diagram for describing definitions of an interface state density and a fixed charge density in a silicon carbide MOS structure.

FIG. 5 is a diagram showing the behavior of electrons and holes by single-wavelength light irradiation.

FIG. 6 is a diagram showing changes in irradiation light wavelength and threshold voltage.

FIG. 7 is a diagram illustrating details of changes in irradiation light wavelength and threshold voltage when scanning is performed from a depletion region to an accumulation region.

FIG. 8 is a diagram showing a change in fixed charge density with respect to irradiation light wavelength.

[Explanation of symbols]

10 CV measuring device, 11 integrator, 12 DC power supply, 13 AC power supply, 15 sample, 18 single wavelength light,
Reference numeral 20 denotes a silicon carbide semiconductor substrate, 21 denotes an oxide film, 23 denotes an ohmic electrode, and 24 denotes a gate electrode.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G059 AA03 BB16 CC20 GG10 HH02 KK10 2G060 AA09 AE40 AF02 AF10 AG08 4M106 AA01 AB01 AB11 BA20 CA12 CB07

Claims (17)

[Claims] 1. A method for evaluating a trap of a semiconductor, comprising: exciting trapped carriers by light irradiation to evaluate a trap level of the semiconductor. 2. A method for evaluating a trap of a semiconductor, comprising: performing CV measurement while irradiating a semiconductor having an internal capacitance with light; and evaluating a trap level based on the measurement result. 3. The method according to claim 2, wherein the trap level is evaluated by obtaining a fixed charge density of the trapped carriers based on a measurement result of the CV measurement. 4. A DC voltage is applied to one electrode formed on the semiconductor while the semiconductor is irradiated with light,
The method according to claim 2, wherein the CV measurement is performed by changing the DC voltage. 5. The CV measurement caused by the AC voltage is performed by applying an AC voltage to the other electrode formed on the semiconductor while the semiconductor is irradiated with light. Item 5. The method according to Item 4. 6. The method according to claim 1, wherein the light is light of a single wavelength. 7. The method according to claim 6, wherein the light is light after using a spectroscope with white light as a light source. 8. The semiconductor device according to claim 1, wherein a photon energy of the light is smaller than a forbidden band of the semiconductor.
The method according to any one of the preceding claims. 9. The method according to claim 1, wherein the semiconductor has a forbidden band of 2.0 eV or more. 10. The method according to claim 1, wherein the semiconductor has a MOS structure. 11. The method according to claim 1, wherein the semiconductor has a pn junction. 12. The method according to claim 1, wherein the semiconductor has a Schottky junction. 13. The semiconductor device according to claim 1, wherein the semiconductor has a heterojunction.
The method described in one. 14. The method according to claim 1, wherein the semiconductor has a semiconductor substrate made of silicon carbide. 15. The method according to claim 1, wherein the semiconductor has a semiconductor substrate made of gallium nitride. 16. The method according to claim 1, wherein the semiconductor has a heterojunction of silicon carbide having different crystal systems. 17. The method according to claim 1, wherein the semiconductor has a heterojunction between gallium nitride and aluminum nitride.