JP2001080072A - Printing apparatus and apparatus and method for generating driving waveform - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a driving waveform from suddenly changing due to cumulative errors by digital/analog converting specific upper bits among the cumulative result of a plurality of accumulated bits and outputting as an analog signal. SOLUTION: Driving waveform data fed from a control part 45 is stored in a memory 60. Driving waveform data read out by a first latch 62 from the memory 60 is temporarily held. Outputs of a first latch 62 and a second latch 66 are added by an adder 66, and the output of the second latch 66 is converted to an analog signal by a digital/analog converter 70. The converted analog signal is amplified by a voltage-amplifying part 72 to a voltage whereby a piezoelectric element drives. A current corresponding to the amplified voltage signal is supplied by a current-amplifying part 74.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technique for generating a driving waveform for operating a driving element.

[0002]

2. Description of the Related Art In recent years, as an output device of a computer,
2. Description of the Related Art A color printer that discharges several colors of ink from an ink head has become widespread, and is widely used for printing an image processed by a computer or the like in multiple colors and multiple gradations. In order to realize multi-gradation printing, the weight of ink droplets ejected from the nozzles of a recording head is controlled, and the size of ink dots formed on a print medium is controlled. .

Conventionally, an ink-jet printer binarizes whether or not to form an ink dot, and expresses a halftone of a printed image by determining how many pixels in a given area have an ink dot. Was common.
However, recently, by forming a plurality of differently sized ink dots in one pixel using light and dark inks,
It is possible to express a halftone of a print image with more gradations.

For example, in an ink jet printer using a piezo element, in order to form ink dots of different sizes, it is necessary to control the meniscus (the surface shape of the ink at the nozzle opening) at the nozzle opening of the recording head and to form the ink droplets. It is important to control the timing of the discharge. Therefore, in order to form a desired ink dot, a drive waveform for operating the piezo element of the recording head is changed according to the size of the ink dot to be formed.

The driving waveform for operating the piezo element has a different resistance value by using a method in which the absolute value of the driving voltage at an arbitrary time is previously stored in a memory or by utilizing the fact that the piezo element forms a capacitor. It has been controlled by switching the resistance between the piezo elements. However, in the former case, there is a problem that a large amount of memory is required to store the driving waveform, and in the latter case, a pulse signal with complicated timing is required.

In order to solve these problems, there is a method of obtaining a drive waveform in a programmable manner by determining the amount of change in voltage of the drive waveform at an arbitrary time and sequentially adding the values by an adder. Proposed.

FIG. 12 is a block diagram showing an internal configuration of a conventional drive waveform generation circuit 100 for generating a drive waveform. FIG. 13 shows the driving waveform generation circuit 1 shown in FIG.
FIG. 9 is an explanatory diagram showing a process of generating a drive waveform at 00. The drive waveform generation circuit 100 shown in FIG. 12 includes a memory 102, an accumulation unit 104, and a digital / analog converter 104. The drive waveform data indicating the waveform of the drive signal COM is stored in the memory 102.
As shown in FIG. 13A, the drive waveform data ΔV1, ΔV2, ΔV3 read from the memory 102 are sequentially accumulated in the accumulator 104 in synchronization with the clock signal CLK. Here, the drive waveform data is data representing a change amount of the drive voltage per one cycle t of the clock signal CLK. Top 1 of the 18-bit accumulation result
The drive signal COM is generated by the digital / analog conversion of the 0 bit by the digital / analog converter 106.

[0008]

In the method of FIG. 13, the drive waveform data ΔV1 and ΔV
If the value obtained by accumulating 2, ΔV3,... Becomes zero, the start and end levels of the drive waveform completely match. However, in practice, the accumulated value of the drive waveform data over one pixel section often does not become zero. This is because a calculation error occurs when setting the drive waveform data. For example,
The first drive waveform data ΔV1 is determined by dividing the design value δ1 of the voltage change in the accumulation period 8t by the number of accumulation periods (that is, 8) in the period 8t. When the division is not divisible, the drive waveform data ΔV1 includes a rounding error. This rounding error is the cause of the accumulated value error at the end of one pixel section. Such errors can be reduced by increasing the number of lower bits that are not subject to digital / analog conversion,
For the upper bits, the error can be set to 0. However, it is difficult to reduce the accumulation error to zero for the lower bits.

In the conventional drive waveform generating device, such errors are sequentially accumulated in the second latch 108 for each pixel section, and a waveform deviated from a desired drive waveform may be generated. That is, for example, when trying to obtain the drive waveform shown in FIG. 14A, as shown in FIG. 14B, the error e1 is accumulated for each cycle, and the start potential of the drive waveform becomes It deviates from the desired driving waveform. When the error e1 further accumulates from the state of FIG. 14B, the adder 106 causes an overflow or an underflow, and the driving waveform may suddenly largely change.

FIG. 15 shows a normal drive waveform and the adder 10.
6 is an explanatory diagram showing drive waveforms when an overflow or underflow occurs. FIG. As shown in FIG. 15B, when the addition result exceeds the upper limit value UL of the output of the adder 106, the output of the adder jumps to a value close to the lower limit value LL, so that the driving waveform changes significantly. FIG.
As shown in (c), when the addition result exceeds the lower limit value LL of the output of the adder 106, the output of the adder jumps to a value close to the upper limit value UL. . Thus, as the accumulated error accumulates,
The drive waveform suddenly changed greatly, and an overcurrent could flow in the circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. When accumulating drive waveform data in a process of generating a drive waveform, the drive waveform rapidly changes due to an accumulation error. The purpose is to prevent

[0012]

Means for Solving the Problems and Their Functions / Effects To solve at least a part of the above-mentioned problems, the present invention provides:
A plurality of drive waveform data for generating a drive waveform are sequentially accumulated, and a specific upper bit of the accumulated result of the accumulated plurality of bits is digital-to-analog converted and output as an analog signal. When accumulating the drive waveform data, when the accumulation result of a plurality of bits is going to exceed any one of the boundary values in a predetermined range, the accumulation result is set to a predetermined value close to the boundary value. By doing so, it is possible to prevent the accumulation result from jumping to the opposite boundary value, so that it is possible to prevent the drive waveform from suddenly changing.

When accumulating the driving waveform data, it is determined whether or not the accumulation result exceeds a boundary value based on the carry signal of the accumulation result and the most significant bit of the driving waveform data. You may. By doing so, it is possible to easily determine whether or not the accumulation result exceeds the boundary value.

When the accumulation result exceeds the upper limit of the predetermined range, the accumulation result is set to the upper limit, and when the accumulation result exceeds the lower limit of the predetermined range, the accumulation result is set to the lower limit. You may.

The present invention can be realized in various forms such as a printing apparatus, a driving waveform generating apparatus, and a driving waveform generating method.

[0016]

Embodiments of the present invention will be described below in the following order based on examples. A. Overall configuration of printing apparatus: B. Configuration and operation of drive waveform generation device: Second embodiment D. Third embodiment: Modification:

A. FIG. 1 is a block diagram showing the overall configuration of a printing apparatus according to the present invention. As shown in FIG. 1, the printing apparatus includes a computer 90, a control circuit 40, a paper feed motor 23, a carriage motor 24 for performing main scanning, and a recording head 50.

In the computer 90, an application program operates under a predetermined operating system. The operating system incorporates a video driver and a printer driver, and displays an image on a display and performs various image processing.

The control circuit 40 includes an interface 41 for receiving a print signal and the like from the computer 90, a RAM 42 for storing various data, a ROM 43 for storing various data processing routines and the like, an oscillation circuit 44,
A control unit 45 including a CPU and the like;
And an interface 47 for sending print signals and drive signals to the paper feed motor 23, the carriage motor 24, and the recording head 50.

The RAM 42 is used as a receiving buffer 42A, an intermediate buffer 42B or an output buffer 42C. The print signal from the computer 90 is stored in the reception buffer 42A via the interface 41.
This data is converted into an intermediate code and stored in an intermediate buffer 4.
2B. Then, necessary processing is performed by the control unit 45 with reference to font data, graphic functions, and the like in the ROM 43, dot pattern data is developed, and stored in the output buffer 42C. The dot pattern data is sent to the recording head 50 via the interface 47.
Sent to

FIG. 2 is a block diagram showing the electrical configuration of the recording head 50. The recording head 50 includes a plurality of shift registers 51A to 51N corresponding to the number of nozzles, a plurality of latch circuits 52A to 52N, a plurality of level shifters 53A to 53N, and a plurality of switch circuits 54A to 54N.
And a plurality of piezo elements 55A to 55N. The print signal SI is input to the shift registers 51A to 51N in synchronization with the clock signal CLK from the oscillation circuit 44. Then, the signals are latched by the latch circuits 52A to 52N in synchronization with the latch signal LAT. The latched print signal SI is amplified by the level shifters 53A to 53N to a voltage that can drive the switch circuits 54A to 54N, and is supplied to the switch circuits 54A to 54N. The drive signals COM from the drive waveform generation circuit 46 are input to the input sides of the switch circuits 54A to 54N, and the piezo elements 55A to 55N are connected to the output sides.

The switch circuits 54A to 54N are, for example,
When the print signal SI is “1”, the drive signal COM is supplied to the piezo elements 55A to 55N to be operated, and when the print signal SI is “0”, it is shut off and not operated. As is well known, a piezo element is an element that distorts the crystal structure due to application of a voltage and converts electric-mechanical energy at an extremely high speed. Although not shown, when the drive signal COM is supplied to the piezo elements 55A to 55N, the piezo elements 55A to 55N deform accordingly, and the walls of the ink chambers also deform. This controls the ejection of ink droplets from the nozzles. Printing is performed by the ejected ink droplets adhering to the print medium.

B. Configuration and operation of drive waveform generation device: B-1. FIG. 3 is a block diagram showing the internal configuration of the drive waveform generation circuit 46. The drive waveform generation circuit 46 includes a memory 60 for storing drive waveform data supplied from the control unit 45, a first latch 62 for temporarily holding drive waveform data read from the memory 60, and a first latch 62 An adder 64 for adding the output to an output of a second latch 66 to be described later;
5, a second latch 66, a digital / analog converter 70 for converting the output of the second latch 66 into an analog signal,
It has. Further, a voltage amplifying unit 72 for amplifying the converted analog signal to a voltage at which the piezo element operates and a current amplifying unit 74 for supplying a current corresponding to the amplified voltage signal are provided. The adder 64 and the second latch 66 constitute an accumulator 68 for accumulating the driving waveform data.
Various signals are supplied from the control unit 45 to the drive waveform generation circuit 46. That is, the memory 60 includes a first clock signal CLK1, a data signal representing drive waveform data,
Address signals A0 to A3 and an enable signal are supplied. The first latch 62 is supplied with a second clock signal CLK2 and a reset signal RESET. The inversion prevention circuit 65 includes a third clock signal C
LK3 is supplied. The second latch 66 is supplied with a third clock signal CLK3 and a reset signal RESET. The reset signal RESET supplied to the first and second latches 62 and 66 is the same. Also,
The same applies to the third clock signal CLK3 supplied to the inversion prevention circuit 65 and the second latch 66. It should be noted that the drive waveform generation circuit 46 includes the control unit 45 and the RA
It functions as a drive waveform generator together with M42 and ROM43. Further, the inversion prevention circuit 65 functions as an accumulation result correction circuit.

B-2. Driving Waveform Generation Method: FIG. 4 is a timing chart showing the timing of writing driving waveform data in the memory 60. Prior to the generation of the drive waveform COM, the data signal indicating the drive waveform data and the address of the data signal are stored in the first clock signal CLK1.
Are supplied from the control unit 45 to the memory 60 in synchronization with.
Although the data signal is one bit, as shown in FIG.
The drive waveform data is transferred one bit at a time by serial transfer using the first clock signal CLK1 as a synchronization signal. That is, when the drive waveform data is transferred from the control unit 45 to the memory 60, first, the first clock signal CLK
The data signal is supplied for a plurality of bits in synchronization with 1. Thereafter, address signals A0 to A3 representing write addresses for storing the data and an enable signal are supplied. The memory 60 reads the address signal at the timing when the enable signal is supplied, and writes the received drive waveform data to the address. Address signal A
Since 0 to A3 are 4 bits, a maximum of 16 types of drive waveform data can be stored in the memory 60.

FIG. 5 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation circuit 46. When the read address B is output as the address signals A0 to A3 after the writing of the drive waveform data into the memory 60 is completed, the first drive waveform data ΔV1 is output from the memory 60. Thereafter, when a pulse of the second clock signal CLK2 is generated, the drive waveform data ΔV1 is held in the first latch 62. In this state, when the next pulse of the third clock signal CLK3 is generated, the second latch 66
And the 16-bit output of the first latch 62 are added by the adder 64, and the addition result is held in the second latch 66. That is, as shown in FIG. 5, once the drive waveform data corresponding to the address signal is selected, every time the third clock signal CLK3 is received, the output of the second latch 66 is set to the drive signal. The values of the waveform data are accumulated. At this time, the inversion prevention circuit 6
5 indicates that the output of the adder 64 has its upper limit value “111.
It is determined whether the value exceeds 1 ″ (18 bits). Then, the inversion prevention circuit 65 outputs a value corresponding to the determination.

In the example shown in FIG. 5, a voltage per cycle t of the third clock signal CLK3 is Δ
Drive waveform data indicating that the voltage is increased by V1 is stored. Therefore, when the address B is made valid by the second clock signal CLK2, the voltage increases by ΔV1. Further, the address A stores ΔV2 = 0 as the drive waveform data, that is, a value indicating that the voltage is held. Therefore, the second clock signal CL
When the address A becomes valid by K2, the waveform of the drive signal is maintained in a flat state with no increase or decrease. Further, the drive waveform data indicating that the voltage per one cycle t of the third clock signal CLK3 is reduced by ΔV3 is stored in the address C. Therefore, after the address C becomes valid by the second clock signal CLK2, ΔV3
The voltage will gradually decrease. The increase or decrease is determined by the sign of the data stored at each address.

In this way, the 1 added by the adder 64
Of the 8-bit addition result, the upper 10 bits of the voltage level data D ₀ are input to the digital / analog converter 70. The entire 18-bit addition result is added to the adder 6
4 is input again. As a result, the voltage level data D ₀ output from the second latch 66 changes stepwise as shown in FIG. This voltage level data D ₀ is
5 is converted by the digital / analog converter 70.
The drive waveform shown in (b) is formed.

The drive waveform data read from the memory 60 is represented by a two's complement representation for negative numbers.
The driving waveform data input to the adder 64 is 16
Although they are bits, when they are added, the value of the most significant bit (16th bit) is used as it is for the 17th and 18th bits. The addition operation of the adder 64 will be described later.

B-3. Internal configuration and operation of the inversion prevention circuit:
FIG. 6 is a block diagram showing the internal configuration of the inversion prevention circuit 65. The inversion prevention circuit 65 includes 18 AND gates AG.
S0 to AGS17 and 18 AND gates AGR0 to AGR0
AGR17 and 18 D flip-flops DFF0 to DFF0
And a DFF 17. First AND Gate AG
S0 to AGS17 are 1s provided from the first latch 62.
The logical product of the inverted signal of the most significant bit MSB of the 6-bit drive waveform data and the carry C output from the adder 64 is obtained, and the output is output to D flip-flops DFF0 to DFF0.
Input to the set terminal S of the FF 17. The second AND gates AGR0 to AGR17 provide the most significant bit MSB of the 16-bit drive waveform data supplied from the first latch 62.
And the inverted signal of carry C output from adder 64, and outputs the result as D flip-flop DFF
0 to the reset terminal R of the DFF 17. The D flip-flops DFF0 to DFF17 output the clock signal CL
In synchronization with the falling edge of the K3, to update the output Q ₀ ~Q _17. That is, when both the set terminal S and the reset terminal R are “0”, the OU which is the accumulation result of the adder 64 is obtained.
T ₀ OUT ₁ . . . OUT ₁₇ is a D flip-flop DFF
_{0 to} DFF 17 outputs Q ₀ Q ₁ . . . As Q _17, is output as it is. When the set terminal S is “0” and the reset terminal R is “1”, the D flip-flop DFF0
ＤDFF17 outputs Q _{0 to} Q ₁₇ are all reset to “0”. Further, when the set terminal S is "1" and the reset terminal R is "0", the D flip-flops DFF0 to DFF
The outputs Q _{0 to} Q ₁₇ of the FF ₁₇ are all set to “1”.

In the embodiment shown in FIG. 6, a pair of AND gates are provided for each of the D flip-flops DFF0 to DFF17. Instead, a total of 18 D flip-flops DFF0 to DFF17 are provided. A pair of AND gates may be shared.

FIG. 7 is an explanatory diagram for explaining the addition processing performed in the adder 64 and a method of correcting the addition result.
Here, for simplicity, the addition result is 8 bits,
The description will be given on the assumption that the drive waveform data supplied from the latch 62 is 6 bits. The actual drive waveform data is expressed in 16-bit two's complement notation, and when added in the adder 64, the most significant bit M
The value of SB (16th bit) is used as it is for the 17th and 18th bits. Therefore, in the following description,
The value of the most significant bit MSB (6th bit) of the 6-bit drive waveform data (the value circled in the figure) is changed to the 7th bit and 8th bit.
The addition is executed using the bit as it is.

FIG. 7A shows the accumulation result "1110010".
0 ”(decimal“ 228 ”) and the drive waveform data“ 01 ”.
0110 ”(decimal“ 22 ”) is added. In this addition, there is no carry and carry C is “0”
It is. The MSB of the drive waveform data is “0”. Therefore, the set terminal S of the D flip-flop DFF
And “0” is input to the reset terminal R,
From the D flip-flops DFF0 to DFF17, the addition result “11111010” is output as it is.

FIG. 7B shows the result of accumulation “1110101”.
1 "(decimal" 235 ") to drive waveform data" 01 ".
0110 ”(decimal“ 22 ”) is added. In this addition, there is a carry, and carry C is "1". The MSB of the drive waveform data is “0”.
It is. Therefore, "1" is input to the set terminal S and "0" is input to the reset terminal R of the D flip-flop DFF, and the D flip-flops DFF0 to DFF17 are input.
Outputs the upper limit value “11111111”.

FIG. 7C shows the result of accumulation "0001110".
1 "(decimal" 29 ") and the drive waveform data" 101 ".
010 "(decimal" -22 "). In this addition, there is a carry, and carry C is "1". The MSB of the drive waveform data is “1”.
It is. Therefore, “0” is input to both the set terminal S and the reset terminal R of the D flip-flop DFF, and from the D flip-flops DFF0 to DFF17,
“00000111” is output as it is.

FIG. 7D shows the accumulation result “0000110”.
1 "(decimal" 13 ") and the drive waveform data" 101 ".
010 "(decimal" -22 "). In this addition, there is no carry, and carry C is "0". The MSB of the drive waveform data is “1”.
It is. Therefore, “0” is input to the set terminal S and “1” is input to the reset terminal R of the D flip-flop DFF, and the D flip-flops DFF0 to DFF17 are input.
Output the lower limit value "0000000000".

As described above, in the first embodiment, the adder 64
Is set to exceed the upper limit value or the lower limit value, the addition result input to the second latch 66 is forcibly set to the upper limit value or the lower limit value. As a result, it is possible to prevent an abrupt change in the drive voltage waveform and an overcurrent from flowing through the circuit.

C. Second Embodiment FIG. 8 is a block diagram showing a configuration of an accumulating unit in a second embodiment. Adder 64
The former stage and the latter stage of the second latch 66 are the same as those of the drive waveform generating circuit 46 of the above-described first embodiment, and therefore description thereof is omitted. In the second embodiment, the adder 64 and the second latch 66
And a selector 67 is provided between them. The selector 67 is connected to data registers 63 a and 63 b and a determination circuit 69.
a, 63b, the selector 67, and the determination circuit 69 function as an inversion prevention circuit.

In the first data register 63a, 18-bit data in which all bits are "1" are set. In the second data register 63b, 18-bit data in which each bit is all "0" is set. The selector 67 selects and outputs one of the three data input from the data registers 63a and 63b and the adder 64 according to the output of the determination circuit 69.

The determination circuit 69 has the same pair of AND gates 69a and 69b as the pair of AND gates (for example, AGS0 and AGR0) shown in FIG. In other words, the determination circuit 69 determines whether the adder 64
Is determined whether or not the addition result exceeds the upper limit value or the lower limit value, and 2-bit data Q69 indicating the determination result is output.

FIG. 9 is an explanatory diagram illustrating the output Q67 of the selector 67 according to the carry C output from the adder 64 and the MSB of the drive waveform data. Carry C
When the MSBs of the driving waveform data are both “0” or “1”, the output Q69 of the determination circuit 69 is output.
Is “00”, and the selector 67 outputs the accumulation result Q64 of the adder 64 as it is. When the carry C is “0” and the MSB of the drive waveform data is “1”, the output Q69 of the determination circuit 69 is “01” and the selector 6
7 outputs 18-bit data in which each bit is "0". Further, when the carry C is “1” and the MSB of the drive waveform data is “0”, the output Q
69 is “10”, and the selector 67 outputs 18-bit data in which all bits are “1”.

As described above, according to the circuit of the second embodiment as well, it is possible to prevent a sudden change in the drive voltage waveform and an overcurrent from flowing through the circuit.

D. Third Embodiment FIG. 10 is a block diagram showing an internal configuration of a drive waveform generation circuit 46 as a third embodiment. The third embodiment is the same as the first embodiment except that a floor signal FLOOR is input to the second latch 66 from the control unit 45 of FIG.

As described with reference to FIG.
The accumulated value at 8 includes an accumulation error in the lower bits. Due to the accumulation error included in the lower bits, a waveform deviated from a desired driving waveform is generated. Therefore,
In the third embodiment, the accumulation error of the lower 8 bits of the 18-bit data in the accumulation section 68 is determined by the floor signal FLOO.
It is cleared using R.

FIG. 11 is a timing chart showing the timing for clearing the lower 8 bits of the second latch 66. Here, it is assumed that the same drive waveform is repeated for each cycle T of one pixel section. The value VM of the voltage level data D ₀ at the start and end of one pixel section (hereinafter referred to as “VM”)
Has a predetermined non-zero value. The start and end of one pixel section are defined by a print timing signal PTS generated in the control unit 45. The print timing signal PTS is a signal for instructing to start outputting a drive waveform when forming an ink dot at each pixel position. The floor signal FLOOR is a signal indicating a timing t0 at which the lower 8 bits of the second latch 66 are cleared. When the floor signal FLOOR is input from the control unit 45 to the second latch 66, only the lower 8 bits of the second latch 66 are cleared, and the upper 10 bits are maintained at the start level VM. In the third embodiment, the floor signal F
LOOR is input at the same timing as the print timing signal PTS, that is, for each cycle of the drive waveform. In this case, the print timing signal PTS is changed to the floor signal FLO.
It may be used as OR. Further, this timing is not limited thereto, for example, the timing t0, t1, etc. that voltage level data D ₀ output from the second latch 66 becomes VM, floor signal at a timing previously known output value The lower 8 bits may be cleared by inputting FLOOR.

According to the third embodiment, since errors in the drive waveform data are cleared at a predetermined timing, accumulation of errors in the drive waveform data can be prevented, and a drive waveform having a desired complicated profile can be easily obtained. it can. Further, even if the accumulation result in the adder 64 may exceed the upper limit or the lower limit without clearing the error of the drive waveform data by the floor signal FLOOR for some reason,
It is possible to prevent an overcurrent from flowing through the circuit due to a sudden change in the drive voltage waveform.

E. Modifications: The present invention is not limited to the above-described embodiment at all, and can be implemented in various modes without departing from the gist thereof,
For example, the following modifications are possible.

E-1. Modification 1 In the above embodiment, the addition result of the adder 64 is either the upper limit value (18-bit value in which each bit is all “1”) or the lower limit value (18-bit value in which all bits are all “0”) Value), the data held in the second latch 66 is forcibly set to the upper limit or the lower limit, but the data held in the second latch 66 is set to the upper limit of the addition result. Alternatively, it can be set to an arbitrary value close to the lower limit. For example, instead of the upper limit, certain lower bits are set to “0”, and all higher bits are set to “1”.
Can be used.

In the above embodiment, the inversion prevention circuit 65 is used.
Has been determined whether the sum exceeds the upper limit value or the lower limit value of the addition result of the adder 64. Instead, any one of a predetermined range of the entire range that the adder 64 can take is determined. May be determined.
For example, when the output of the adder 64 is 8 bits, the addition result can take a value of 0 to 255 in decimal, but it is determined whether or not the upper limit value is “255” and the lower limit value is “0”. Instead, it may be determined whether or not the value exceeds a boundary value (“5” or “250”) in the range of 5 to 250. That is, generally, when the accumulation result of the drive waveform data is going to exceed any one of the boundary values in a predetermined range, the accumulation result is set to a predetermined set value close to the boundary value. do it.

E-2. Modification Example 2 The drive waveform generation device and the drive waveform generation method of the present invention are used not only for the printing apparatus described in the above-described embodiment, but also for the drive waveform generation device and the drive waveform generation for driving other actuators and the like. It can also be applied as a method.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the overall configuration of a printing apparatus according to the present invention.

FIG. 2 is a block diagram illustrating an electrical configuration of a recording head.

FIG. 3 is a block diagram showing an internal configuration of a drive waveform generation circuit according to the present invention.

FIG. 4 is a timing chart showing the timing of writing drive waveform data in a memory.

FIG. 5 is an explanatory diagram illustrating a process of generating a drive waveform.

FIG. 6 is a block diagram showing an internal configuration of the inversion prevention circuit of the present invention.

FIG. 7 is an explanatory diagram illustrating an addition process performed by an adder 64 and a method of correcting an addition result.

FIG. 8 is a block diagram illustrating a configuration of an accumulating unit according to a second embodiment of the present invention.

FIG. 9 is an explanatory diagram illustrating an output of a selector according to a carry C output from an adder 64 and an MSB of drive waveform data.

FIG. 10 is a block diagram showing an internal configuration of a drive waveform generation circuit according to a third embodiment of the present invention.

FIG. 11 is an explanatory diagram for explaining a timing of inputting a floor signal in the third embodiment.

FIG. 12 is a block diagram showing an internal configuration of a conventional drive waveform generation circuit.

FIG. 13 is an explanatory diagram illustrating a method of generating a drive waveform.

FIG. 14 is an explanatory diagram illustrating accumulation of errors in a process of generating a drive waveform.

FIG. 15 is an explanatory diagram showing a normal drive waveform and a drive waveform when an adder causes overflow or underflow.

[Explanation of symbols]

 23 ... Paper feed motor 24 ... Carriage motor 40 ... Control circuit 41 ... Interface 42 ... RAM 42A ... Reception buffer 42B ... Intermediate buffer 42C ... Output buffer 43 ... ROM 44 ... Oscillation circuit 45 ... Control unit 46 ... Drive waveform generation circuit 50 ... Recording heads 51A to 51N Shift registers 52A to 52N Latch circuits 53A to 53N Level shifters 54A to 54N Switch circuits 55A to 55N Piezo elements 60 Memory 62 First latch 63a Data registers 63b Data registers 64 Addition Device 65 inversion prevention circuit 66 second latch 67 selector 68 accumulator 68a accumulator 69 determination circuit 69a AND gate 69b AND gate 70 D / A converter 72 voltage amplifying unit 74 Current amplification unit 90 ... Computer 1 0 ... drive waveform generation circuit 102 ... memory 104 ... accumulator 106 ... D / A converter

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Noboru Asauchi 3-5-5 Yamato, Suwa-shi, Nagano Seiko Epson Corporation (72) Inventor Yuichi Nishihara 3-5-35 Yamato, Suwa-shi, Suwa, Nagano Seiko -Epson Corporation F-term (reference) 2C057 AF39 AF99 AM03 AM18 AM22 AN01 AR04 AR08 BA03 BA14 2C062 AA02 AA14

Claims (11)

[Claims] 1. The method according to claim 1, further comprising the steps of:
A printing apparatus that records an image on a recording medium, comprising: a print head having a plurality of nozzles and a plurality of drive elements for driving the plurality of nozzles to eject ink droplets; and A driving waveform generating circuit that generates a transmitted driving waveform, wherein the driving waveform generating circuit stores a plurality of driving waveform data for generating the driving waveform; An accumulator for sequentially accumulating the drive waveform data sequentially read one by one at a predetermined read timing at a predetermined accumulative timing; and a result of the accumulation of the plurality of bits in the accumulator being a predetermined value. An accumulation result correction circuit for setting the accumulation result to a predetermined set value close to the boundary value when trying to exceed any boundary value of the range; and a plurality of bits obtained by the accumulation unit. Of the accumulation result, the printing apparatus comprising: a digital / analog converter for outputting an analog signal, a certain upper bit to a digital / analog converter. 2. The printing apparatus according to claim 1, wherein the accumulation unit includes: a first latch circuit for holding the accumulation result; and the drive waveform data read from the memory. An adder for updating the accumulation result by adding the accumulation result held by the first latch circuit;
Wherein the drive waveform data is expressed in two's complement notation, and the accumulation result correction circuit, based on the carry signal of the adder and the most significant bit of the drive waveform data, A printing apparatus comprising: a determination unit configured to determine whether the accumulation result output from the adder exceeds the boundary value. 3. The printing apparatus according to claim 2, wherein the accumulation result correction circuit is further interposed between the adder and the first latch circuit to output the output of the adder. A determination unit configured to determine, when the accumulation result output from the adder exceeds the boundary value, the output of the second latch circuit to the boundary value. A printing apparatus for setting the predetermined value close to the predetermined value. 4. The printing apparatus according to claim 3, wherein the determination unit is configured to determine the second one when the accumulation result output from the adder exceeds an upper limit value of an output of the adder. The output of the second latch circuit is set to the lower limit when the accumulation result output from the adder exceeds the lower limit of the output of the adder. The printing device to set to the value. 5. A drive waveform generator for generating a drive waveform for driving a drive element, comprising: a memory for storing a plurality of drive waveform data for generating the drive waveform; An accumulator for sequentially accumulating the drive waveform data read one by one at a predetermined timing at a predetermined accumulation timing; and a result of accumulating the plurality of bits in the accumulator being a predetermined value. An accumulation result correction circuit that sets the accumulation result to a predetermined set value close to the boundary value when trying to exceed any one of the boundary values of the range; A digital-to-analog converter that digitally / analog-converts a specific upper bit of the accumulation result and outputs the converted signal as an analog signal. 6. The driving waveform generating apparatus according to claim 5, wherein the accumulating section includes a first latch circuit for holding the accumulation result, and the driving waveform read from the memory. An adder for updating the accumulation result by adding data and the accumulation result held by the first latch circuit;
Wherein the drive waveform data is expressed in two's complement notation, and the accumulation result correction circuit, based on the carry signal of the adder and the most significant bit of the drive waveform data, A drive waveform generation device comprising: a determination unit that determines whether the accumulation result output from the adder exceeds the boundary value. 7. The drive waveform generating device according to claim 6, wherein the accumulation result correction circuit is further interposed between the adder and the first latch circuit, and A second latch circuit that holds the output of the second latch circuit when the accumulation result output from the adder exceeds the boundary value. A drive waveform generator for setting the predetermined set value close to a boundary value. 8. The drive waveform generation device according to claim 7, wherein the determination unit is configured to: when the accumulation result output from the adder exceeds an upper limit value of an output of the adder. An output of the second latch circuit is set to the upper limit value, and when the accumulation result output from the adder exceeds a lower limit value of the output of the adder, the output of the second latch circuit is set to A drive waveform generator for setting the lower limit value. 9. A driving waveform generating method for driving a driving element, comprising: (a) sequentially selecting a plurality of driving waveform data for generating the driving waveform one by one at a predetermined timing; (B) sequentially accumulating the selected drive waveform data at a predetermined accumulation timing; and (c) making the accumulation result of the plurality of bits exceed any one of boundary values in a predetermined range. Setting the accumulation result to a predetermined set value close to the boundary value; and (d) digital / analog converting a specific upper bit of the accumulation result of the plurality of bits. A driving waveform generation method comprising: 10. The driving waveform generating method according to claim 9, wherein in the step (c), the accumulation result is based on a carry signal of the accumulation result and a most significant bit of the driving waveform data. A drive waveform generation method including a step of determining whether or not a value exceeds the boundary value. 11. The driving waveform generation method according to claim 10, wherein in the step (c), when the accumulation result exceeds an upper limit of the predetermined range, the accumulation result is set to the upper limit. Setting the accumulated result to the lower limit when the accumulated result exceeds the lower limit of the predetermined range.