JP2001077687A - Phase comparator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate an ASIC, etc., mounting a phase comparator circuit PD by improving the phase comparing characteristics of the phase comparator circuit PD, to improve the frequency characteristics of a PLL(phased-locked loop) circuit, etc., including this. SOLUTION: A phase comparator circuit includes a NAND gate NA8 which makes an up signal UP to be at a high level, in response to that a reference clock signal RFCK is made to be at a high level in advance of a feedback clock signal FBCK and returns it to a low level in response to that a stop signal n7 is made to be at a low level, a NAND gate NA9 which makes a down signal DOWN to be at a high level in response to that the clock signal FBCK is made to be at a high level in advance of the signal RFCK and returns it to a low level in response to that the signal n7 is made to be at a low level, and a NAND gate NA7 which makes the signal to be at a low level in response to that both of the signal RFCK and the signal FBCK are made to be at a high level. A delay control circuit DC which identifies that the phase comparator circuit PD comes into an overlapped state to raise the potential of a delay control signal GDC is provided to selectively reduce the transmission delay time of the gate NA7 in response to the rise of the potential of the signal GDC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparison circuit, and more particularly to a phase comparison circuit of a PLL circuit mounted on a logic integrated circuit device such as an ASIC, an improvement in the phase comparison characteristic thereof, and a speedup of the logic integrated circuit device. For technology that is particularly effective to use.

[0002]

2. Description of the Related Art A PLL (Phase) for generating an internal clock signal phase-synchronized with a reference clock signal supplied from the outside.
and a logic integrated circuit device such as an ASIC (application-specific integrated circuit) that includes a modularized PLL circuit as a clock signal source. The PLL circuit selectively generates an up signal or a down signal having a pulse width corresponding to a phase difference between the reference clock signal and the internal clock signal or a frequency-divided signal thereof, and an output from the phase comparison circuit. A charge pump circuit for generating a control voltage having a potential corresponding to the phase difference between the reference clock signal and the internal clock signal according to the up signal and the down signal, and controlling the oscillation frequency according to the potential of the control voltage output from the charge pump circuit A voltage-controlled oscillation circuit for generating a substantial internal clock signal.

[0003]

Prior to the present invention, the present inventors engaged in the development of a PLL circuit including a phase comparison circuit and mounted on an ASIC, and noticed the following problems. That is, as shown in FIG. 10, for example, the phase comparison circuit PD included in the PLL circuit has its second input terminal (here, the input terminals of each logic gate are, for example, first to An inverter V1 of the reference clock signal RFCK is referred to as a second input terminal.
(NAND) gate NA receiving inverted signal due to
1 and a NAND gate NA2 having a first input terminal receiving an inverted signal of the feedback clock signal FBCK obtained by dividing the internal clock signal by the inverter V2.

The output signal n1 of the NAND gate NA1 of the phase comparison circuit PD is supplied to first input terminals of NAND gates NA3, NA7 and NA8.
The second output signal n2 is supplied to the second input terminal of the NAND gate NA4, the fourth input terminal of the NAND gate NA7, and the third input terminal of the NAND gate NA9. The output signal n3 of the NAND gate NA3 is supplied to the first input terminal of the NAND gate NA5 and the NAND gate NA7.
And the output signal n4 of the NAND gate NA4 is supplied to the second input terminals of the NAND gates NA6 and NA8.
9 and a third input terminal of the NAND gate NA7.
Is supplied to the input terminal of.

On the other hand, the output signal n7 of the NAND gate NA7
Is supplied to the second input terminal of the NAND gate NA5, the first input terminals of the NAND gates NA6 and NA9, and the third input terminal of the NAND gate NA8. The output signal n5 of the NAND gate NA5 is output from the NAND gate NA3.
And the output signal n6 of the NAND gate NA6 is supplied to the first input terminal of the NAND gate NA4.

Further, the output signal n of the NAND gate NA8
8 is supplied to the first input terminal of the NAND gate NA1 and becomes an up signal UP after being logically inverted by the inverter V3. In addition, NAND gate NA9
Is supplied to the second input terminal of the NAND gate NA2, and after being logically inverted by the inverter V4, becomes the down signal DOWN. As is well known, the up signal UP raises the potential of the control voltage VC, which is the output signal of the subsequent charge pump circuit, and changes the frequency of the internal clock signal, which is the substantial output signal of the subsequent voltage controlled oscillation circuit VCO. It works to raise it. The down signal DOWN lowers the potential of the control voltage VC,
It works to lower the frequency of the internal clock signal.

As a result, the output signal n1 of the NAND gate NA1 constituting the phase comparison circuit PD is selectively set to the high level while the reference clock signal RFCK is set to the high level, as in the embodiment of FIG. The output signal n2 of the NAND gate NA2 is the feedback clock signal FBCK.
Is selectively set to the high level while the signal is set to the high level. The output signal n7 of the NAND gate NA7 is set to a low level in response to the output signal n1 of the NAND gate NA1, that is, the reference clock signal RFCK, and the output signal n2 of the NAND gate NA2, that is, the feedback clock signal FBCK, both set to the high level. The output signal n3 of the NAND gate NA4 or the output signal n4 of the NAND gate NA4 is set to the low level, and is returned to the high level.

Further, the NAND gate NA3 forms a latch circuit together with the NAND gate NA5, and the output signal n3 of the output signal n7 of the NAND gate NA7 goes low before the output signal n1 of the NAND gate NA1, that is, the reference clock signal RFCK goes low. Until it is returned, it is selectively set to the low level. Similarly, the NAND gate NA4 constitutes a latch circuit together with the NAND gate NA6, and the output signal n4 of the NAND gate NA4 is supplied to the NAND gate NA7.
After the output signal n7 is set to the low level, the output signal n2 of the NAND gate NA2, that is, the feedback clock signal FBCK
Is selectively set to the low level until is returned to the low level.

On the other hand, the output signal n8 of the NAND gate NA8, which is the inverted signal of the up signal UP, is supplied to the NAND gate NA1.
After the output signal n1, ie, the reference clock signal RFCK is set to the high level, the output signal n7 of the NAND gate NA7.
To the low level, in other words, from when the reference clock signal RFCK is set to the high level to when the feedback clock signal FBCK is set to the high level, that is, the reference clock signal R of the feedback clock signal FBCK.
During the period corresponding to the delay phase difference with respect to FCK, the signal is kept at the low level, during which the up signal UP is kept at the high level.

The output signal n9 of the NAND gate NA9, which is the inverted signal of the down signal DOWN, is output from the NAND gate N9.
The period from when the output signal n2 of A2, that is, the feedback clock signal FBCK is set to the high level to when the output signal n7 of the NAND gate NA7 is set to the low level, in other words, after the feedback clock signal FBCK is set to the high level, the reference clock signal RFCK is Until the high level, that is, the reference clock signal R of the feedback clock signal FBCK
During the period corresponding to the advance phase difference with respect to FCK, the signal is kept at the low level, and during that time, the down signal DOWN is kept at the high level.

As is clear from the above, the output signal n7 of the NAND gate NA7 which is set to the low level via the signal path B is such that the feedback clock signal FBCK is set to the high level behind the reference clock signal RFCK, or In response to the signal FBCK being set to the high level prior to the reference clock signal RFCK, the signal FBCK functions as a stop signal for returning the up signal UP (or the down signal DOWN), which is set to the high level via the signal path A, to the low level, for example. That is, the low level of the stop signal is held by the latch circuit including the NAND gates NA3 and NA5 or the NAND gates NA4 and NA6 until the reference clock signal RFCK or the feedback clock signal FBCK returns to the low level.

In the conventional PLL circuit, the NAND gate NA7 for generating the stop signal is composed of a normal CMOS (complementary MOS) NAND gate, and its transmission delay time is determined by the P-channel and N-channel MOSFETs (metal An oxide semiconductor field-effect transistor, which is a general term for an insulated gate field-effect transistor in the form of a MOSFET in this specification). Further, the transmission delay time of the NAND gate NA7 affects the phase comparison characteristic of the phase comparison circuit PD. For example, if this transmission delay time is too short, as shown in FIG. In a region where the phase difference of the clock signal FBCK is close to zero, the up signal UP and the down signal DOWN
Are generated in a so-called dead zone state in which neither of them can be generated. Conversely, if the transmission delay time of the NAND gate NA7 is too long, as shown in FIG.
And a down signal DOWN are simultaneously generated.

Up signal UP and down signal DOWN
Ideally, as shown in FIG. 11 (b), it is desirable that, even in a region where the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is close to zero, it is generated continuously with the same slope. Thus, the phase comparison circuit PD has a linear phase comparison characteristic.

However, in the conventional PLL circuit, as described above, the transmission delay time of the NAND gate NA7 is equal to the MOS delay time.
Since it is fixedly determined by the operation characteristics and the like of the FET, the MO
The dead zone state or the overlap state often occurs under the influence of process variations of the SFET, power supply voltage fluctuations, and the like. The dead zone state and the overlap state degrade the phase comparison characteristics of the phase comparison circuit PD, cause an excess or deficiency in the frequency adjustment amount with respect to the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK, and increase the frequency of the PLL circuit. Deteriorate characteristics. As a result, the frequency fluctuation of the internal clock signal becomes large, and an extra timing margin must be secured on the side of the internal clock signal receiving device, and the speed of a logic integrated circuit device such as an ASIC equipped with a PLL circuit is increased. Is restricted.

SUMMARY OF THE INVENTION It is an object of the present invention to realize a phase comparison circuit having an improved phase comparison characteristic, improve a frequency characteristic of a PLL circuit or the like including the phase comparison circuit, and implement a machine such as an ASIC equipped with the PLL circuit. The purpose is to speed up the cycle.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0017]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a PLL circuit mounted on a logic integrated circuit device such as an ASIC is configured, and when the reference clock signal is set to a high level prior to the feedback clock signal, the up signal is set to the high level, and the stop signal is set to the low level. A first logic gate for returning the signal to a low level in response to the signal, and a down signal to a high level in response to the feedback clock signal being set to a high level prior to the reference clock signal, and a stop signal to a low level. And a third logic gate for setting the stop signal to a low level when both the reference clock signal and the feedback clock signal are set to a high level. In the comparison circuit, for example, the phase comparison circuit overlaps in a region where the phase difference between the reference clock signal and the feedback clock signal is close to zero. A delay control circuit that raises the potential of the delay control signal by identifying the state of the delay control signal, and selectively reduces the transmission delay time of the third logic gate in response to the potential rise of the delay control signal. Configuration.

According to the above-described means, the phase comparison circuit in the overlap state can be returned to the dead zone state autonomously and automatically controlled so as to always have a linear phase comparison characteristic. As a result, the phase comparison characteristics of the phase comparison circuit are improved, the frequency characteristics of the PLL circuit including the phase comparison circuit are improved, the necessity of securing an unwilling timing margin in the subsequent circuit is eliminated, and the PLL circuit is mounted. The speed of a machine cycle of a logic integrated circuit device such as an ASIC can be increased.

[0019]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit including a phase comparator to which the present invention is applied. First, an outline of the configuration and operation of the PLL circuit including the phase comparison circuit of this embodiment will be described with reference to FIG. The PLL circuit of this embodiment is not particularly limited, but is mounted on a predetermined ASIC.
As a clock signal source of a digital system having C as a constituent element, based on an externally supplied reference clock signal RFCK, an internal clock signal ICK having a frequency, for example, about eight times that of the reference clock signal RFCK is generated. The circuit elements constituting each block in FIG. 1 are formed together with other circuit elements constituting the ASIC on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. Further, in the following description, the internal clock signal ICK is shown as a single-phase clock signal, but may be actually a multi-phase clock signal.

In FIG. 1, the PLL circuit receives a reference clock signal RFCK (first clock signal) at one input terminal and a feedback clock signal FBCK (second clock signal) at the other input terminal. A phase comparison circuit PD is provided. Up signal UP (first phase control signal) and down signal DOW, which are output signals of phase comparison circuit PD
N (the second phase control signal) is supplied to the charge pump circuit CP
And the control voltage VC, which is the output signal of the charge pump circuit CP, is supplied to the voltage-controlled oscillation circuit VCO. The original clock signal VCK, which is an output signal of the voltage controlled oscillator VCO, is supplied to the subsequent circuit as an internal clock signal ICK after passing through a clock buffer CB, and is also divided by a frequency dividing circuit FD at a predetermined frequency dividing ratio. After being circulated, it is supplied to the phase comparison circuit PD as a feedback clock signal FBCK.

In this embodiment, the reference clock signal R
Although FCK is not particularly limited, for example, 14.3 MHz
(Megahertz) as a relatively low frequency pulse signal having a center frequency, and an internal clock signal IC as an output signal thereof.
K is, for example, eight times the reference clock signal RFCK, that is, 1
Let 14.4 MHz be its center frequency. Therefore, the frequency division ratio of the frequency dividing circuit FD is set to 1/8, and the center frequency of the feedback clock signal FBCK is set to the reference clock signal RFCK.
14.3 MHz, which is the same as

The phase comparison circuit PD of the PLL circuit PLL
Reference clock signal RFCK and feedback clock signal FBCK
Are compared, and an up signal UP or a down signal DOWN having a pulse width corresponding to the difference is selectively generated.

That is, when the phase of the feedback clock signal FBCK lags behind the reference clock signal RFCK, the phase comparison circuit PD selectively changes the up signal UP to the power supply voltage VCC only for a period corresponding to the phase difference. A high level (hereinafter, a high level refers to a level like the power supply voltage VCC unless otherwise stated) and a down signal D
OWN remains at a low level such as the ground potential VSS (hereinafter, the low level refers to a level such as the ground potential VSS unless otherwise stated). On the contrary, the phase of the feedback clock signal FBCK is changed to the reference clock signal RFCK.
, The down signal DOWN is selectively set to the high level only for a period corresponding to the phase difference, and the up signal UP is kept at the low level. The specific configuration and operation of the phase comparison circuit PD will be described later in detail.

On the other hand, the charge pump circuit CP of the PLL circuit PLL integrates the high level of the up signal UP and the down signal DOWN which are the output signals of the phase comparison circuit PD, and controls the potential of the control voltage VC which is the output signal. .
That is, the charge pump circuit CP outputs the up signal UP
Is set to the high level, the potential of the control voltage VC is selectively increased in accordance with the pulse width, and the down signal DOWN is generated.
Is at a high level, the potential of the control voltage VC is selectively lowered according to the pulse width. Control voltage VC
Is supplied to the voltage-controlled oscillation circuit VCO as described above.

The voltage controlled oscillation circuit VCO controls the frequency, that is, the phase of the source clock signal VCK, which is the output signal, according to the potential of the control voltage VC supplied from the charge pump circuit CP. That is, the voltage-controlled oscillation circuit VCO increases the frequency of the source clock signal VCK as the potential of the control voltage VC increases, and advances the phase. Further, as the potential of the control voltage VC decreases, the frequency of the source clock signal VCK is reduced, and the phase thereof is delayed. As a result, the original clock signal VCK becomes
The center frequency is controlled to converge to eight times the reference clock signal RFCK, that is, 114.4 MHz, whereby the phase of the feedback clock signal FBCK is controlled to match the reference clock signal RFCK.

FIG. 2 is a circuit diagram of a first embodiment of the phase comparator PD included in the PLL circuit PLL of FIG. FIG. 3 is a circuit diagram of an embodiment of a variable delay gate, that is, a NAND gate NA7 included in the phase comparison circuit PD of FIG. 2, and FIG. 4 is a circuit diagram of an embodiment of the delay control circuit DC. It is shown. The specific configuration and operation of the phase comparison circuit PD included in the PLL circuit PLL of this embodiment will be described with reference to these drawings. In the following circuit diagrams, the MOSFET with an arrow at the channel (back gate) portion is a P-channel type, and the N-channel MOSFET without the arrow is
Are shown separately from

In FIG. 2, the phase comparison circuit PD of this embodiment is not particularly limited, but its second input terminal receives a NAND gate NA1 receiving an inverted signal of the reference clock signal RFCK by the inverter V1, and its first input. A terminal includes a NAND gate NA2 for receiving an inverted signal of the feedback clock signal FBCK by the inverter V2. The output signal n8 of the NAND gate NA8 (first logic gate) is supplied to the first input terminal of the NAND gate NA1, and the output signal n1 is supplied to the NAND gates NA3 and N3.
A7 and the first input terminal of NA8. The output signal n9 of the NAND gate NA9 (second logic gate) is supplied to the second input terminal of the NAND gate NA2, and the output signal n2 is supplied to the second input terminal of the NAND gate NA4, the NAND gate NA7 (third input). Of the NAND gate NA9 and the third input terminal of the NAND gate NA9.

The output signal n5 of the NAND gate NA5 is supplied to a second input terminal of the NAND gate NA3, and the output signal n3 is supplied to the first input terminal of the NAND gate NA5 and the second input terminals of the NAND gates NA7 and NA8. Supplied. An output signal n6 of the NAND gate NA6 is supplied to a first input terminal of the NAND gate NA4, and the output signal n4 is supplied to second input terminals of the NAND gates NA6 and NA9 and a third input terminal of the NAND gate NA7. Is done. The output signal n7 of the NAND gate NA7 is supplied to the second input terminal of the NAND gate NA5 and the first input terminal of the NAND gate NA6. The output signal n7 of the NAND gate NA7 is further supplied to a third input terminal of the NAND gate NA8 and a first input terminal of the NAND gate NA9. NAND gate N
The output signal n8 of A8 becomes the up signal UP after further passing through the inverter V3, and the output signal n9 of the NAND gate NA9 becomes the down signal DO after passing through the inverter V4.
WN.

In this embodiment, the NAND gate NA7
Is a variable delay gate to which a delay control signal GDC is supplied from a delay control circuit DC.
The NAND gate NA8 is connected to the upper terminal of the delay control circuit DC.
The output signal n8 of the NAND gate NA9 is supplied to the lower terminal thereof.

Here, the NAND gate NA7, which is a variable delay gate, is not particularly limited, but is provided in parallel between a power supply voltage VCC (first power supply voltage) and its output node n7 as shown in FIG. P-channel MOSFETs P1 (third MOSFET), P2, P
3 and P4 (fourth MOSFET), and an N-channel MOSFET N5 provided in series between output node n7 and ground potential VSS (second power supply voltage).
(Seventh MOSFET), N1 (fifth MOSFET
T), N2, N3 and N4 (sixth MOSFET)
And

The gates of the MOSFETs P1 and N1
The output signal n1 of the NAND gate NA1 is supplied in common,
The output signal n2 of the NAND gate NA2 is commonly supplied to the gates of the MOSFETs P4 and N4. Also, MO
The gates of the SFETs P2 and N2 have a NAND gate NA.
3 is supplied in common and the MOSFET P3
And N3, the output signal n4 of the NAND gate NA4 is commonly supplied. The gate of the MOSFET N5 is supplied with a delay control signal GDC from the delay control circuit DC, and the MOSFET 5 is further provided with an N-channel MOSFET N6 having a gate receiving the power supply voltage VCC in a parallel form.

For these reasons, the MOSFETs P1 to P4 of the NAND gate NA7 are connected to the corresponding NAND gates NA7.
1, NA3, NA4 or NA2 output signal n1, n
3, n4 or n2 is set to a low level, that is, an invalid level, and each is selectively turned on. In response to this, the output signal n7 of the NAND gate NA7 is selectively set to a high level, that is, an invalid level. The MOSFETs N1 to N4 of the NAND gate NA7 are selectively turned on when the output signal n1, n3, n4 or n2 of the corresponding NAND gate NA1, NA3, NA4 or NA2 is set to a high level, that is, an effective level. Provided that all of the output signals n1, n3, n4 and n2 are at a high level.
The output signal n7 of A7 is selectively set to a low level, that is, an effective level.

By the way, the MOSF of the NAND gate NA7
The ETN 6 is constantly turned on when the power supply voltage VCC is supplied to its gate, and flows a bias current according to its conductance. In addition, MOSFET N5
When the delay control signal GDC is supplied to its gate, its conductance changes according to the potential of the delay control signal GDC, and an additional current according to the conductance flows.

That is, the conductance of the MOSFET 5 increases as the potential of the delay control signal GDC increases, whereby the additional current flowing through the MOSFET N5 increases. On the other hand, MOSFETN
5 becomes lower as the potential of the delay control signal GDC becomes lower.
The additional current flowing through ETN5 is reduced.

When the additional current flowing through the MOSFET N5 is large, the change of the output signal n7 of the NAND gate NA7 from the high level, that is, the invalid level, to the low level, that is, the valid level becomes faster, and the transmission delay time as the NAND gate NA7 becomes shorter. On the other hand, when the additional current flowing through the MOSFET N5 decreases, the change of the output signal n7 of the NAND gate NA7 from the high level to the low level becomes slow, and the transmission delay time of the NAND gate NA7 becomes long. As a result, the NAND gate NA7 acts as a variable delay gate whose transmission delay time is changed according to the potential of the delay control signal GDC, which is a feature of the present invention.

As will be described later, when the transmission delay time of the NAND gate NA7 is reduced, the output signal n serving as a stop signal is reduced.
7 changes to the low level faster, and the NAND gate NA
8 and NA9 are closed earlier, and the pulse widths of the up signal UP and the down signal DOWN, which are the output signals of the phase comparison circuit PD, are reduced. As a result, in a region where the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is close to zero, the phase comparison characteristic of the phase comparison circuit PD changes from the overlap state where the up signal UP and the down signal DOWN are simultaneously at the high level. The state shifts to the dead zone state side in which none is set to the high level.

On the other hand, if the transmission delay time of the NAND gate NA7 becomes longer, the change of the output signal n7, which is a stop signal, to a low level becomes slow, and the NAND gates NA8 and NA7
9 is delayed, and the phase comparison circuit PD
Up signal UP and down signal DOWN as output signals of
Becomes longer. As a result, the reference clock signal R
In a region where the phase difference between the FCK and the feedback clock signal FBCK is close to zero, the phase comparison characteristic of the phase comparison circuit PD changes from the dead zone state in which neither the up signal UP nor the down signal DOWN is set to the high level, and both of them are simultaneously high. It shifts to the overlap state side which is the level.

Next, the delay control circuit D of the phase comparison circuit PD
C is not particularly limited, but as shown in FIG. 4, two P-channel MOSFETs P5 (the first P-channel MOSFETs P5) are provided in series between the power supply voltage VCC and its output node GDC.
MOSFET) and P6 (second MOSFET);
Capacitance means provided between output node GDC and ground potential VSS, that is, capacitance C1 is included. Of these, MOSFE
The output signal n of the NAND gate NA8 is connected to the gate of TP5.
8 is supplied, and the output signal n9 of the NAND gate NA9 is supplied to the gate of the MOSFET P6. Also, the capacity C
1 is a resistance means having a predetermined resistance value, that is, a resistance R1.
Are provided in a parallel configuration.

The capacitance C1 of the delay control circuit DC is
When ETP5 and P6 are both turned on, in other words, output signals n8 and n9 of NAND gates NA8 and NA9 are both at low level, and up signal U
When the P and the down signal DOWN are simultaneously at the high level and in the overlap state, they are selectively charged, and in response thereto, the potential of the delay control signal GDC, which is the output signal of the delay control circuit DC, increases. Further, the phase comparison circuit PD is released from the overlap state, and the MOSFET
When either P5 or P6 is turned off, the capacitance C1
Is gradually discharged via the resistor R1, and the potential of the delay control signal GDC decreases.

As described above, when the potential of the delay control signal GDC increases, the NAND gate NA7 of the phase comparator PD
, And the phase comparison characteristic of the phase comparison circuit PD shifts from the overlap state to the dead zone state. When the delay control signal GDC becomes low,
The transmission delay time of the NAND gate NA7 of the phase comparison circuit PD increases, and the phase comparison characteristic of the phase comparison circuit PD shifts from the dead zone state to the overlap state. As a result, the phase comparison characteristic of the phase comparison circuit PD is corrected to be an ideal linear state by itself, which will be described later in detail together with the specific operation of the phase comparison circuit PD.

FIG. 5 is a signal waveform diagram of one embodiment of the phase comparison circuit PD of FIG. 2, and FIG. 6 is an enlarged signal waveform diagram of one embodiment centered on the timing T2. It is shown. FIG. 7 shows the phase comparison circuit PD of FIG.
FIG. 2 shows an operation characteristic diagram of one embodiment. The specific operation, phase comparison characteristics, and characteristics of the phase comparison circuit PD of this embodiment will be described with reference to these drawings.

FIG. 5 shows timing T1 as
The feedback clock signal FBCK is equal to the reference clock signal RFCK.
The clock cycle which is set to the effective level, that is, the high level, is illustrated later. Further, as the timing T2, the feedback clock signal FBCK and the reference clock signal RFCK
Exemplifies a clock cycle in which the feedback clock signal FBCK is at the high level at the same time.
Exemplifies a clock cycle that is set to a high level prior to the reference clock signal RFCK. In the following description of the operation description, please refer to FIGS.

In FIG. 5, a reference clock signal RF supplied from an external clock generator to a PLL circuit PLL is provided.
CK is a pulse signal having a duty of about 50%, and its center frequency is, for example, 14.3 MHz as described above.
It is said.

When both the reference clock signal RFCK and the feedback clock signal FBCK are at the low level, the phase comparison circuit PD outputs the output signals n1 to n2 and n5 to n5 of the NAND gates NA1 to NA2 and NA5 to NA6.
n6 (hereinafter, internal signals n1 to n2 and n5, respectively)
To n6) are at the low level, and the NAND gate N
Output signals n3 to A3 to NA4 and NA7 to NA9
n4 and n7 to n9 (hereinafter referred to as internal signal n3, respectively)
To n4 and n7 to n9) are at a high level. As a result, both the up signal UP and the down signal DOWN, which are inverted signals of the internal signal n8 or n9, are set to low level.

At timing T1, when the reference clock signal RFCK is set to a high level prior to the feedback clock signal FBCK, the phase comparator PD raises the reference clock signal RFCK (here, for example, from the low level of the reference clock signal RFCK to the low level). The change to the high level is referred to as “rising”. The same applies hereinafter) and the internal signal n8.
, The output signal of the NAND gate NA1, that is, the internal signal n1 is set to the high level. Further, in response to the rise of the internal signal n1 and the high level of the internal signals n3 and n7, the output signal of the NAND gate NA8, that is, the internal signal n8 is set to the low level.
(Here, the change of the internal signal n8 from the high level to the low level is referred to as “falling”.
After that, the up signal UP is set to the high level.

When the feedback clock signal FBCK is set to the high level with a delay of a predetermined phase difference, the phase comparator PD receives the rising of the feedback clock signal FBCK and the high level of the internal signal n9, and outputs the output of the NAND gate NA2. The signal, that is, the internal signal n2 is set to the high level. Further, in response to the rise of the internal signal n2 and the high level of the internal signals n1, n3 and n4, the output signal of the NAND gate NA7 as the stop signal, that is, the internal signal n7 is made low.

As a result, the internal signal n8 is returned to the high level, and in response to the rise of the internal signal n8, the up signal UP is returned to the low level, and the internal signals n5 and n6 are set to the high level. Signal n
5 and n6, the internal signals n3 and n6
4 is at the low level. Further, the internal signals n5 and n5
6, the internal signal n7 is returned to the high level, but since the internal signal n3 is at the low level, the internal signal n8 holds the high level and the up signal U
P remains at low level. The internal signals n5 and n6, which are the output signals of the NAND gates NA5 and NA6, keep the high level in response to the low level of the internal signal n3 or n4 even after the internal signal n7 is returned to the high level.

When the reference clock signal RFCK is returned to the low level, the falling of the reference clock signal RFCK and the high level of the internal signal n8 receive the internal signal n.
1 is returned to the low level. In response to the fall of the internal signal n1, the internal signal n3 is returned to a high level,
In response to the rise of the internal signal n3 and the high level of the internal signal n7, the internal signal n5 is returned to the low level.

Further, when the feedback clock signal FBCK is returned to the low level with a delay corresponding to the phase difference, the falling of the feedback clock signal FBCK and the high level of the internal signal n9 cause the internal signal n2 to become Returned to level. In response to the falling of the internal signal n2, the internal signal n4 is returned to the high level. In response to the rising of the internal signal n4 and the high level of the internal signal n7, the internal signal n6 is returned to the low level. The phase comparison circuit PD is returned to the initial state.

As a result, the up signal UP is output from the time when the reference clock signal RFCK is set to the high level to the time when the feedback clock signal FBCK is set to the high level, that is, the reference clock signal RFCK of the feedback clock signal FBCK.
And the potential of the control voltage VC, which is the output signal of the charge pump circuit CP in the subsequent stage, rises by a period corresponding to the pulse width.

On the other hand, at timing T3 when the feedback clock signal FBCK is set to a high level earlier than the reference clock signal RFCK, the phase comparator PD receives the rising of the feedback clock signal FBCK and the high level of the internal signal n9. The internal signal n2 is set to a high level. Further, the rise of the internal signal n2 and the internal signals n4 and n7
, The internal signal n9 is set to low level, and in response to the fall of the internal signal n9, the down signal DOWN is set to high level.

When the reference clock signal RFCK is set to the high level with a delay of a predetermined phase difference, the phase comparison circuit PD receives the rising of the reference clock signal RFCK and the high level of the internal signal n8, and changes the internal signal n1 to the internal signal n1. High level. Further, in response to the rise of the internal signal n1 and the high levels of the internal signals n2, n3 and n4, the internal signal n7 as a stop signal is set to a low level.

As a result, the internal signal n9 is returned to the high level, and in response to the rise of the internal signal n9, the down signal DOWN is returned to the low level. Further, the internal signals n5 and n6 are set to the high level, and in response to the rise of the internal signals n5 and n6, the internal signals n3 and n4 are set to the low level. Further, in response to the falling of the internal signals n5 and n6, the internal signal n7 is returned to the high level. However, since the internal signal n4 is at the low level, the internal signal n9 holds the high level and the down signal DOWN is It is kept at low level. The internal signals n5 and n6 remain after the internal signal n7 is returned to the high level.
Similarly, it receives the low level of the internal signal n3 or n4 and holds the high level.

When the feedback clock signal FBCK is returned to the low level, the falling of the feedback clock signal FBCK and the high level of the internal signal n9 receive the internal signal n.
2 is returned to the low level. In response to the fall of the internal signal n2, the internal signal n4 is returned to a high level,
In response to the rise of the internal signal n4 and the high level of the internal signal n7, the internal signal n6 is returned to the low level.

Further, when the reference clock signal RFCK is returned to the low level with a delay corresponding to the phase difference, the internal signal n1 receives the falling edge of the reference clock signal RFCK and the high level of the internal signal n8, and receives the internal signal n1. Returned to level. In response to the falling of the internal signal n1, the internal signal n3 is returned to the high level. In response to the rising of the internal signal n3 and the high level of the internal signal n7, the internal signal n5 is returned to the low level. The phase comparison circuit PD is returned to the initial state.

As a result, the down signal DOWN is generated from the time when the feedback clock signal FBCK is set to the high level until the reference clock signal RFCK is set to the high level, that is, the reference clock signal RF of the feedback clock signal FBCK.
The signal is set to the high level for a period corresponding to the advance phase difference with respect to CK, and the potential of the control voltage VC, which is the output signal of the subsequent charge pump circuit CP, increases by the amount corresponding to the pulse width.

Next, at the timing T2 when the reference clock signal RFCK and the feedback clock signal FBCK are set to the high level almost at the same time, the phase comparator PD in FIG.
As shown by the bold solid line in the enlarged signal waveform diagram of FIG. 7, the internal signal n1 is set to the high level in response to the rising of the reference clock signal RFCK and the high level of the internal signal n8, and the rising of the feedback clock signal FBCK. And the high level of the internal signal n9, the internal signal n2 is set to the high level. Also, the internal signal n8 is set to a low level in response to the rising of the internal signal n1 and the high level of the internal signals n3 and n7, and the internal signal is set in response to the rising of the internal signal n2 and the high level of the internal signals n4 and n7. n9 is also at the low level.

However, in response to the rise of the internal signals n1 and n2 and the high levels of the internal signals n3 and n4, the internal signal n7 as a stop signal is made low at almost the same time, so that the internal signals n8 and n9 are immediately high. The level is returned to the level, and both the up signal UP and the down signal DOWN do not reach the high level.

When the reference clock signal RFCK and the feedback clock signal FBCK are returned to the low level, the phase comparator PD receives the fall of the reference clock signal RFCK and the high level of the internal signal n8, and the internal signal n1 goes to the low level. In response to the fall of the feedback clock signal FBCK and the high level of the internal signal n9, the internal signal n2 is returned to the level. Also, internal signals n1 and n1
2, the internal signals n3 and n4 are returned to the high level. In response to the rising of the internal signals n3 and n4 and the high level of the internal signal n7, the internal signals n5 and n6 are returned to the low level. Then, the phase comparison circuit PD is returned to the initial state.

As a result, the up signal UP and the down signal DOWN are both kept at the low level without being set to the high level, and the potential of the control voltage VC, which is the output signal of the subsequent charge pump circuit CP, is not changed.

As is clear from the above description, the output signal of the NAND gate NA7 constituting the phase comparison circuit PD, that is, the internal signal n7 acts as a stop signal.
Up signal U which has once become a valid level, that is, a high level
The P and the down signal DOWN are returned to the invalid level, that is, the low level, when the internal signal n7 is set to the valid level, that is, the low level. Therefore, the NAND gate NA7
Is a region where the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is close to zero, that is, for example, at this timing T2, the rise time, fall time, and pulse width of the up signal UP and the down signal DOWN. , And the phase comparison characteristic of the phase comparison circuit PD.

That is, when the transmission delay time of the NAND gate NA7 is too short, as shown in FIG. 7A, the NAND gates NA8 and NA9 serving as the generation gates of the up signal UP and the down signal DOWN are correspondingly relatively fast. Closing at the timing, the phase comparison circuit PD enters a dead zone state in which both the up signal UP and the down signal DOWN cannot be generated. Conversely, if the transmission delay time of the NAND gate NA7 is too long, the closing timing of the NAND gates NA8 and NA9 is correspondingly delayed as shown in FIG. 7C, and the phase comparison circuit PD outputs the up signal UP and An overlap state occurs in which the down signals DOWN are simultaneously generated.

Up signal UP and down signal DOWN
Ideally, as shown in FIG. 7 (b), it is desirable that, even in a region where the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is close to zero, it is continuously generated with the same gradient. Thus, the phase comparison circuit PD has a linear phase comparison characteristic.

However, in the conventional PLL circuit, as described above, the transmission delay time of the NAND gate NA7 is equal to the MOS delay time.
Since it is fixedly determined by the operation characteristics and the like of the FET, the MO
In many cases, the dead zone state or the overlap state occurs due to the influence of the process variation of the SFET and the fluctuation of the power supply voltage.
, The frequency characteristics of the PLL circuit are deteriorated, and the increase in the speed of the machine cycle of the ASIC equipped with the PLL circuit is restricted.

In order to cope with this, in the phase comparison circuit PD of this embodiment, as described above, the NAND gate NA7 for generating the internal signal n7 as a stop signal comprises a variable delay gate, and the transmission delay time thereof is It is selectively changed according to the output signal of the delay control circuit DC for identifying the state, that is, the delay control signal GDC.

That is, as shown by a thin solid line in FIG. 6, for example, the phase comparison circuit PD is in the overlapping state, and the phase difference between the reference clock signal RFCK and the feedback clock signal FBCK is close to zero at the timing T2.
As described above, when the up signal UP and the down signal DOWN are simultaneously set to the high level, the phase comparison circuit PD of this embodiment receives the low levels of the internal signals n8 and n9 and receives the MOSFET P5 of the delay control circuit DC as described above. P
6 are simultaneously turned on. Therefore, these MOS
The capacitor C1 is charged via the FETs P5 and P6,
The potential of the delay control signal GDC rises and the NAND gate N
The conductance of the MOSFET N5 of A7 increases, and the transmission delay time of the NAND gate NA7 decreases. As a result, the phase comparison circuit PD is controlled to change to the dead zone state side, as indicated by the arrow in FIG. 7C, and is eventually released from the overlap state.

On the other hand, as shown in FIG. 7A, the phase comparison circuit PD outputs an up signal UP and a down signal DOW.
In a dead zone state where none of N can be generated, the MOSFETs P5 and P6 of the delay control circuit DC are turned off. For this reason, the capacitor C1 is gradually discharged via the resistor R1, and the potential of the delay control signal GDC decreases, so that the MOSFET N5 of the NAND gate NA7
Becomes smaller, and the transmission delay time of the NAND gate NA7 becomes longer. Thereby, the phase comparison circuit P
D is controlled to change to the overlap state, as indicated by an arrow in FIG. 7A, and is eventually released from the dead zone state.

Hereinafter, the phase comparison circuit PD moves between an extremely small overlap state and an extremely small dead zone state, and its average phase comparison characteristic is shown in FIG.
This is close to the ideal state of (b). As a result, the phase comparison characteristic of the phase comparison circuit PD is improved, and the phase comparison circuit PD is improved.
By improving the frequency characteristics of the PLL circuit including the above, it is possible to eliminate the necessity of securing an unwilling timing margin in the subsequent circuit, and to speed up the machine cycle of the ASIC equipped with the PLL circuit.

The functions and effects obtained from the above embodiments are as follows. That is, (1) a PL mounted on a logic integrated circuit device such as an ASIC.
An L circuit is configured to set an up signal to a high level when the reference clock signal is set to a high level prior to the feedback clock signal, and to return the stop signal to a low level when the stop signal is set to a low level. And a second signal for returning the down signal to a high level in response to the feedback clock signal being set to a high level prior to the reference clock signal, and returning the same to a low level in response to the stop signal being set to a low level. A phase comparison circuit including a logic gate and a third logic gate that sets the stop signal to a low level in response to both the reference clock signal and the feedback clock signal being set to a high level, for example, the reference clock signal and the feedback clock signal. In the region where the phase difference is close to zero, it is recognized that the phase comparison circuit is in the overlap state, and the potential of the delay control signal is selectively raised. A delay control circuit for providing said third
Logic gates are variable delay gates, and the transmission delay time can be selectively shortened in response to the potential rise of the delay control signal. The effect of being able to return to the zone state side is obtained.

(2) According to the above item (1), an effect is obtained that the phase comparison circuit automatically controls to always have a linear phase comparison characteristic, and the phase comparison characteristic can be improved. (3) According to the above items (1) and (2), it is possible to improve the frequency characteristics of a PLL circuit or the like including a phase comparison circuit, and eliminate the necessity of securing an unwilling timing margin in a subsequent circuit. The effect is obtained. (4) According to the above items (1) to (3), an effect that a machine cycle of an ASIC or the like having a PLL circuit mounted thereon can be speeded up is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the PLL circuit PLL can include, for example, various compensation circuits for improving disturbance characteristics, and the block configuration can take various embodiments. Further, the reference clock signal RFCK and the primitive clock signal VC
K, the frequency of the internal clock signal ICK and the frequency of the feedback clock signal FBCK and their ratios can be set arbitrarily.

In FIG. 2, the circuit configuration of the phase comparison circuit PD can be variously considered without being restricted by the present embodiment. Further, a NAND gate N serving as a third logic gate
A7 can be replaced with a normal NAND gate NA7 and a buffer V5 as a variable delay gate, for example, as shown in FIG. In this case, the NAND gate NA7 for setting the logical condition of the internal signal n7 and the variable delay gate or buffer V5 for setting the transmission delay time thereof are separated to relatively easily set the logical condition and the timing condition of the internal signal n7. it can. The buffer V5 serving as the variable delay gate includes P-channel MOSFETs P8 and P9 provided in parallel between the P-channel MOSFET P7 and the output node n7, as illustrated in FIG. Among them, an inverted delay control signal GDCB corresponding to an inverted signal of the delay control signal GDC is supplied from the delay control circuit DC to the gate of the MOSFET P8,
The gate of FET P9 is constantly coupled to ground potential VSS.

In FIG. 3, the concrete configuration of the NAND gate NA7 as a variable delay gate can take various embodiments, and various methods for controlling the transmission delay time can be considered. In FIG. 4, the specific configuration of the delay control circuit DC is not restricted by the present embodiment, and the phase comparison circuit P
Various methods for controlling the potential of the delay control signal GDC according to the state of D may be considered. The potential control of the delay control signal GDC can be performed by identifying not only the overlap state but also the dead zone state. 5 and 6, the effective level and the absolute time relationship of each signal do not limit the gist of the present invention. In FIG.
The phase comparison characteristic of the phase comparison circuit PD is only an example and does not affect the gist of the present invention.

In the above description, the invention made mainly by the present inventor is referred to as the application field AS
The case where the present invention is applied to a PLL circuit mounted on an IC and a phase comparison circuit thereof has been described. However, the present invention is not limited thereto. For example, a phase comparison circuit or a PLL circuit formed as a single unit, a phase comparison circuit or PLL
The present invention can be applied to various memory integrated circuit devices and logic integrated circuit devices including circuits, and various systems including such memory integrated circuit devices or logic integrated circuit devices. INDUSTRIAL APPLICABILITY The present invention is widely applicable to at least a phase comparison circuit that can be in an overlap state or a dead zone state, and an apparatus or system including the same.

[0075]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the P mounted on an ASIC or the like
An LL circuit is configured to set an up signal to a high level when the reference clock signal is set to a high level prior to the feedback clock signal, and to return the stop signal to a low level when the stop signal is set to a low level. And a second signal for returning the down signal to a high level in response to the feedback clock signal being set to a high level prior to the reference clock signal, and returning the same to a low level in response to the stop signal being set to a low level. A phase comparison circuit including a logic gate and a third logic gate that sets the stop signal to a low level in response to both the reference clock signal and the feedback clock signal being set to a high level. In the region where the phase difference of the signal is close to zero, the phase comparison circuit identifies the overlap state and raises the potential of the delay control signal. The delay control circuit is provided, a third logic gate propagation delay time of, and selectively be shortened configuration receives the potential rise of the delay control signal.

As a result, the phase comparison circuit in the overlap state is returned to the dead zone state autonomously,
It can be automatically controlled to always have a linear phase comparison characteristic. As a result, the phase comparison characteristics of the phase comparison circuit are improved, the frequency characteristics of the PLL circuit and the like including the phase comparison circuit are improved, and the need for securing an unwilling timing margin in the subsequent circuit is eliminated. The machine cycle of a logic integrated circuit device such as an ASIC to be mounted can be speeded up.

[Brief description of the drawings]

FIG. 1 shows a PL including a phase comparison circuit to which the present invention is applied.
FIG. 3 is a block diagram showing one embodiment of an L circuit.

FIG. 2 is a circuit diagram showing a first embodiment of a phase comparison circuit of the PLL circuit of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a NAND gate NA7 as a variable delay gate of the phase comparison circuit of FIG. 2;

FIG. 4 is a circuit diagram showing one embodiment of a delay control circuit of the phase comparison circuit of FIG. 2;

FIG. 5 is a signal waveform diagram showing one embodiment of the phase comparison circuit of FIG. 2;

FIG. 6 is an enlarged signal waveform diagram showing one embodiment of the phase comparison circuit of FIG. 2;

FIG. 7 is an operation characteristic diagram showing one embodiment of the phase comparison circuit of FIG. 2;

FIG. 8 is a circuit diagram showing a second embodiment of the phase comparator of the PLL circuit of FIG. 1;

9 is a circuit diagram showing one embodiment of an inverter V5 as a variable delay gate of the phase comparison circuit of FIG.

FIG. 10 is a circuit diagram illustrating an example of a phase comparison circuit of the PLL circuit.

11 is an operation characteristic diagram illustrating an example of the phase comparison circuit in FIG.

[Explanation of symbols]

PLL: PLL (Phase Locked Loop) circuit, P
D: phase comparison circuit, CP: charge pump circuit, V
CO: voltage-controlled oscillator, FD: frequency divider, CB
…… Clock buffer, RFCK …… Reference clock signal, FBCK …… Feedback clock signal, UP …… Up signal, DOWN …… Down signal, VC …… Control voltage, VC
K: primitive clock signal, ICK: internal clock signal. DC: delay control circuit, GDC: delay control signal.
T1 to T3 timing. GDCB... Inversion delay control signal. P1 to P9: P-channel MOSFET, N1
To N7 ... N-channel MOSFET, V1 to V5 ...
Inverter (V5 in FIG. 8 is a variable delay inverter), NA
1 to NA9 ... NAND gate (NA7 in Fig. 2 is a variable delay gate), R1 ... resistor, C1 ... capacitance, n1 to n9 ...
... internal node or internal signal.

Claims (6)

[Claims] 1. A method for identifying a phase difference between a first clock signal and a second clock signal generated based on the first clock signal to advance a phase of the second clock signal. And a second phase control signal for delaying the phase of the second clock signal, wherein the first phase control signal selectively delays the phase of the second clock signal. In the region where the phase difference is close to zero, the overlap state in which the first and second phase control signals are simultaneously generated or the dead zone state in which neither of them is generated is identified, and the phase comparison characteristic is corrected by itself. A phase comparison circuit having a function that can be performed. 2. The phase comparison circuit according to claim 1, wherein the first phase control signal is valid when the first clock signal is set to a valid level prior to the second clock signal. A first logic gate for returning the stop signal to an invalid level in response to the change of the stop signal to a valid level; and a second logic gate for setting the second clock signal to a valid level prior to the first clock signal. Receiving the second phase control signal, setting the second phase control signal to an effective level, receiving the stop signal being set to an effective level, and returning the stop signal to an invalid level; and the first and second clock signals. Are set to the valid level, and the stop signal is set to the valid level.
Wherein the correction of the phase comparison characteristic is performed by controlling a transmission delay time of the third logic gate. 3. The phase comparison circuit according to claim 1, wherein the correction of the phase comparison characteristic is performed by identifying the overlap state. And a delay control circuit for selectively increasing the potential of a delay control signal as an output signal when both of the control signals are at valid levels, wherein the transmission delay time of the third logic gate is A phase comparison circuit characterized in that the potential is shortened by increasing the potential of a control signal. 4. The delay control circuit according to claim 3, wherein the delay control circuit is provided in series between a first power supply voltage and an output node thereof, and receives an effective level of the first or second phase control signal. First and second MOSFETs, each of which is selectively turned on, a capacitance means provided between its output node and a second power supply voltage, and a resistance means provided in parallel with the capacitance means. A phase comparison circuit characterized by comprising: 5. The logic circuit according to claim 2, wherein the third logic gate is provided in parallel between a first power supply voltage and an output node thereof, and wherein the third logic gate is provided in parallel with the first power supply voltage. The third and fourth MOSFETs, each of which is selectively turned on in response to the invalid level of the second clock signal, are provided in series between an output node thereof and a second power supply voltage. Alternatively, the semiconductor device includes fifth and sixth MOSFETs selectively turned on in response to an effective level of the second clock signal, and a seventh MOSFET having a gate receiving the delay control signal. And a phase comparison circuit. 6. The phase comparison circuit according to claim 1, wherein the phase comparison circuit is included in a PLL circuit mounted as a module in a predetermined logic integrated circuit device. A phase comparison circuit characterized by the following.