JP2001077307A - Input protective circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the trigger voltage of the snap back of an n-type MOSFET used in an input protective circuit without breaking a protective element itself. SOLUTION: An input protective circuit is provided with an n-type MOSFET 1 the drain D of which is connected to an input terminal Vin for an internal element, and the source S of which is connected to a ground GND together with a substrate B and a first diode row 2 which are successively connected in series between the input terminal Vin and ground GND. In addition, the gate G of the MOSFET 1 is connected to a junction N1 which divides the first diode row 2 into tow parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit for protecting an internal element by short-circuiting an overvoltage at an input terminal without causing destruction of the protection element itself.

[0002]

2. Description of the Related Art When an excessive voltage such as a surge voltage is applied to an input terminal of a semiconductor device, internal elements are destroyed,
To prevent the semiconductor device from becoming inoperable, an input protection circuit is required. FIG. 5 shows a configuration of a conventional general input protection circuit. This conventional circuit,
The drain D is connected to the input terminal Vin for the internal element to be protected, and the source S and the gate G are connected to the substrate B
, NMOSFET connected to ground GND
(N type Metal Oxide Semiconductor Field Effect Tr
ansistor) 101. When a negative overvoltage is applied to the input terminal Vin of such an input protection circuit, the voltage between the drain D of the nMOSFET 101 and the substrate B is increased.
The n-junction is forward biased and the current is
Since the current flows to D, destruction of the internal element is prevented. on the other hand,
When a positive overvoltage is applied, the nMOSFET 10
1 performs a parasitic bipolar operation, and the current is
Since the current flows to D, destruction of the internal element is prevented. The parasitic bipolar operation is a phenomenon that occurs when a current flows through a substrate, a voltage drop occurs due to a substrate resistance, and a parasitic bipolar transistor composed of a source S-substrate B-drain D conducts, and as shown in FIG. Has a current-voltage characteristic called snapback. Here, the voltage Vt1 that shifts from the high resistance region to the low resistance region is called a trigger voltage, and this trigger voltage needs to be set lower than the breakdown voltage of the internal element (normally, the breakdown voltage of the gate oxide film). is there.

The disadvantages of the conventional input protection circuit as shown in FIG. That is, the gate oxide film thickness of the MOSFET is 7 to 8 nm in the generation with a gate length of 0.35 μm, 5 to 6 nm in the generation with a gate length of 0.25 μm, and the gate length is 0 to 0 nm.
In the 18 μm generation, the thickness becomes smaller with each generation, such as 3.5 to 4 nm. Since the dielectric breakdown voltage of the gate oxide film is approximately 15 MV / cm in terms of electric field, it is 10 to 12 V for the generation with the gate length of 0.35 μm, 7 to 9 V for the generation with the gate length of 0.25 μm, and the gate length is 0.18 μm.
It is about 5-6V for m generations. Since the overvoltage applied to the input terminal is instantaneous, even if a voltage higher than the above-mentioned breakdown voltage is applied, the gate oxide film will not be destroyed immediately, but it will lead to deterioration in reliability due to characteristic fluctuations etc. Is no different. For this reason, in the conventional input protection circuit shown in FIG. 5, since the trigger voltage of snapback is high, there has been a problem that the internal elements cannot be completely protected with miniaturization of the elements.

To solve such a problem, an input protection circuit improved from the configuration shown in FIG. 5 has been proposed (Charvaka Duvvury and Carlos Diaz: "Dynamic gate c").
oupling of nMOS for efficient output ESD protectio
n ", IEEE International Reliability Physics Symposiu
m Proceedings, pp. 141-150 (1992)). FIG. 6 shows a configuration of a conventional improved input protection circuit. In this conventional circuit, an nMOSFET 1 having a drain D connected to an input terminal Vin for an internal element to be protected and a source S connected to a ground GND together with a substrate B
01, a MOSFET formed of a field oxide film (hereinafter referred to as a MOSFET) having a drain D connected to the gate G of the nMOSFET 101, a gate G connected to the input terminal Vin, and a source S connected to the ground GND together with the substrate B. Field MOSFET 102).

The input terminal V of the input protection circuit shown in FIG.
When a negative overvoltage is applied to in, a current flows to the ground GND via the drain D-substrate B of the nMOSFET 101 as in the conventional circuit shown in FIG.
The destruction of the internal element connected to the input terminal Vin is prevented. On the other hand, when a positive overvoltage is applied, the gate voltage of the field MOSFET 102 increases, and the gate G of the field MOSFET 102 and the nMOSFET 1
The voltage determined by the capacitance division ratio of each of the gates 01 is
It affects the gate G of the nMOSFET 101. as a result,
Since the channel of the nMOSFET 101 opens and the trigger voltage of snapback decreases as indicated by Vt1 'in FIG. 7, it is possible to prevent the destruction of the internal element having a thinner gate oxide film. .

[0006]

However, in the input protection circuit shown in FIG.
02 is easily broken. That is, at the time of abnormal input, a voltage determined by the capacitance division between the gate of the field MOSFET 102 and the gate of the nMOSFET 101 is applied to each gate. However, the gate capacitance of the nMOSFET 101 is overwhelmingly larger (the gate capacitance is larger than that of the field oxide film). (The oxide film is overwhelmingly thin.)
Therefore, as a result, most of the voltage is
It will be at the gate of T102. However, the oxide film is generally thin in the overlap region between the gate and the source and drain of the field MOSFET. If the field is LOCOS (Local Oxidation
Of silicon, the oxide film is gradually thinned at both ends, and when the field is formed by a trench, the overlap region between the source and the drain is the gate. The oxide film itself. Therefore, in any case, it is unavoidable that dielectric breakdown of the oxide film easily occurs in this portion.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and a MOS transistor used in an input protection circuit at the time of abnormal input without using a field MOSFET.
An object of the present invention is to provide an input protection circuit capable of preventing the destruction of an internal element having a thin gate oxide film by opening a channel of an FET and reducing a trigger voltage of snapback thereof.

[0008]

According to a first aspect of the present invention, there is provided an input protection circuit, wherein a drain is connected to an input terminal for an internal element, and a source is connected to a negative side of a power supply together with a substrate. NMOSFET connected
And a first diode row connected in series between the input terminal and the negative side of the power supply in the forward direction.
A gate of the nMOSFET is connected to a connection point dividing the first diode row.

According to a second aspect of the present invention, there is provided an input protection circuit, wherein a drain is connected to an input terminal for an internal element, and a source is connected to a positive side of a power supply together with a substrate.
A second diode array connected in series between the positive side of the power supply and the input terminal in the forward direction, and the gate of the pMOSFET is connected to the second
Is connected to a connection point for dividing the diode row.

According to a third aspect of the present invention, there is provided an input protection circuit, wherein a drain is connected to an input terminal for an internal element, and a source is connected to a negative side of a power supply together with a substrate.
A first diode array connected in series between the input terminal and the negative side of the power supply in the forward direction, and the gate of the nMOSFET is connected to the first
A circuit connected to a connection point that divides the diode string of the above, and a drain connected to an input terminal for the internal element,
PMOS whose source is connected to the positive side of the power supply together with the substrate
A connection point between the positive side of the power supply and the input terminal, the second diode string being connected in series in the forward direction, and the gate of the pMOSFET dividing the second diode string. And a circuit connected to the circuit.

According to a fourth aspect of the present invention, there is provided the input protection circuit according to the first or third aspect, wherein a voltage drop of each diode constituting the first diode string with respect to an input voltage equal to or lower than a power supply voltage. However, the number of the diodes is set so as to be lower than the forward voltage of the diode.

According to a fifth aspect of the present invention, there is provided the input protection circuit according to the first or third aspect, wherein a voltage applied to a gate of the nMOSFET for an input voltage equal to or lower than a power supply voltage is a threshold of the nMOSFET. The number of diodes constituting the first diode row is set so as to be equal to or lower than the value voltage.

According to a sixth aspect of the present invention, there is provided the input protection circuit according to the second or third aspect, wherein a voltage drop of each of the diodes constituting the second diode row with respect to an input voltage equal to or lower than a power supply voltage. However, the number of the diodes is set so as to be lower than the forward voltage of the diode.

According to a seventh aspect of the present invention, there is provided the input protection circuit according to the second or third aspect, wherein a voltage applied to a gate of the pMOSFET for an input voltage equal to or lower than a power supply voltage is a threshold of the pMOSFET. It is characterized in that the number of diodes constituting the second diode row is set so as to be equal to or lower than the value voltage.

[0015]

According to the present invention, in a configuration using only an nMOSFET or a configuration using an nMOSFET and a pMOSFET, in a state where a positive side of a power supply is opened, when a negative overvoltage is applied to an input terminal, a drain-substrate of the nMOSFET is applied. Since the pn junction between them is forward-biased, current flows in the negative direction of the power supply to prevent the destruction of the internal elements, and when a positive overvoltage is applied to the input terminal, the nMOSFET is turned off. Since the parasitic bipolar operation is performed, a current flows to the negative side of the power supply and the destruction of the internal element is prevented. At this time, the voltage at the connection point dividing the first diode row is applied to the gate of the nMOSFET, and As a result, the channel of the nMOSFET opens, a current flows,
Since the snap-back trigger voltage is reduced, it is possible to prevent the destruction of the internal element having a thinner gate oxide film. Further, in the present invention, when the negative side of the power supply is opened in the configuration using only the pMOSFET or the configuration using the nMOSFET and the pMOSFET, when the positive overvoltage is applied to the input terminal, the drain-substrate between the pMOSFET and the substrate is formed. Because the pn junction is forward biased,
When a current flows in the positive direction of the power supply to prevent the destruction of the internal elements and, when a negative overvoltage is applied to the input terminal, the pMOSFET performs a parasitic bipolar operation, so that the current flows to the positive side of the power supply. And the internal element is prevented from being destroyed. At this time, the voltage of the connection point dividing the second diode row is applied to the gate of the pMOSFET, and as a result, the channel of the pMOSFET is opened and the current flows,
Since the snap-back trigger voltage is reduced, it is possible to prevent the destruction of the internal element having a thinner gate oxide film.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a circuit diagram showing a configuration of an input protection circuit according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of forming an input protection circuit of the present embodiment on a semiconductor substrate. FIG.

As shown in FIG. 1, the input protection circuit of this embodiment includes an nMOSFET 1 having a drain D connected to an input terminal Vin for an internal element to be protected and a source S connected to a ground GND together with a substrate B; A diode array 2 connected in series between the input terminal Vin and the ground GND in the forward direction,
The gate G of ET1 connects the diode row 2 to the input terminal Vi.
It has a configuration in which it is connected to a connection point N1 that is divided into n1 and n2 diodes 3 sequentially from the n side.

Next, an example of forming the input protection circuit of this embodiment on a semiconductor substrate will be described with reference to FIG. In a p-type semiconductor substrate 11, a p-well 13 and a plurality of n-wells 14 separated by a field oxide film 12 are formed. In the p-well 13, a source 16 and a drain 17 formed of an n-type high-concentration region are formed, and n-type is formed by a gate electrode 15 formed on the source 16 and the drain 17.
MOSFET 1 is formed. Further p-well 13
Inside, a contact region 19 for connecting to the ground GND is provided separately from the nMOSFET 1 and the field oxide film 12. On the other hand, a plurality of n-wells 14
In each of the p-type high concentration regions 20 of the diode,
And the n-well 14 separated by the field oxide film 12
And a plurality of diodes 3 are formed. A silicide layer 21 is formed on the surface of the gate electrode 15, the source 16, the drain 17 composed of an n-type high-concentration region, the contact regions 18 and 19, and the p-type high-concentration region 20 of each diode 3. The contact region 18 between adjacent diodes and the high-concentration region 20 are sequentially connected in series by wiring, the drain 17 of the nMOSFET 1 and the high-concentration region 20 at one end of the diode row are connected to the input terminal Vin, and the gate electrode is connected. 15 is connected to the connection point N1 of the diode row, and the source 16 of the nMOSFET 1 and the contact region 1
9 and the contact region 18 at the other end of the diode row are connected to the ground GND.

The operation of the input protection circuit of this embodiment will be described below with reference to FIGS. When a negative overvoltage is applied to the input terminal Vin, the pn junction between the drain D and the substrate B of the nMOSFET 1 is biased in the forward direction, so that a current flows in the direction of the ground GND and the internal element is prevented from being destroyed. Is done. On the other hand, when a positive overvoltage is applied to the input terminal Vin, the nMOSFET 1 performs a parasitic bipolar operation, so that a current flows to the ground GND and the internal elements are prevented from being destroyed. At this time, first, a connection point N1 where the overvoltage is distributed by n1 and n2 diodes 3
Is applied to the gate G of the nMOSFET 1. As a result, the channel of the nMOSFET 1 is opened, a current flows, and the trigger voltage of snapback is reduced as in the case of the conventional example shown in FIG. 6, so that the internal element having a thin gate oxide film is prevented from being destroyed. It becomes possible. In the input protection circuit of this example, the element that receives most of the voltage at the time of an abnormal input is a diode constituted by a pn junction, so that the protection element itself is destroyed unlike the conventional example shown in FIG. There is an advantage that there is no.

In this example, the number of connections n1 and n2 of the diode 3 is such that the forward voltage of the diode is Vf, nMO
The threshold voltage of SFET1 is Vth and the power supply voltage is Vdd
Vdd / (n1 + n2) <Vf (1) {n2 / (n1 + n2)} Vdd <Vth (2) Equation (1) is obtained during normal operation.
This is a condition for suppressing a leak current flowing through the diode 3. At the time of normal operation, a voltage of Vdd is applied to both ends of the (n1 + n2) series-connected diodes 3 at the maximum, so that the voltage Vd distributed to each diode is applied.
d / (n1 + n2) is the forward voltage Vf of each diode.
If it is lower than the above, the leakage current of the diode can be suppressed. Equation (2) indicates that during normal operation, nMOSF
This is a condition for suppressing a leak current flowing through ET1. During normal operation, the gate G of the nMOSFET 1
, A voltage of {n2 / (n1 + n2)} Vdd is applied at the maximum. If this value is smaller than the threshold voltage Vth of nMOSFET1, the source of nMOSFET1
The leakage current between the S and the drain D is suppressed.

As an example, the case where the power supply voltage Vdd is 1.8 V will be described. Now, when the forward voltage Vf of the diode 3 is 0.3 V and the threshold voltage Vth of the nMOSFET 1 is 0.3 V, (1) From the formula, (n1 + n2)
> 6 is derived, and n1 / n2> 5 is derived from equation (2). Therefore, for example, n1 = 6 and n2 = 1 may be set. In this case, the maximum voltage distributed to each diode during normal operation and the maximum voltage applied to the gate G of the nMOSFET 1 are both 0.26 V, so that the forward voltage Vf of the diode and the threshold voltage Vth of the nMOSFET 1, respectively. The value is smaller by about 0.04 V.
When the variation of the threshold voltage Vth of the nMOSFET 1 is 0.04 V or more, the ratio between n1 and n2 may be further increased.

Next, a method for forming the input protection circuit of this embodiment on a semiconductor substrate will be described with reference to FIG. First, an element isolation oxide film (field oxide film) 12 having a depth of 450 nm is formed in a p-type substrate 11, and then, using a photoresist as a mask, boron (B) is applied at 2 × 1 at 300 keV.
0 ¹³ cm ⁻² , 4 × 10 ¹² c at 200 keV
The p-well 13 is formed by continuously implanting 5 × 10 ¹² cm ⁻² at m ⁻² and 30 keV. Next, using a photoresist as a mask, phosphorus (P) is applied at 700 keV for 2 hours.
× 10 ¹³ cm ⁻² , 4 × 10 ¹² cm at 500 keV
^-2, and further, arsenic (As) was
5 × 10 ¹² cm ^{−2 is} implanted at keV, and n well 14 is injected.
To form Next, a gate electrode 15 of polycrystalline silicon having a thickness of 150 nm and a gate length of 0.18 nm is formed through a gate oxide film having a thickness of 3.5 nm. Next, arsenic is applied at 10 keV and 3 × 10
^After implanting ¹⁴ cm ⁻² to form n-type low concentration regions of source and drain (not shown), a gate sidewall (not shown) of an oxide film having a width of 100 nm is formed. Next, arsenic is applied at 3 × 10 ¹⁵ at 50 keV using a photoresist as a mask.
cm ⁻² implanted into a source 1 comprising an n-type high concentration region
6, the drain 17 is formed, the nMOSFET 1 is formed, and the contact region 18 of the n-well 14 is formed. Next, using a photoresist as a mask, boron difluoride (BF ₂ ) is applied at 30 keV to 3 × 10 ¹⁵ cm.
^-2 implantation to form a contact region 19 of the p-well 13 and a p-type high concentration region 20 to form a pn
A plurality of junction diodes 3 are formed. afterwards,
Gate electrode 15 and source 1 comprising n-type high concentration region
6, a 30 nm-thick cobalt (Co) silicide layer 21 on the surface of each of the drain 17 and each of the contact regions 18 and 19 and the p-type high concentration region 20 of the diode 3.
After forming an interlayer insulating film (not shown), necessary parts are connected by metal wiring.

As described above, according to the input protection circuit of this example, the nMOSFET used in the input protection circuit can be used without causing damage to the protection element itself at the time of abnormal input.
The trigger voltage of the snapback can be reduced, thereby preventing the destruction of the internal element having the thinner gate oxide film.

Second Embodiment FIG. 3 is a circuit diagram showing a configuration of an input protection circuit according to a second embodiment of the present invention, and FIG. 4 is an example of forming the input protection circuit of this embodiment on a semiconductor substrate. FIG. As shown in FIG. 3, the input protection circuit of this example has an nM in which the drain D is connected to the input terminal Vin for the internal element to be protected, and the source S is connected to the ground GND together with the substrate B.
An OSFET 1 and a diode row 2 connected in series between the input terminal Vin and the ground GND in the forward direction are sequentially provided. The gate G of the nMOSFET 1 is connected to the diode row 2 by n1 pieces sequentially from the input terminal Vin side. n2
A circuit connected to a connection point N1 that divides a diode 3 into a diode 3, a drain D is connected to an input terminal Vin for an internal element to be protected, and a source S is connected to a power supply Vdd together with a substrate B. type Met
al Oxide Semiconductor Field Effect Transistor) 4
And a diode array 5 connected in series between the power supply Vdd and the input terminal Vin in the forward direction.
The gate G of the MOSFET 4 is connected to the diode row 5 in order from the input terminal Vin side.
And a circuit connected to a connection point N2.

In the input protection circuit of this example, the nMOS
An example of forming the FET1 and the diode array 2 on the semiconductor substrate is the same as that of the first embodiment shown in FIG. Hereinafter, referring to FIG. 4, the pMOSFET 4 and the diode row 6 in the input protection circuit of this example will be described.
An example of formation on a semiconductor substrate will be described. In a p-type semiconductor substrate 31, an n-well 33 and a plurality of n-wells 34 separated by a field oxide film 32 are formed. n
In the well 33, a source 36 composed of a p-type high concentration region is provided.
And a drain 37 are formed, and a pMOSFE is formed by the gate electrode 35 formed thereon.
T4 is formed. Further, in the n-well 33, a contact region 39 for connecting to the ground GND is provided.
Separated by the pMOSFET 4 and the field oxide film 32,
Is provided. On the other hand, in the plurality of n-wells 34, a p-type high-concentration region 40 of the diode and a contact region 38 of the n-well 34 separated by the field oxide film 32 are provided. It is formed. A gate electrode 35, a source 36 comprising a p-type high concentration region, a drain 37, and contact regions 38, 3
9, a silicide layer 41 is formed on the surface of the p-type high-concentration region 40 of each diode 6, and the contact region 38 between adjacent diodes and the high-concentration region 40 are sequentially connected in series by metal wiring. Connect to pMO
The drain 37 of the SFET 4 and the contact region 38 at one end of the diode row are connected to the input terminal Vin, the gate electrode 35 is connected to the connection point N2 of the diode row, and the pMOS
The source 36 of the FET 4, the contact region 39, and the high concentration region 40 at the other end of the diode row are connected to the power supply Vdd.

In this example, the nMOSF
The operation for protecting the internal elements on the ET1 side is the same as that of the first embodiment. When a positive overvoltage (higher than the power supply Vdd) is applied to the input terminal Vin on the pMOSFET 4 side, the pn junction between the drain D and the substrate B of the pMOSFET 4 is biased in the forward direction, so that the current is reduced to the power supply Vdd. Flow in the direction to prevent the destruction of the internal element. On the other hand, when a negative overvoltage is applied to the input terminal Vin, the pMOSFET 4 performs a parasitic bipolar operation, so that a current flows to the power supply Vdd and the internal elements are prevented from being destroyed. In this case, first, the overvoltage is set to n3
The voltage at the connection point N2 divided by the n and n4 diodes 6 is applied to the gate G of the pMOSFET 4. As a result, p
Since the channel of the MOSFET 4 opens, a current flows, and the snap-back trigger voltage decreases, it is possible to prevent the destruction of the internal element having a thin gate oxide film.
In the input protection circuit of this example, even on the pMOSFET side, the element that receives most of the voltage at the time of abnormal input is pn
Since the diode is formed by the junction, the protection element itself is not destroyed.

In the circuits shown in FIGS. 3 and 4, the connection numbers n3 and n4 of the diodes 6 are set by replacing n1 with n3 and replacing n2 with n4 in the equations (1) and (2).
Can be performed in exactly the same manner as in the case of the first embodiment shown in FIG. For example, power supply voltage Vdd = 1.8 V, forward voltage V of diode 6
f = 0.3V, the threshold voltage of pMOSFET4 is-
In the case of 0.3 V, n3 = 6 and n2 = 1 may be set. p
When the variation in the threshold voltage of the MOSFET 4 is large, the ratio between n3 and n4 is further increased, similarly to the first embodiment.

Next, a method of forming the input protection circuit of this embodiment on a semiconductor substrate will be described with reference to FIGS. First, after device isolation oxide films (field oxide films) 12 and 32 having a depth of 450 nm are formed in the p-type substrates 11 and 31, boron (B) is deposited at 300 keV and 2 × 10 4 using a photoresist as a mask. ¹³ cm ^-2 , 20
4 × 10 ¹² cm ⁻² at 0 keV, 5 × 1 at 30 keV
The p-well 13 is formed by continuously implanting 0 ¹² cm ⁻² . Next, using a photoresist as a mask, phosphorus (P) is added at 2 × 10 ¹³ cm ⁻² , 50 at 700 keV.
4 × 10 ¹² cm ^{−2 is} implanted at 0 keV, and arsenic (As) is further implanted at 5 × 10 ¹² cm ⁻² at 100 keV to form n-wells 14, 33, and 34. Next, through a 3.5 nm-thick gate oxide film, a 150 nm-thick
Polycrystalline silicon gate electrode 1 having a gate length of 0.18 nm
5, 35 are formed. Then, using a photoresist as a mask, arsenic is implanted at 3 × 10 ¹⁴ cm ^{−2 at} 10 keV to form n-type low concentration regions of source and drain (not shown). After boron fluoride (BF ₂ ) is implanted at 3 × 10 ¹⁴ cm ^{−2 at} 10 keV to form p-type low concentration regions of source and drain (not shown), a gate sidewall (not shown) of an oxide film having a width of 100 nm is formed. ) Is formed. Then, using a photoresist as a mask, arsenic is implanted at 3 × 10 ¹⁵ cm ⁻² at 50 keV to form a source 16 and a drain 17 composed of an n-type high concentration region.
To form nMOSFET 1 and n
A contact region 18 of the well 14 and a contact region 38 of the n-well 34 are formed. Next, using a photoresist as a mask, boron difluoride (BF ₂ ) is deposited for 30 ke.
3 × 10 ¹⁵ cm ^{−2 is} implanted with V to form the contact region 19 of the p-well 13 and the p-type high-concentration regions 20 and 40 to form the diode 3 by the pn junction.
6 are formed, and a source 36 and a drain 37 made of a p-type high concentration region are formed.
The SFET 4 is formed. Thereafter, the gate electrode 15 and n
A cobalt (Co) silicide layer 21 having a thickness of 30 nm is formed on each surface of the source 16 and the drain 17 composed of the high-concentration type regions, the contact regions 18 and 19 and the p-type high concentration region 20 of the diode 3. The thickness of the gate electrode 35, the source 36 and the drain 37 made of a p-type high concentration region, the contact regions 38 and 39, and the surface of the p-type high concentration region 40
After forming a cobalt silicide layer 41 nm and an interlayer insulating film (not shown), necessary parts are connected by metal wiring.

As described above, according to the input protection circuit of this example, the nMOSFET used in the input protection circuit can be used without causing damage to the protection element itself at the time of abnormal input.
In addition, the trigger voltage of the snapback of the pMOSFET can be reduced, thereby preventing the destruction of the internal element having the thinner gate oxide film.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there may be design changes within the scope of the present invention. Even this is included in the present invention. For example, the present invention can be applied not only to the case where the input protection circuit has only the nMOSFET and the case where the input protection circuit has the nMOSFET and the pMOSFET, but also to the case where only the pMOSFET is provided.

[0031]

As described above, according to the input protection circuit of the present invention, the nMOSFE forming the input protection circuit is provided.
The diode array is used for the voltage dividing circuit at the gate input of the T and / or pMOSFET, so that the protection element itself is not destroyed at the time of abnormal input.
The snap-back trigger voltage of the nMOSFET and / or the pMOSFET used in the input protection circuit can be reduced, and therefore, it is possible to prevent the destruction of the internal device having the thinner gate oxide film.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an input protection circuit according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an example of forming the input protection circuit of the present embodiment on a semiconductor substrate.

FIG. 3 is a circuit diagram showing a configuration of an input protection circuit according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing an example of forming the input protection circuit of the present embodiment on a semiconductor substrate.

FIG. 5 is a diagram showing a configuration of a conventional general input protection circuit.

FIG. 6 is a diagram showing a configuration of a conventional improved input protection circuit.

FIG. 7 is a diagram showing a snapback operation of the MOSFET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 nMOSFET 2 diode string 3 diode 4 pMOSFET 5 diode string 6 diode

Claims (7)

[Claims] 1. An nMOSFET having a drain connected to an input terminal to an internal element and a source connected to a negative side of a power supply together with a substrate, and an nMOSFET connected in series in a forward direction between the input terminal and the negative side of the power supply. An input protection circuit, comprising: a first diode row; and a gate of the nMOSFET connected to a connection point dividing the first diode row. 2. A pMOSFET having a drain connected to an input terminal to an internal element and a source connected to the positive side of a power supply together with a substrate, and a pMOSFET connected in series in a forward direction between the positive side of the power supply and the input terminal. An input protection circuit, comprising: a second diode row; and a gate of the pMOSFET connected to a connection point dividing the second diode row. 3. An nMOSFET having a drain connected to an input terminal for the internal element and a source connected to the negative side of the power supply together with the substrate, and serially connected in series in a forward direction between the input terminal and the negative side of the power supply. A circuit in which a gate of the nMOSFET is connected to a connection point dividing the first diode row, a drain is connected to an input terminal for an internal element, and a source is a substrate. And pM connected to the positive side of the power supply
An OSFET, and a second diode row connected in series between the positive side of the power supply and the input terminal in the forward direction, and a gate of the pMOSFET is connected to a node for dividing the second diode row. And a circuit connected to the input protection circuit. 4. The number of the diodes so that a voltage drop of each diode constituting the first diode row is lower than a forward voltage of the diode with respect to an input voltage equal to or lower than a power supply voltage. The input protection circuit according to claim 1 or 3, wherein 5. An input voltage equal to or lower than a power supply voltage, the voltage applied to the gate of the nMOSFET is changed to the nMOSF.
4. The input protection circuit according to claim 1, wherein the number of diodes constituting the first diode row is set so as to be equal to or lower than a threshold voltage of ET. 6. The number of the diodes so that a voltage drop of each diode constituting the second diode row is lower than a forward voltage of the diode with respect to an input voltage equal to or lower than a power supply voltage. 4. The input protection circuit according to claim 2, wherein 7. An input voltage equal to or lower than a power supply voltage, the voltage applied to the gate of the pMOSFET is changed to the pMOSF.
4. The input protection circuit according to claim 2, wherein the number of diodes constituting the second diode row is set so as to be equal to or lower than a threshold voltage of ET.