JP2001075820A - Real time os device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an OS performing fast processing without imposing a burden on a processor by scheduling a task with hardware. SOLUTION: A bit matrix storing part 10 stores the priority of each task to be a scheduling object and information showing the order for every priority. A priority encoder 12 reads the priority of a task having the highest priority. A comparator 14 compares the priority of the read task with the priority of an active task and outputs an interrupt signal for task switching to a processor when the read priority is higher than the priority of the active task. A stack pointer address generation circuit 20 receives the task priority and the order of each different priority high in the order for every priority among applicable priority tasks and generates a stack pointer address used for task switching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a real-time OS device in which a portion for executing a task switching process is constituted by hardware.

[0002]

2. Description of the Related Art A widely used computer OS
(Operating system) is realized by software. However, in a system that executes communication protocol processing, for example, there is a demand that task switching must be completed in a short time, for example, 1 microsecond. In the field where such real-time property is strictly required, there is a limit to the correspondence of the OS realized by software. Therefore, a real-time OS device in which task switching processing is configured by hardware is being studied (hardware real-time OS and its evaluation, IEICE VLD93-97 (1993-12)). The evaluation, the religious technique VLD94-40 (1994-0
7)).

[0003]

However, the above-mentioned prior art has the following problems to be solved.
The realization of a real-time OS using software has been increasing with the performance enhancement of processors. However,
For example, when operations of a ready queue and a wait queue related to a task schedule are executed by software, an address operation of each task requires a large number of cycles. While the processor is performing this address manipulation, no other application programs can run, thus causing processor overhead. That is, when the task is frequently switched, the operation speed of another application is significantly reduced.

When a large number of interrupt signals are asserted, software processing is started via processing by an interrupt handler. However, the overhead of processing by an interrupt handler poses a problem for software that needs to process an interrupt immediately. In addition, if it takes a large number of cycles from the setting of the event flag to the state where the task can be executed, the overhead of the event flag processing is required for software that needs to process the event flag immediately. It becomes a problem.

When a cyclic handler is specified,
The CPU stops other processing and searches for a queue or decrements a timer. In this case, the load on the processor becomes a problem.
Further, a configuration in which a plurality of processors are mounted and an OS and an application are shared and processed is also conceivable. However, since many cycles are required for processing a system call for calling one CPU from another CPU, it is not easy to efficiently execute the real-time OS. On the other hand, the hardware-based OS introduced above has not yet solved these specific problems.

[0006]

The present invention employs the following structure to solve the above problems. <Structure 1> a storage circuit storing information indicating the priority of each task to be scheduled and the order of priority,
A circuit for reading out the priority of the task having the highest priority from the priorities and priorities of the tasks stored in the storage circuit, a priority of the read task, and a priority of the task being executed. And an interrupt signal output circuit including a circuit that outputs an interrupt signal for task switching to the processor when the read priority is higher than the priority of the task being executed. The priority of the read task and the priority of the higher priority task among the tasks of the corresponding priority stored in the storage circuit are accepted, and the stack pointer address used for task switching is set. A real-time OS device comprising: a stack pointer address generation circuit for generating the stack pointer address.

<Configuration 2> Real-time O described in Configuration 1
In the S device, the circuit for generating a stack pointer address receives the current priority of the task being executed from the circuit for outputting an interrupt signal, generates and outputs a stack pointer address for saving the task being executed, When a save completion signal is input from the processor, a signal synthesizing circuit that accepts the next priority of the task newly read from the storage circuit and generates and outputs a stack pointer address of the newly executed task is provided. A real-time OS device characterized by the above-mentioned.

<Configuration 3> Real-time O described in Configuration 1
In the S device, the priorities of the tasks saved immediately before or the tasks that have transited to the waiting state are retained by priority, and read from the storage circuit storing the priority of each task and information indicating the priority order. A real-time OS device comprising a queue control circuit for masking a part of the priority line bit and selecting a task at the head of the queue with the same priority as a task to be executed next.

<Configuration 4> Real-time O described in Configuration 1
A real-time OS device in the S device, wherein an interrupt signal is stored in a storage circuit that stores information indicating the priority of each task and the priority order.

<Structure 5> Real-time O described in Structure 1
A real-time OS device in the S device, wherein an interrupt signal and an enable bit indicating the validity of the interrupt signal are stored in a storage circuit storing information indicating the priority of each task and the priority order.

<Configuration 6> Real-time O described in Configuration 1
In the S device, when there is a task in the event flag waiting state, a memory storing event flag information including a current flag pattern and a waiting flag pattern for each task is compared with the current flag pattern and the waiting flag pattern. And a memory circuit storing information indicating the priority of each task and the priority order so that the task in the waiting state is shifted to the executable state when the current flag pattern and the waiting flag pattern match. A real-time OS device comprising a circuit for outputting data for rewriting the contents and a write address.

<Configuration 7> Real-time O described in Configuration 1
In the S device, if a cyclically activated handler exists,
A memory for storing cyclically activated handler information including a remaining time and a cycle time for each handler, a circuit for comparing the current remaining time with the cycle time, and a circuit for determining whether a current flag pattern and a wait flag pattern match. A circuit for rewriting the contents of a storage circuit storing information indicating the priority of each task and the order of priority, and a circuit for outputting a write address, so as to shift the cyclically activated handler to an executable state. Real-time OS device.

<Structure 8> Real-time O described in Structure 1
In the S device, the storage circuit storing information indicating the priority of each task and the order of priority includes information for distinguishing a stopped state, an executable state, a waiting state, and an execution state of each task. Real-time OS device.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. <Example 1> FIG. 1 is a block diagram showing a real-time OS device of Example 1 according to the present invention. This device realizes high-speed execution of task switching processing, which is the main processing of the real-time OS, using hardware. Before describing the specific configuration and operation of this device, a ready queue and a wait queue for task management will be described first.

FIG. 2 is an explanatory diagram of a configuration example of a general ready queue. The bit table 1 has the number of priorities provided in advance, here 31 bits, and at least one task control block (TC
When B) is connected, "1" is added. If one task control block (TCB) is not connected, "0" is set. The bit with the highest priority is at the top of the figure. Here, “1” is set in the bit table 1 of the bit having the second priority. Here, several task control blocks TCB are connected. The TCB is a block for specifying a task and controlling each task, and is a block for holding various information related to the task such as a stacker address and a task state. O
S refers to the TCB in this way, and selects the task with the highest priority among the tasks requesting processing as the task to be executed next.

The task queue table 1A is a table for sequentially storing each task in a queue when there are a plurality of tasks having the same priority. The task queue table 1A holds addresses representing the first TCB and the last TCB. Tasks connected like a chain in this way are called task chains. All TCBs connected to the ready queue are in an executable state. Tasks are executed in order from the TCB having the highest priority and closest to the task queue table 1A.

FIG. 3 is an explanatory diagram of a configuration example of a general wait queue. The wait queue is a queue connected to the TCB in an event occurrence waiting state. The wait queue pointer 3 holds an address indicating the first TCB and the last TCB for waiting for an event. This TCB
Is similar to the TCB shown in FIG. Each TCB
Is moved from the ready queue to the wait queue when the system enters the event waiting state. When the state changes from the event wait state to the executable state, the wait queue is connected to the end of the chain of the corresponding priority of the ready queue.

Normally, the TCBs shown in FIG. 2 are executed in the order of priority and in the order of proximity to the task queue table 1A. Here, when a certain TCB in the wait queue enters an executable state, it is connected to the end of the corresponding portion of any chain of the ready queue according to its priority. As described above, the tasks are arranged based on the addresses shown in the task queue table 1A of the ready queue, and the processor switches tasks while referring to this order. In the present invention, such task switching is realized by hardware, and the overhead for task switching processing to the processor is reduced.

FIG. 4 is a block diagram of the real-time OS device of the first embodiment. The figure includes an RTOS coprocessor 5 controlled by a CPU 4, a main memory 6, a work memory 7, and a decoder 8. In the main memory 6,
It mainly stores application software programs and data executed by the CPU. The RTOS coprocessor 5 is a hardware coprocessor for realizing a real-time OS device. The sequencer control of the RTOS coprocessor 5 is realized by hard wired. This figure shows main control lines for the control. The contents will be described later with reference to FIG.

The work memory 7 is a work memory used when the RTOS coprocessor 5 operates. Here, a stack pointer register accessed by a stack pointer address generated by the RTOS coprocessor 5 is stored. The contents will be described later. Decoder 8
Is a circuit that decodes an address MA output from the CPU 4 and generates a chip select signal MMCS or HRCS of the main memory 6 or the RTOS coprocessor 5.

For data exchange between the CPU 4, the RTOS coprocessor 5, and the main memory 6, a data bus MD and an address bus MA are used. The exchange of data between the RTOS coprocessor 5 and the work memory 7 is performed using the address bus WA, the data bus WD, and the chip select signal WMCS.

FIG. 1 is a block diagram of a main part of a real-time OS device according to the first embodiment. The device shown in the figure is a bit matrix storage unit 10 for storing data of 8 × 8 bits, an address register (ADR) 11, a priority encoder (PE) 12, a multiplexer (MUX) 18, a priority register (PRIR) 13, Unit 14, decoder 1
5, a flip-flop 16 and an OR gate 17.

The bit matrix storage unit 10 stores information arranged just like a ready queue as shown in FIG. The vertical direction is the priority, and in this example, 0
8 to 7 are set. A queue arrangement is provided in the horizontal direction for each priority. Bits on the left with the same priority have higher rank. Information for scheduling each task is arranged in one matrix in one bit. When this bit is “0”, it indicates an event waiting state or a pause state, and “1”
Indicates an executable state.

In the present invention, the description of the hardware is simplified by expressing the wait state and the sleep state with the same bit "0". If the two are to be distinguished, the status bits may be set to 2 bits. In this case, "0
A state of “0” indicates a suspended state, a state of “00” is a waiting state, and a state of “10” is an executable state. Will be executed.

The address register 11 is for temporarily storing an address for reading or writing each bit of the bit matrix storage unit 10. The address of the bit matrix storage unit 10 is composed of 6 bits, with the upper 3 bits indicating the priority and the lower 3 bits indicating the order of the same priority. Hereinafter, this is called a priority order. The priority encoder 12 performs an OR operation on the bits that are in an executable state at each priority,
This is a circuit that receives and encodes the logical OR of the eight types of priorities. That is, it is a circuit for detecting the highest priority task in the executable state in the bit matrix storage unit 10 and obtaining information on the priority.

The output of the priority encoder 12 is 4
Bits, the upper 1 bit is priority encoder 1
2 is a bit indicating whether the output is valid or invalid. Priority 7
If the bit is set in the row of, the output is “111”.
The output becomes "1000" if a bit is set in a row of priority 0. If no "1" bit is set in any of the priority bit strings, the output is invalid. , "0000".

The priority register 13 is a register for temporarily holding the output of the priority encoder 12. The contents of this register are updated when the context saving of the task executed immediately before by the CPU 1 is completed. That is, prior to the input of the save completion signal TC, the priority of the task being executed is held, and when the save completion signal TC is input,
It operates to keep the priority of the task to be executed next.
Note that the context is various data necessary for the task to restart.

The comparator 14 compares the output of the priority encoder 12 with the output of the priority register 13,
When the output of the priority encoder 12 is large, it has a function of outputting “1”. This is because when a task having a higher priority than the priority of the currently executing task stored in the priority register 13 becomes ready for execution and is written to the bit matrix storage unit 10, an interrupt for switching the task is executed. It is for generating a signal.

The decoder 15 is a circuit that decodes task information that is cleared from the bit matrix storage unit 10 after processing is completed, and generates a self-clear signal SCL. This decoder 15 is used when the address ADRN of the task being processed and the address set in the address register 11 are the same, and the bit matrix storage 1
When a write request HRCS for writing “0” to a corresponding part of “0” is input, the self-clear signal SCL is asserted. As a result, an interrupt signal for saving the task being executed is generated.

The flip-flop 16 is a flip-flop that temporarily holds the self-clear signal in order to take timing when an interrupt signal is generated from the self-clear signal SCL. The OR gate 17 calculates the logical sum of the output of the flip-flop 16 and the output of the comparator 14, and
This is a circuit that outputs an interrupt signal INT. This interrupt signal INT is used for an interrupt for requesting the CPU 1 to switch tasks.

The multiplexer 18 receives information corresponding to the priority output from the priority encoder 12, and from the bit matrix storage unit 10, eight bits for one column of the corresponding priority (herein referred to as priority line bits). ) Has a function to take out. This priority line bit LB, the next priority NY output from the priority encoder 12, and the current priority LY output from the priority register 13
Are supplied to the stack pointer address generation circuit 20 shown in the figure, where the stack pointer address SPA of each task required for task switching is generated.

FIG. 5 is a block diagram of the stack pointer address generation circuit. This circuit uses inverter 2
1, AND gates 22, 23, priority encoders 24, 25, multiplexer 28, OR gate 27,
It includes a priority order register 30, a multiplexer 31, a decoder 32, a subtractor 33, a multiplexer 34, an OR gate 35, an order register 36, a stack pointer table register 37, and an adder 38.

The priority order register 30 is a register capable of storing eight types of 3-bit data corresponding to the respective priorities. In this register, when a task of a certain priority with a certain priority is saved or switched from the executable state to the event waiting state, data of three bits corresponding to the priority is held. Has functions. As described with reference to FIGS. 2 and 3, when there are a plurality of tasks having the same priority, a queue is formed. When a queue is formed, processing is started in order from the task arranged at the head of the queue. When a task enters the event waiting state, the task arranged next to the task comes to the head of the queue.

However, the bit matrix storage unit 1
The eight bits at the same priority location of 0 are arranged so as to correspond to the predetermined tasks. For example, if the leftmost task among them is always regarded as the head of the queue, the task closest to the right end May not be at the head of the queue. To implement the above queue by hardware, for example, the task at the left end is set to the head of the queue first, and when the task changes to the event waiting state, the task at the second from the left is set to the head of the queue. Control is required. Moreover, this queue needs to be controlled separately for each priority.

Therefore, the multiplexer 28 outputs the priority order of the tasks in the event waiting state, and the subtractor 33 has a function to shift the queue one place to the right when the task enters the event waiting state. . When the task is saved, the queue remains unchanged, so that the subtracter 33 does not function. The position of the next queue can be determined by looking at the order of priority after such processing. The priority order register is a register for storing the priority order for specifying the position of the queue for all the priorities.

The decoder 32 designates the position of the queue and generates mask information for extracting the priority order corresponding to the task at the head of the queue from the priority line bits read from the bit matrix storage unit. . The AND gates 22 and 23 have a function of masking a part of the priority line bit with the mask information.

More specifically, any one of the priorities in the priority register 30 is assigned to the multiplexer 31.
And converted by the decoder 32 into mask information. This mask information is input to AND gates 22 and 23. The AND gate 22 is a circuit that receives the inverted mask information by the inverter 21 and the priority line bit LB output from the multiplexer 18 shown in FIG.

The AND gate 23 stores the mask information and FIG.
Is a circuit which receives the priority line bit LB output from the multiplexer 18 shown in FIG. The priority encoder 24 is an AND gate 2
2 is a circuit that encodes the output of No. 2 and obtains the highest-order bit in the portion of the priority line bit LB not masked by the AND gate 22. The priority encoder 25 encodes the output of the AND gate 23 and outputs the AND gate 2 of the priority line bits LB.
3 is a circuit for finding the highest-order bit in the portion not masked by 3.

The multiplexer 28 includes the AND gate 23
This is a circuit controlled by the output of the OR gate 27 that takes the logical sum of the outputs of the priority encoders 24 and 25, and selects and outputs one of the outputs of the priority encoders 24 and 25. If even one bit contains “1” in the output of the AND gate 23, “1” is output from the OR gate 27,
The multiplexer 28 selects and outputs the output of the priority encoder 25. That is, the output of the priority encoder 25 is always selected with priority. The output of the multiplexer 28 is input to the multiplexer 34. The multiplexer 28
Is input to another terminal of the multiplexer 34 via the subtractor 33.

As described above, the priority order register 30 holds the priority order when the task being executed is saved or switched to the event waiting state. The order of priority is held in a storage area that is differentiated by priority. For example, when the priority of the task is “6”, the priority order is held in the portion of L6. The OR gate 35 sends the priority order register 30
A signal for holding timing is output. OR gate 3
5 includes a self-clear signal S output at the end of the task.
CL and a save completion signal TC output when saving of the task executed immediately before is completed. The OR gate 35 outputs a control signal so that the output of the multiplexer 34 is held in the priority order register at the timing when the task is completed and when the task is completely saved.

The output of the priority order register 30 is input to the multiplexer 31. The output of the multiplexer 31 is input to the decoder 32. The multiplexer 31
A signal NY corresponding to the priority of the task to be executed next is
It has a function of taking out data corresponding to the priority order from the storage area of the corresponding priority in the priority order register 30 which is received from the interrupt signal generation circuit shown in FIG.

The decoder 32 converts the data output from the multiplexer 31 corresponding to the 3-bit priority order into 8 bits.
It is converted into bit mask information M. For example, when the extracted priority order is 100, that is, No. 4, four pieces of mask information "1" are arranged from the right, and the others are set to 0. That is,
It becomes “000011111”. Thus, when the eight priority line bits are masked, only the right four bits are output from the AND gate 23. The task indicating “1” on the leftmost side is the first task in the next queue. That is, a process of setting the fourth or lower task from the right to the head of the queue is realized by the mask information.

Here, if "1" is not included in the right four bits, the output of the AND gate 23 includes:
No information indicating the next task is included. At that time, the task indicating “1” on the leftmost side of the signal output from the AND gate 23 is at the head of the queue. This switching is performed by the OR gate 27.

The multiplexer 34 selects the output of the subtracter 33 when receiving the self-clear signal. In other cases, a signal directly input from the multiplexer 28 is selected. For example, a task that has set its own task to a suspended state (such as an event waiting state) sets the corresponding bit in the bit matrix storage unit 10 to “0”. Then, at this time, the self-clear signal SCL becomes valid and is input to the multiplexer 34. As a result, the multiplexer 34 outputs a value obtained by decrementing the priority order by one. This is stored in the priority order register 30. Therefore, the task in the event waiting state is moved to the end of the queue by the mask information.

On the other hand, the order register 36 provided on the lower right side of the figure is a register for holding the order of priority output from the multiplexer 28. Evacuation completion signal T
When C is asserted, the order register 36 stores the priority order output from the multiplexer 28 at that time. Stack pointer table register 37
Is a register for storing a pointer pointing to the top of the stack pointer table provided in the work memory 7 of FIG.

FIG. 6 is a view illustrative of the configuration of the stack pointer table. In the illustrated work memory 2, a stack pointer of each task to be managed is stored. The stack pointer indicates a storage location of various information (context) for restarting the task. The storage areas of the stack pointer are distinguished in order of priority, and eight storage areas are provided for the same priority. These storage areas correspond to information of all tasks stored in the bit matrix storage unit 10. The address of each storage area in the work memory 2 is obtained by adding a value obtained by combining the priority and the priority order to the address stored in the stack pointer table register 37.

The adder 38 shown in FIG. 5 receives a value obtained by combining the current priority LY output from the circuit shown in FIG. 1 with the priority order stored in the order register 36, and outputs the stack pointer table register 37 Has the function of adding the address stored in the memory. Thus, a stack pointer address is generated. A predetermined program start address is already set in the stack pointer table at an initial stage, and the initially set program is executed even when context recovery processing from the stack is executed for the first time.

That is, when the task is put into the sleep state, the stack pointer address for storing the program start address of the task is sequentially generated by the order register 36, the stack pointer table register 37, and the adder 38. .

<Operation> The specific operation of the above circuit will be described below. FIG. 7 is an explanatory diagram of a task initial value allocation status. (A) of the figure is the address of each task. It is assumed that there are three types of tasks, task0, task1, and task2. The address in the bit matrix storage unit 10 is represented by a 6-bit numerical value shown in FIG. The first, b, is a symbol indicating that these addresses are in binary representation. Further, an underscore provided in the middle of the 6-bit numerical value of “0” or “1” is a display in which the priority and the priority order can be distinguished, and has no practical meaning.

(B) shows the contents of the bit matrix storage. For example, task0 has a priority of “6” from the upper three bits. Also, from the lower 3 bits,
The priority order is “5”. Therefore, "1" stands at the position corresponding to the seventh from the bottom and the sixth from the right from the bit matrix storage unit. The same is true for other tasks,
Bits of “1” are set at three places in total. Here, three system calls are defined to facilitate the description of the operation.

The first system call is slp-tsk
(Task-id). This system call changes its task from the execution state to the waiting state. This operation is performed by task-i on the bit matrix.
The bit corresponding to d is cleared to “0”. The status bits on the bit matrix are both "executable" and "executable", and are not distinguished.

The next system call is sus-tsk
(Task-id). This system call changes a task from an executable state to a wait state. This operation is performed by task-id on the bit matrix.
Is cleared to "0".

The next system call is rsm-tsk
(Task-id). This system call changes another task from the waiting state to the executable state. This operation is performed by task-
The bit corresponding to id is set to “1”.

In each system call, the corresponding task ID (task) is stored in the address register 11 shown in FIG.
−id), and writes “1” in the execution state or the executable state, and writes “0” in the waiting state.

FIG. 8 is a diagram for explaining the contents of each task and the execution order of the tasks. (A) to (c) of FIG.
The content of task2 is shown. Each of these shows only the part of the system call, and the other parts are not shown. The portion sandwiched between / * and * / indicates the corresponding processing step. This processing step is a hardware state change in the circuits shown in FIGS. 1 and 2, and is not a program processing step.

FIG. 6D shows the task execution order. Here, for example, the tasks are task0, ta
sk1, task2, task0, task2, and task1 are executed in this order. Hereinafter, FIG. 1 and FIG.
The operation of the circuit shown in FIG.

[Step S1] First, the priority encoder 12 receives data for each priority from the bit matrix storage unit 10 in which the data as shown in FIG. 7 is stored, and performs a logical sum. The input of the priority encoder 12 is “01001000”, and the highest priority is the sixth bit from the right (the first bit is 0), so the encoder output is “1110”.
The most significant bit “1” indicates that the output of the priority encoder 12 is valid. The three right bits represent the sixth.

The priority register 13 has an initial value “000”.
The comparator 14 sets the output to "1" because the output of the priority encoder 12 is larger than the value stored in the priority register 13. The OR gate 17 accepts this and outputs "1". Assert an interrupt signal to the CPU 4.

[Step S 2] Data corresponding to the priority output from the priority encoder 12 is input to the multiplexer 18. Therefore, multiplexer 1
No. 8 selects and outputs the sixth priority line bit LB. The content is shown in the sixth row 1 in FIG.
As shown in the column, it becomes "00100000". FIG.
Receives the priority NY output from the priority encoder 12 and stores the data of the priority order corresponding thereto into the priority order register 30.
And output it. Its initial value is set to "111". Therefore, the decoder 32 outputs “11111
111 ”is output.

Since the output of the decoder 32 is all 1s, the AND gate 23 performs a logical AND operation with the priority line bit output from the multiplexer 18 and outputs the value of the priority line bit LB as it is to the priority encoder 25.
Output to On the other hand, since the inverter 21 inverts the output of the decoder 32, the signal of all 0 and the priority line bit LB are input to the AND gate 22. Therefore,
The output of the AND gate 22 is all 0s.

The priority encoder 25 indicates the position of the most significant bit of the 8-bit signal output from the AND gate 23 in which the "1" is set by a 3-bit signal. Therefore, when an input having a fifth “1” is received, the output is set to “101”. this is,
That is, the priority order is a value represented by a 3-bit binary signal.

On the other hand, the priority encoder 24 performs the same operation, but since the value of all 0 is input to the priority encoder 24, the output of the priority encoder 24 is all 0.

The OR gate 27 controls the multiplexer 28 to select the output of the priority encoder 25 when at least one "1" is included in the output of the AND gate 23. Therefore, the output of the priority encoder 25 is selected by the multiplexer 28 and output to the multiplexer 34. In this way, this circuit is a task of the priority output from the priority encoder 12 shown in FIG. 1, and outputs the value indicating the highest priority order as a 3-bit binary signal. Operate.

[Step S3] When the interrupt signal INT output from the OR gate 17 shown in FIG. 1 is asserted, the CPU 4 shown in FIG. 3 switches contexts. At this time, the CPU 4 executes the initialization routine when starting up a new task, and saves the stack read address for resuming the task that has been executed so far to the stack pointer table shown in FIG. .
This stack is an area for storing a context. In this example, since the CPU 4 is still executing the initialization routine, the context of the initialization routine is saved on the stack.

“000” was stored in the priority register 13. The initial value “0” is also stored in the order register 36.
00 ”. These are combined with“ 0 ”.
The value “00000” and the address of the stack pointer table stored in the stack pointer table register 37 are stored in the adder 38. Thus, the value of the stack pointer table shown in FIG. A stack pointer for restarting the initialization routine is stored at the address indicating the top.

When such processing is executed by the CPU 4, the CPU 4 outputs a save completion signal TC.
When the save completion signal TC is asserted, the priority register 13 stores the priority “110” of the next task output from the priority encoder 12. The order register 36 stores “101”, which is the priority order of the next task output from the multiplexer 28.

On the other hand, the multiplexer 34 operates so as to normally select and output the priority order output from the multiplexer 28 as it is. When the save completion signal TC is asserted, writing into the priority order register 30 through the OR gate 35 becomes possible. The writing position is specified by the current priority NY.
Therefore, "1" is added to the L6 portion of the priority order order register 30.
01 ”is stored.

At the same time, when the save completion signal TC is asserted, a signal obtained by combining the output of the priority register 13 and the output of the order register 36 is input to the adder 38. The adder 38 adds these values to the output of the stack pointer table register 37 to generate a stack pointer address SPA. This makes it possible to read out the corresponding data in the stack pointer table storing the start address of the program of the task task0 to be operated.

[Step S4] Using the stack pointer address SPA, the CPU 4 extracts the stack pointer from the corresponding address in the stack pointer table shown in FIG. 6, and starts the operation of the task task0. The task task0 executes the system call slp-tsk (task0-id) during execution, thereby clearing the bit indicating its own task stored in the bit matrix storage unit 10 from task0-id to 0. That is, a process of shifting the task from the operation state to the sleep state is thereby performed.

The decoder 15 shown in FIG. 1 receives and decodes the address of this task and data for setting the bit of the corresponding portion of the bit matrix storage unit 10 to “0”, and asserts the self-clear signal SCL. The most significant bit of the priority register 13 is switched to "0" at this timing. The multiplexer 34 shown in FIG. 5 receives the self-clear signal SCL, and the multiplexer 34 selects and outputs the output of the subtracter 33.

The OR gate 35 is connected to the self-clear signal SC
When L is asserted, the priority order register 30 can be written. Therefore, the signal output from the multiplexer 34 is stored in the priority of the corresponding task, that is, the portion of L6. The content is “100” obtained by subtracting “1” from “101”. This is processing for moving this task to the end of the queue.

[Step S 5] In the bit matrix storage unit 10, a signal “00001000” is output to the priority encoder 12 because the bit corresponding to the task task 0 is set to “0”. Thereby, the priority encoder 12
A signal “1011” indicating that the highest priority of the task in the execution waiting state is “3” is output. When this is input to the comparator 14, the comparator 14 compares the value with the value “0110” stored in the priority register 13. Since the contents of the priority register 13 have already been invalidated and the output of the priority encoder 12 is larger than the output of the priority register 13, the comparator 14 outputs "1". This is input to the OR gate 17, and the interrupt signal INT is asserted again.

[Step S 6] A signal “011” is input from the priority encoder 12 to the multiplexer 18, and the multiplexer 18 extracts and outputs the priority line bit LB of the corresponding priority from the bit matrix storage unit 10. . The signal output from the priority encoder 12 and corresponding to the next priority NY is:
The signal is input to the multiplexer 31 shown in FIG. As a result, the data “111”, which is the initial value, is read from the portion corresponding to L3 of the priority order register 30 and is input to the decoder 32 through the multiplexer 31.

As described above, the decoder 32 outputs an all-one signal as mask information in the initial state.
As a result, the priority line bit LB output from the AND gate 23 to the multiplexer 18 is output directly to the priority encoder 25. The AND gate 22 blocks all input signals, and a value of all 0 is input to the priority encoder 24. The OR gate 27 controls the multiplexer 28 to output the output of the priority encoder 25. As a result, the multiplexer 28 outputs an order of priority "111".

[Step S7] CPU 4 shown in FIG.
Performs context switching as in the case of task0. That is, the CPU 4 saves the stack pointer address for resuming the task 0 to the corresponding address in the stack pointer table shown in FIG. After that evacuation,
When the save completion signal TC is output, the adder 38 calculates the stack pointer address of the next task based on the new priority and the priority order. That is, a signal indicating the priority “1011” is stored in the priority register 13, and a signal “110” is stored in the priority register 36.

FIG. 9 is a timing chart of the system call task0. The above-described steps 1 to S8 are executed at such timing. (A) is a system clock. At time t0 of the system clock, the address MA and the data MD of the circuit shown in FIG. 1 become valid. This address is a signal output from the address register ADR11.
At the next timing t1, the write request HRCS becomes valid, and this signal and data of "0" are accepted, and the decoder 15 makes the self-clear signal SCL valid for one clock.

Here, the flip-flop 16 receives the self-clear signal, and outputs the content of the self-clear signal to the OR gate 17 at the next clock, that is, at the timing of t2. Therefore, the interrupt signal int is asserted at the timing of t2. When the interrupt signal int is asserted, the processor 4 clears the most significant bit, that is, the valid bit of the priority register 13 from “1” to “0”. Then, the priority order register 30 stores this t2
At the timing of, the priority order of the task stored immediately before is rewritten to the priority order of the new task.

Thus, after the timing t2, the CPU 4
Executes the process of saving the context of the task that was valid until immediately before with reference to the stack pointer address output from the adder 38 shown in FIG. When the save processing is completed, the save completion signal is made valid for one clock at the timing of tn.

Thus, the priority register 13 stores data corresponding to the priority of a new task. The adder 38 outputs a stack pointer address for a new task. Further, the priority order register 30 stores a priority order of a new task. Thus, a new task is executed after the timing tn + 1. As described above, all task switching is realized using hardware.

[Step S8] Next, the task task1
The operation after switching to is described. First, CPU4
Extracts the context from the work memory using the stack pointer address of the new task output from the adder 38. Then, the operation of the new task task1 is started. During the execution of this task task1, the system call slp-tsk (task1-id) is executed. In task1-id, the bit corresponding to task task1 in the bit matrix storage unit 10 is cleared to "0".

The decoder 15 asserts the self-clear signal SCL at this timing. Multiplexer 2
Numeral 8 outputs the priority order of this task, which is decremented by “1” by the subtracter 33 and stored in the priority order register 30 through the multiplexer 34. This storage location is L3. The stored data is “101”.

[Step S9] The task task of the bit matrix storage unit 10 is executed by the above-described system call.
The bit corresponding to 1 is cleared to "0". The priority of task 2 which is the next task is “3” which is the same as task 1
It is. Therefore, the priority encoder 12 outputs the same signal as “1101” as before. The multiplexer 18 outputs a bit string “0” corresponding to the priority.
0001000 "and the priority line bit LB
And

[Step S 10] At the same time, the signal stored in the priority “011” portion of the priority order register 30 is output through the multiplexer 31. In the portion corresponding to L3 of the priority order register 30, data "101" is stored by the immediately preceding task. When this is extracted, the decoder 32 outputs the mask information “00111111”. AND Gate 2
3, the mask information is input from the decoder 32, and the priority line bit LB having the content “00001000” is input from the multiplexer 18.

The leftmost of the six bits from the right,
Since the bit of “1” has the fourth priority order,
The signal “011” is transmitted to the priority encoder 25
Output from Since the output of the OR gate 27 is “1”, the multiplexer 28 outputs a signal corresponding to the priority order.

[Step S11] Here, the stack is saved by the CPU 4, and the save completion signal TC is asserted. When the save completion signal TC is asserted,
The order “011” is stored in the order register 36.
At the same time, the order “011” is stored in the L3 portion of the priority order register 30. The adder 38 outputs the output of the stack pointer table register 37 and the order register 36
Is added to the output of the priority register 13 to generate and output a stack pointer address.

[Step S12] The CPU 4 uses the stack pointer address SPA to store the work memory 2
To access the stack pointer table. In this way, the stack pointer address of the task task2 is extracted from the work memory, and this task is executed.
In FIG. 8C, the task task2 is a system call rsm-tsk (task1-i) during execution.
d) is executed, and the corresponding bit of the bit matrix storage unit 10 is set to "1" from task1-id.

However, even if the corresponding bit in the bit matrix storage unit 10 is set to "1", the output of the priority encoder 12 does not change. As a result, the output of the comparator 14 does not change, so that the interrupt signal INT is not asserted. Therefore, the task 2 executes the system call (rsm-tsk), and then continues the processing.

[Step S13] The task task2 is
During execution, the system call rsm-tsk (task0
Perform id). As a result, a process of setting the corresponding bit of the bit matrix storage unit 10 from “task0-id” to “1” is performed. As a result, the output of the priority encoder 12 becomes “1110”.
This is according to the address of each task shown in FIG. The comparator 14 holds “1011” which is the priority of the task task2. Therefore, the comparator 14 outputs “1” assuming that the signal output from the priority encoder 12 is large. Thus, the interrupt signal INT is output from the OR gate 17 and asserted.

[Step S14] Multiplexer 18
Extracts the corresponding priority line bit LB from the bit matrix storage unit 10 in accordance with the output of the priority encoder 12. This content is “00100000”
Becomes The multiplexer 31 extracts the priority order “100” stored so far from the portion of the priority order register 30 where the priority is L6 and supplies it to the decoder 32. Since this content is 4, the decoder 32
The mask information “00011111” in which the +1 bit becomes 1 is generated.

The AND gate 23 takes the logical product of the priority line bit LB and the output of the decoder 32. As a result, the output of the priority encoder 25 becomes "101".
Becomes The signal of the decoder 32 is supplied to the AND gate 23.
, The upper three bits of the priority line bit LB are masked. Therefore, the output of the AND gate 23 is all 0
Becomes As a result, the OR gate 27 sets the output to “0”, and the multiplexer 28 operates to select the output of the priority encoder 24.

The AND gate 22 receives the inverted signal of the mask information and the priority line bit LB. As a result, from the AND gate 22, the upper three bits of the priority line bit LB become valid data, ie, "00".
100000 "is obtained. This is encoded by the priority encoder 24. Since the bit position is at the fifth position, the priority encoder 24 outputs" 101 ". As a result, the output of the multiplexer 28 becomes" 101 ". Become.

[Step S15] Similar to step S3, the saving process is performed. When the saving completion signal is asserted, "110" is stored in the priority register 13. The order register 36 includes the multiplexer 28
The signal of “101” output from is stored. This signal is stored in the corresponding portion of the priority order register 30, that is, the portion of L 6 through the multiplexer 34 in the same manner as before. The adder 38 adds the output of the priority register 13 and the output of the order register 36 to the output of the stack pointer table register 37, and outputs a stack pointer address.

[Step S16] Using the stack pointer address SPA, the CPU 4 extracts a stack pointer of a new task from the stack pointer table of the work memory 2. The next task to start is task t
Ask0. That is, the task t which was interrupted before
A process for restarting ask0 is executed. Task task
0 is executed to the end, and the system call slp-tsk (task0-id) is executed at the last stage. As a result, the operation of clearing the corresponding bit of the bit matrix storage unit 10 from “task0-id” to “0” is performed. At the same time, the upper one bit of the priority register 13 is cleared to “0”, and the content of the priority register 13 becomes “0110”.

[Step S17] In the bit matrix storage section 10, the bit corresponding to task task0 is cleared to “0”. As a result, the priority encoder 12 outputs “011” indicating that the priority is “3”. The comparator 14 outputs a “1” signal to the OR gate 17 because the output of the priority encoder 12 is larger than the output of the priority register 13. Thus, the interrupt signal INT is asserted again.

[Step S18] Multiplexer 18
Extracts the corresponding priority line bit LB from the bit matrix storage unit 10 according to the priority “011” output from the priority encoder 12. at the same time,
The corresponding priority “011” of the priority order register 30
, That is, the order stored in L3 is selected by the multiplexer 31. The order “011” was stored in the L3 part of the priority order register. This is the result of the execution in step S11.

Therefore, in the decoder 32, 4
The mask information “000011111” that becomes “1” only is generated. This mask information has the contents of masking the upper 4 bits in the AND gate 23 and masking the lower 4 bits in the AND gate 22. As a result, from the priority encoder 25, the task ta
“011” corresponding to the rank of sk2 is output. Also, the task tas is output from the priority encoder 24.
“110” corresponding to the rank of k1 is output. Since the output of the OR gate 27 becomes “1”, the multiplexer 2
8 selects and outputs “011” as the signal output from the priority encoder 25.

[Step S19] The stack is saved as in step S3, and the save completion signal TC is asserted. The signal “011” output from the multiplexer 28 is stored in the order register 36 by the save completion signal. Furthermore, priority order register 3
The signal of “011” is stored in the register of L3 corresponding to “0”. The adder 38 generates a stack pointer address based on the output of the stack pointer table register 37, the output of the priority register 13, and the output of the order register 36.

[Step S20] The CPU 4 determines whether the adder 3
The work memory 2 is accessed using the stack pointer address output from the memory 8. Then, the CPU 2 retrieves the stack pointer from the corresponding address in the stack pointer table, and resumes the execution of the task task2 whose execution has been suspended halfway. Task task2
Is a system call slp-t immediately before the end of the processing.
Execute sk (task-id). Thereby, ta
A process of clearing the corresponding bit of the bit matrix storage unit 10 from “sk2-id” to “0” is executed. At the same time, the self-clear signal SCL is output from the decoder 15.

As a result, the signal output from the multiplexer 28 is decremented by the subtracter 33, and the value is output to the priority order register 30 through the multiplexer 34. Then, this value “010” is stored in the L3 portion of the priority order register 30.

[Step S21] In the bit matrix storage section 10, the bit corresponding to task task2 is cleared to "0". However, a bit corresponding to task task1 is stored in a portion corresponding to the same priority, and the output of the priority encoder 12 remains "1011". The comparator 14 outputs a comparison result. That is, the output “1011” of the priority encoder and the output “0011” of the priority register 13 are compared.

The multiplexer 18 stores the priority line bit LB according to the priority in the bit matrix storage 1
Take from 0. The content is “01000000”. This data is a line bit of a portion corresponding to the priority “3”. The multiplexer 31 selects and extracts the data of the L3 portion corresponding to the priority “011” from the priority order register 30. This is the decoder 32
Is converted into mask information. The content of the mask information is “00000111”.

[Step S22] The upper 5 bits of the AND gate 23 are masked, and the lower 3 bits of the AND gate 22 are masked. As a result, an all-zero signal is output from the AND gate 23. The priority encoder 25 outputs “000”. Also, AND gate 2
2 outputs the data corresponding to the priority line bit LB to the priority encoder 24. The priority encoder 24 outputs “110” to the multiplexer 28. Since the output of the OR gate 27 is "0", the multiplexer 28 outputs the priority encoder 2
4 is selected and output.

[Step S23] Similar to step S3, the stack is saved, and the save completion signal TC is asserted. When the save completion signal is asserted, the signal “110” output from the multiplexer 28 is stored in the order register 36. At the same time, a signal of "110" is stored in the L3 portion of the priority order register 30. The adder 38 outputs the stack pointer address SPA according to the output of the stack pointer table register 37 and the output of the priority register 13 and the order register 36.
Generate When task task1 finally calls the system call task1-id, the processing of all tasks ends.

<Effect of Specific Example 1> As described above, the real-time OS device of the specific example 1 shown in FIG. 1 stores information indicating the priority of each task to be scheduled and the priority order by the storage circuit. And the scheduling is performed entirely by hardware. When there is a system call for task switching from task to task, the interrupt signal output circuit including the comparator 14 and the like shown on the right side of FIG.
Output an interrupt signal to This circuit includes a circuit for reading out the priority of a task having the highest priority from the priorities and priorities of tasks stored in a storage circuit, a priority of the read task and a priority of a task being executed. And a circuit that outputs an interrupt signal for task switching to the processor when the read priority is higher than the priority of the task being executed. A task having a high degree of selection can be selected as a task to be executed next, and an interrupt signal can be generated and output by hardware.

The stack pointer address generation circuit including the lower right adder 38 in FIG. 5 supplies the CPU with the save stack pointer address of the immediately preceding task. Then, when the CPU completes the evacuation and receives the evacuation completion signal, it outputs a stack pointer address of a new task and causes the CPU to read a new stack pointer.
As described above, since the stack pointer address generation processing and the stack pointer address switching are performed by hardware, the load on the CPU is reduced, and high-speed processing is enabled.

Also, the priorities of the tasks saved immediately before or the tasks that have transitioned to the waiting state are retained by priority, and a part of the priority line bits read from the bit matrix storage unit is masked. Since the queue control circuit that selects the task at the head of the queue with the same priority as the task to be executed next is realized, the management of the queue of tasks that has been conventionally controlled by software can be realized by hardware.

<Specific Example 2> Interrupt processing is conventionally controlled by an interrupt controller. Many interrupt signals are input to the interrupt controller. The interrupt controller adjusts the conflict between these interrupt signals and holds one interrupt signal in the interrupt signal output register. This signal is sent to the CPU to activate the interrupt handler. The CPU analyzes the interrupt state and passes it to the application. Since the CPU executes a series of processes for processing the interrupt after the interrupt is asserted, the interrupt process becomes a heavy load. In this specific example, the interrupt processing is integrated with the hardware of the task scheduling processing of the specific example 1, and
Reduce overhead.

FIG. 10 is an explanatory diagram of the hardware configuration of a general interrupt controller. AND gate 41
Is a gate for receiving an interrupt signal from each unit.
The interrupt mask register 40 is a circuit that generates a mask signal according to the write setting and outputs the mask signal to the AND gate 41. A plurality of mask signals are supplied to the AND gate 41 for a plurality of interrupt signals. Then, the interrupt signal passed without being masked by the AND gate 41 is stored in the interrupt register 42.

The interrupt register 42 is provided with a plurality of interrupt signal holding areas corresponding to tasks and devices to be interrupted. The priority encoder 44 reads out the number of the highest priority interrupt signal stored in the interrupt register 42 and
Circuit. The OR gate 43 is a circuit that asserts an interrupt signal to the CPU when any area of the interrupt register 42 becomes “1”, that is, when an interrupt occurs.

FIG. 11 is a diagram for explaining a processing example of the interrupt handler. The CPU processes the output of the interrupt handler using a C-like program as shown in FIG. That is, when the output signal of the OR gate 43 is asserted, the CPU executes the interrupt handler program. In the interrupt handler program, the output of the priority encoder 44 is read to determine which interrupt signal has the highest priority. Next, swi
The corresponding processing process is called by the tch statement.
Processing corresponding to the interrupt signal is performed for the first time by this call. That is, the interrupt processing is executed in the order of the interrupt numbers N-1, N-2,... This is the same as the state in which tasks having the respective priorities just wait for processing. Therefore, in the case of software, an overhead for executing the program shown in FIG.

FIG. 12 is a block diagram of a bit matrix storage unit according to the second embodiment. The device of the second embodiment differs from the first embodiment only in the structure of this portion. The interrupt signals are connected to the bit matrix storage unit 10 such that eight sets of three interrupt signals are input, for a total of 24 interrupt signals. Assuming that the vertical axis in the figure is the Y axis and the horizontal axis is the X axis, for example, the first bit of the leftmost signal line is an interrupt signal of (7, 7). The second bit is an interrupt signal of (6, 7). The third bit is an interrupt signal of (5, 7).

The next six interrupt signals are interrupt signals whose first bits are (7, 6). The second bit is a (6, 6) interrupt signal. The third bit is a (5, 6) interrupt signal. In this example, 3 × 8, that is, a total of 24 interrupt signals are accepted, but this numerical value may be freely changed. Such an interrupt signal functions effectively only when the enable bit stored in advance for each coordinate unit is “1”. The enable bit is on the left side of the 2-bit data at each coordinate in the figure. On the right are the status bits.

That is, for example, when the enable bit of (7, 5) is "1" and the interrupt signal of the first bit of the third signal line from the left is asserted, the interrupt becomes valid. When an interrupt is enabled, a status bit is set along with the enable bit. That is, the data “11” is stored in the portion (7, 5). Note that an address register 11 is provided to write such an enable bit. The Y-axis direction in the figure is the priority, as in the specific example 1, and the priority encoder 12
Has the function of outputting the highest priority data based on the logical sum output similar to that of the first embodiment.

FIG. 13 is a diagram illustrating the initial assignment of interrupts when the second embodiment is executed. As shown in (a), in each of the lines 7, 6, and 5 indicating a high-priority task in the bit matrix storage unit 10, two-bit data is stored as an initial value. The left bit of the two bits indicates an enable bit. On the right are the status bits. Therefore, as shown in the figure, (7,
It can be seen that the enable bits are "1" in columns 5) and (6, 3).

FIG. 13B shows tasks (10) and (1).
The interrupt handlers 1) and (12) are shown. Task 10
Is assigned to (7, 5), the interrupt handler for task 11 is assigned to (6, 3), and the interrupt handler for task 12 is assigned to (5, 1).
In the lower priority, as in the specific example 1, (3, 6)
And (3, 3) show waiting tasks. If the priority of the interrupt processing is higher than that of a general task, such allocation makes it possible to schedule the interrupt and the general task in the same manner as in the first embodiment.

FIG. 15 shows a timing chart of the interrupt processing. The operation of the device of the second embodiment will be described with reference to FIG. First, at the timing t0, as shown in FIG. 14 (i), another task is executing a process. Then, at timing t1, the interrupt signal 63 shown in (c) is asserted. This 63 is
This is an interrupt signal corresponding to the coordinates of (6, 3). Since the enable bit at this coordinate in the bit matrix storage unit 10 is “1”, the status bit of the bit matrix (6, 3) becomes “1”. Also, since the priority is higher than other tasks, the 11th interrupt handler int-han
d1 is activated.

At the next timing t2, this time, FIG.
The interrupt signal 73 shown in (b) is asserted. However, since the enable bit of the corresponding coordinates (7, 3) in the bit matrix storage unit 10 is “0”, the status bit remains “0”. That is, no interrupt is accepted. Therefore, the 11th interrupt handler remains in the execution state. At the next timing t3, the interrupt signal 75 is asserted. Since the enable bit of the corresponding coordinate (7, 5) in the bit matrix storage unit 10 is "1", the state bit of this coordinate becomes "1".

Referring to the bit matrix storage unit 10, the 10th interrupt handler int-hand0 executed by this interrupt has a higher priority than the 11th interrupt handler int-hand1 executed so far. The 10th interrupt handler is activated.
When the No. 10 interrupt handler completes the process and negates the No. 75 interrupt signal, int-hand0 by the No. 10 interrupt handler clears its status bit to “0” and completes the process. The 11th interrupt handler int-hand1 interrupting again resumes execution (timing t4).

Next, at timing t5, the interrupt signal 5
1 is asserted. Since the enable bit of (5, 1) in the bit matrix storage unit 10 is “1”, the status bit at this coordinate becomes “1”. Here, comparing the 11th interrupt handler that is currently being executed with the 12th interrupt handler that has been interrupted, the 12th interrupt handler is not activated because it has a lower priority. At the timing t6, the processing of the eleventh interrupt handler ends, and the interrupt signal 63 is negated. The eleventh interrupt handler int-hand11 clears the status bit to “0” and completes the process.

At this timing, that is, at timing t6, 1
The second interrupt handler int-hand2 is activated. At the next timing t7, the twelfth interrupt handler int-hand2 completes the process and negates the interrupt signal. In this way, the execution of another task that was being executed before the interruption was input is resumed. Except for the part shown in FIG. 12, the same hardware as that of FIG. 1 is used, and the operation of scheduling an interrupt according to the priority order is completely the same as that of the first embodiment, and therefore, the duplicated description will be omitted.

<Effects of Specific Example 2> As described above, the bit matrix storage unit 10 is configured using the same hardware as that of the specific example 1.
By storing the interrupt signal in the CPU, the schedule of the interrupt signal can be realized by hardware.
Therefore, software processing for the interrupt handler becomes unnecessary, and it takes only a cycle of context switching from the assertion of the interrupt signal to the activation of the handler corresponding to the interrupt signal.
Therefore, interrupt processing with extremely high throughput can be performed.

In the above example, the reason why the enable bit is provided and the coordinates for accepting the interrupt are limited is as follows.
This is because the same function as that of the conventional interrupt mask register shown in FIG.
When the interrupt mask is unnecessary, the interrupt signal can be processed and controlled in exactly the same manner as in the first embodiment.

<Example 3> In a real-time OS device, an event flag may be used for a synchronization process between tasks. Eventflag system calls include
There are “event flag waiting state”, “event flag setting state”, and “event flag clear state”. In the event flag waiting state, information on the flag ID and the waiting pattern is held. In the event flag setting state, the flag ID
And the setting pattern are held. In the event flag clear state, the flag ID is held.

The task that has called the event-flag waiting system call has the same event flag I as another task.
The event flag setting system call of D is called, and the system enters a wait state until the set pattern becomes the same as the wait pattern. When the setting pattern becomes the same as the waiting pattern, the task that has called the eventflag waiting system call transitions from the waiting state to the executable state, and is connected to the task chain corresponding to the priority of the task. The task that has called the event flag setting system call executes the next instruction after setting the setting pattern.
The event flag clear initializes a pattern corresponding to the flag ID.

FIG. 15 is a diagram illustrating an example of the configuration of a general event flag queue. In the figure, an event flag pointer 45A is a pointer area indicating the head and the end of an event flag queue connected in a chain. Each queue 45
B holds the wait flag pattern and the set flag pattern of the event flag, and the TCB of the task in the wait flag pattern.

FIG. 16 is an explanatory diagram of an example of using an event flag. Here, there are three types of tasks as shown in (a), (b), and (c) of the figure, each of which calls a system call relating to an event flag. The task execution order is shown in (d). In the figure, “wai-flg” is a system call for waiting for an event flag, and arguments are arranged in the order of an event flag ID, a waiting pattern, and a task ID. se
t-flg is a system call for setting an event flag.
Arguments are arranged in the order of the event flag ID and the setting pattern. clr-flg is a system call for clearing an event flag, and takes an event flag ID as an argument.

First, when an event flag waiting system call (wai-flg) is made from task 0, the current pattern of the event flag pointer corresponding to the event ID (if1) and the waiting pattern are compared. The current pattern is “0x0” here. Here, the wait pattern is “0x3”. If they do not match, the TCB address of the task that called the system call is set in the TCB pointer of the event ID.
This task is task0. The wait pattern of TCB is “0x3”.

When a system call (set-flg) for setting an event flag is made in task1, the result of the logical OR of the set pattern is reflected on the current pattern of the event flag pointer corresponding to the event ID. The current pattern is “0x0” and the setting pattern is “0x1”. As a result of the logical sum, the current pattern becomes “0x1”, and T
It does not match the wait pattern of the CB queue “0x3”. Therefore, the waiting state of task 0 continues.

When a system call (set-flg) for setting an event flag is made in the next task 2, the set pattern is logically ORed with the current pattern of the event flag pointer corresponding to the event ID. The current pattern is “0x1” and the setting pattern is “0x2”. As a result of the logical sum of the two, the current pattern becomes “0x3”. TCB
The queue waiting pattern is also “0x3”. Therefore, they match, the TCB address is extracted from the TCB pointer of the event flag if0, and the task 0 becomes ready for execution.

When the event flag clear system call (clr-flg) is made in task task0, the current pattern of the event flag pointer is cleared to "0" corresponding to the event ID.

Conventionally, all of the above processing has been executed by the CPU using software. Therefore, it takes a large number of cycles from the setting of the event flag until the task waiting for the flag becomes executable. If the event flag needs to be processed immediately, there is a problem with the overhead of the event flag processing.

FIG. 17 is a block diagram of hardware for processing an event flag according to the third embodiment. By replacing the portion of the adder 38 shown in FIG. 5 with the circuit shown in FIG. 17, event flag processing becomes possible. The order register 36 and the stack pointer table register 37 shown in FIG. 5 and the priority LY output from the priority order register 13 shown in FIG. 1 are input to this circuit.

The multiplexers 48, 49, 52, 54,
56, 57, 61 and 62 are all sequencers 47
Operates to select and output one of the input signals. The ALU 51 is a circuit for incrementing the address and determining whether the waiting pattern matches the current pattern. The 0 detection circuit 46 is a circuit for determining whether the ALU 51 has detected “0”. That is, AL
When detecting that U51 has output "0", the sequencer 47 is operated to be reset.

Flag queue head address register 50
Is a register that receives the head address of the block of the event flag information as data MD and holds it. The flag queue read address register 58 is a register for holding an address when data is read from the block of the event flag information output from the multiplexer 56. The flag queue write address register 59 is a register for holding an address when data is written to the event flag information block output from the multiplexer 57.

The registers 53 and 55 are for temporarily holding event flag information. Driver 6
3 is for holding the output of the multiplexer 61. From this driver 63, the work memory data WD
Is output. The work memory address WA is output from the multiplexer 62.

FIG. 18 shows an example of allocating event flag information on the work memory. Each of the event flag information blocks 0 to n-1 has a wait flag pattern, a current flag pattern, a handler ID, and a spare area. The head is the address stored in the flag queue head address register 50 shown in FIG.

[Step S1-0] First, the task tas
k0 is the system call wai-flg (if1, 0x
The process after calling 3) will be described. This call is directly transmitted to the sequencer 47. When the call is transmitted to the sequencer, the sequencer 47 performs the following operation and simultaneously stops the CPU 4.

[Step S1-1] The task task0 is started, and the system call wai-flg is called. In this system call, the value of the wait flag pattern “0x3” is set in the event flag if1. The event flag if1 has “1” as an index value. Therefore, the value is temporarily stored in the register 53.

[Step S1-2] The address information of the flag queue head address register 50 and the register 53
ALU5 is shifted to the right together with the index value of
Add at 1. This value is stored in the flag queue write address register 59.

[Step S1-3] The event flag waiting value “0x3” is set in the register 55. [Step S1-4] The register 5 is stored in the work memory of the address value indicated by the flag queue write address register 59.
Write the event flag waiting value “0x3” of No. 5.

[Step S1-5] The value of the flag queue write address register 59 is set to "1" by using the ALU 51.
And the result is stored in the flag queue read address register 58. [Step S1-6] Next, the information flag pattern of the event flag information block 1 written at the address indicated by the flag queue read address register 58 is read from the work memory, and is written to the register 53.

[Step S1-7] To determine whether the value of the register 55 containing the wait flag pattern of the first event flag information block matches the value of the register 53 containing the current flag pattern. ,
The ALU 51 performs an exclusive OR process by receiving both signals. If they match, the output of ALU 51 is "0". This is detected by the 0 detection circuit 46.
In this case, they do not match. The result is transmitted to the sequencer 47.

[Step S1-8] The value stored in the flag queue write address register 59 is fetched into the ALU 51, and "2" is added to the value to make the address value of the handler ID of the top event flag information block. . Write this value back again. That is, the bit matrix storage unit 1
The ID number of the task task0 corresponding to the address 0 is set as data MD, sent to the register 53 through the multiplexer 52, and stored therein.

[Step S1-9] The value of the flag queue write address register 59 is accessed as an address signal to the work memory, and the data stored in the register 53 is written. Further, the ID number of task0 corresponding to the bit matrix address stored in the register 53 is passed to the bit matrix storage unit 10, and the bit of the corresponding portion is cleared. As a result, an interrupt occurs as in the first embodiment, the task task0 is saved on the stack, and a new task is started. Sequencer 47
Restarts the operation of the CPU.

[Step S2-0] The processing after the task task2 calls the system call set-flg (if1, 0x1) is started. This call is passed directly to the sequencer. [Step S2-1] The task task1 is activated, and the system call set-flg is called. In this system call, the value “0x1” of the set flag pattern is set in the event flag if1. Since the event flag has "1" as an index value, the value is temporarily stored in the register 53.

[Step S2-2] The address information stored in the flag queue head address register 50 and the index value stored in the register 53 are shifted to the right using the ALU 51 and carry added, and the result is added to the flag queue. The data is simultaneously stored in the read address register 58 and the flag queue write address register 59.

[Step S2-3] Next, the data of the current state flag pattern of the first event flag information block is fetched from the work memory and stored in the register 55. [Step S2-4] The event flag set value “0x1” is fetched from the data bus and stored in the register 53.

[Step S2-5] The ALU 51 fetches the contents of the register 53 and the register 55 and calculates the logical sum of the two. Then, the result is written back to the register 55. [Step S2-6] The data stored in the register 55 is written to the work memory at the address indicated by the flag queue write address register 59. As a result, the updated data of the current state flag pattern is written.

[Step S2-7] The address value of the flag queue read address register 58 is fetched into the ALU 51, "1" is added thereto, and the result is written back to the flag queue read address register 58. [Step S2-8] Read flag queue address 5 from work memory
The wait flag pattern of the event flag information block indicated by 8 is read. This event flag information block is the first information block. Then, the result is written into the register 53.

[Step S2-9] The ALU 51 calculates an exclusive OR of the data written in the registers 53 and 55. The result is returned to the 0 detection circuit 4 again.
Judge at 6. Also in this case, the ALU 51 does not output “0”. That is, since the content stored in the register 53 does not match the content stored in the register 55, the process is executed as it is. [Step S2-10] The task task1 calls the system call slp-tsk (task1-id) and completes its own process.

[Step S3-0] Task task2
Is the system call set-flg (if1, 0x2)
The processing after calling is started. This call:
It is transmitted directly to the sequencer 47. [Step S3-1] The task task2 is activated, and the system call set-flg is called. In this system call, the value “0x2” of the setting flag pattern is set in the event flag if1. Since the event flag has "1" as an index value, the value is temporarily stored in the register 53.

[Step S3-2] Thereafter, the current flag pattern and the waiting flag pattern are stored in the register 5 respectively.
3 and stored in the register 55. That is, step S3-
From step 1 to storage of these patterns, step S2-
2 to S2-8, the same procedure will be omitted. In this case, the data stored in the registers 53 and 55 are both “3”.

[Step S3-3] The ALU 51 takes an exclusive OR of the data stored in the register 53 and the register 55. The result is returned to the 0 detection circuit 46 again.
Judge. In this case, the ALU 51 outputs “0”. That is, the content stored in the register 53 and the content stored in the register 55 match. Therefore, 1
In order to take out the handler ID of the event flag information block, the flag queue read address register 5
The content of 8 is taken out to the ALU 51 and "1" is added.
Then, the address value of the handler ID is written back to the flag queue read address register 58.

[Step S3-4] 1 from work memory
After reading the handler ID of the event flag information block and storing it in the register 53, it is transferred to the address register of the bit matrix storage unit 10. Example 1
As described above, the control is performed so that “1” is set in the element of the corresponding bit matrix.

[Step S3-5] The flag queue write address register 59 is used to generate the wait flag pattern address of the first event flag information block.
Is taken into the ALU 51, and "1" is added thereto. Then, the address value of the handler ID is written back to the flag queue write address register 59 again. [Step S3-6] "0" is written to the address indicated by the flag queue write address register 59 on the work memory to clear the wait flag pattern.

[Step S4-0] The processing after the task task0 calls the system call cif-flg (if1) is started. This call is made to sequencer 4
It is conveyed directly to 7. [Step S4-1] The task task0 is restarted, and the system call clr-flg (if1) is called. Since the event flag has "1" as an index value, the value is temporarily stored in the register 53.

[Step S4-2] The address information stored in the flag queue head address register 50 and the index value stored in the register 53 are fetched into the ALU 51, which is shifted right and carry-added. Then, the result is stored in the flag queue write address register 59. [Step S4-3] "0" is written to the data of the current flag pattern of the first event flag information block in the work memory.

<Effect of Specific Example 3> As described above, when there is a task waiting for an event flag, an area for storing event flag information for each task is provided in the work memory. A circuit for comparing the current flag pattern and the wait flag pattern, including the current flag pattern and the wait flag pattern, and a bit matrix storage unit for transferring the task in the wait state to the executable state when the two match. Since the circuit for outputting the data for rewriting the contents and the write address is provided, it becomes possible to execute the event flag processing by dedicated hardware using the same hardware as in the first embodiment. Therefore, the task waiting for the event flag can be started at high speed.

A system call for setting a flag pattern, for example, set-flg, and a system call for clearing a flag pattern, for example, cir-flg, have a CP
After U executes the system call, another operation can be continued, so that the flag processing and the application processing by the CPU can be executed simultaneously in parallel.

<Specific Example 4> The real-time OS has a cyclically activated handler for periodically executing software at regular intervals. When this is normally processed, an interrupt is issued to the CPU at regular intervals from a hardware timer and the CPU is executed. Finds a handler corresponding to the waiting interval from the interrupt handler and activates the task.

FIG. 19 shows a hardware block diagram of the cyclically activated handler. The timer 64 is connected to the CPU 4, and an interrupt signal is asserted from the timer 64 at a constant cycle. When the interrupt signal is asserted from the timer 64, the CPU 4 activates an interrupt handler,
Perform predetermined software processing. This is the conventional method.

FIG. 20 is a diagram for explaining the configuration of the cyclically activated handler queue. The handler queue stores a start interval, a current remaining interval, and a handler address. The cyclically activated handler queue pointer 39 displays the head and tail of the handler queue. When an interrupt is received from the timer, the CPU sets the cyclically activated handler queue pointer 3
The pointer is traced from 9 to check the value of the block remaining interval of each cyclically activated handler. Then, from this value, "1"
pull. When the subtraction result becomes "0", the value of the activation interval is copied to the current remaining interval, and the program indicated by the handler address is activated. After performing such operations up to the end of the queue, the process returns to the original process.

As described above, when the cyclic handler is designated, the CPU is stopped because other processes are executed and the search of the handler queue and the subtraction of the timer are executed, so that the CPU is overloaded. In this specific example, this processing is realized by hardware.

FIG. 21 shows a hardware block diagram of the periodic startup according to the fourth embodiment. This circuit is arranged in the adder 38 for generating the stack pointer address shown in FIG. Specific example 3 of FIG.
Similarly to the above, the ALU 51 performs arithmetic processing, and the multiplexers 48, 49, 52, 54, 56, 57, 61, and 62 are operated by the sequencer 47, and the work memory data W
D and a work memory address WA are generated.

This circuit differs from the third embodiment in that a timer 100 is provided. Further, a time queue head address register 104, a multiplexer 103, a time queue tail address register 105, and a coincidence circuit 106 shown in the upper right part of FIG.
6 and 57 are configured by a timer queue read address register and a timer queue write address register. The other parts are completely the same as those of the circuit of the third embodiment.

The timer 100 is a timer that periodically asserts an interrupt signal for activating a handler. The time queue head address register 104 is a register for holding an address when reading a block of cyclically activated handler information. The time queue tail address register 105 is a register that holds the last address of the block of the cyclically activated handler information.

The matching circuit 106 is a circuit for determining whether or not the write address matches the last address of the block of the cyclically activated handler information. The timer queue read address register is a register for holding an address when reading a block of cyclically activated handler information.
The timer queue write address register 102 is for holding an address at the time of writing a block of cyclically activated handler information.

<Operation> FIG. 22 is a diagram for explaining an example of allocation of cyclically activated handler information on the work memory. In this example, as shown in this figure, the cyclically activated handler information blocks are allocated from 0th to -1st on the work memory, and information corresponding to the conventional handler queue is stored in order. This leading address is the address indicated by the time queue head address register 104. The cyclically activated handler information block has a remaining time, a cyclical time, and a handler ID corresponding to a bit matrix address.

[Step S1-0] Here, an initial process is executed. [Step S1-1] First, the timer 100 asserts an interrupt signal to the sequencer 47. [Step S1-2] The sequencer 47 receives the interrupt, and stores the address information stored in the time queue head address register 104 into the timer queue read address register 101 and the timer queue write address register 1.
Copy to 02.

[Step S2-0] Next, the process of the cyclically activated handler information block 0 is executed. [Step S2-1] The address indicated by the timer queue read address register 101 is accessed from the work memory, and the remaining time data of the cyclically activated handler information block 0 is copied to the register 53. This processing is performed in the same manner as in the specific example 3, except that the multiplexer 48, the path from the timer queue read address register 101 to the register 53,
52 to operate to transfer data. Next, the data in the register 53 is read by the ALU 51, "1" is reduced from the data, and the data is written back to the register 53 again.

[Step S2-3] The 0 detection circuit 46 is operated to determine whether or not the output of the ALU 51 is "0". If it is not "0", it is determined that this cyclically activated handler cannot be activated yet. If the remaining time is "0", the output of the ALU 51 becomes "0", and thus, 0 is detected at this time. [Step S2-4] The address stored in the timer queue write address register 102 is output to the work memory, and the remaining time data of the cyclically activated handler information block 0 stored in the register 53 is written back.

[Step S2-5] Similarly, the address value stored in the timer queue write address register 102 is transferred to the ALU 51, and "3" is added. Then, the result is stored in the timer queue write address register 1.
Write it back to 02. At the same time, the timer queue read address register 101 writes the same address value. In this way, by advancing the address by “3”, the state where the remaining time of the cyclically activated handler information block 0 is read from
The state shifts to a state where the remaining time of the cyclically activated handler information block 1 is read. That is, the processing of steps S1-0 and 2-0 decrements the remaining time of the cyclically activated handler information block 0, determines that the remaining time is not "0", and proceeds to the next processing.

[Step S3-0] Here, the process of the cyclically activated handler information block 1 is executed. [Step S3-1] The address indicated by the timer queue read address register 101 is accessed from the work memory. Then, the remaining time data of the cyclically activated handler information block 1 is read, and this is written to the register 53.

[Step S3-2] The data stored in the register 53 is taken out, and the ALU 51 is used to subtract "1". [Step S3-3] The 0 detection circuit 46 determines whether or not the result of the ALU is "0". For example, it is assumed here that the output of the ALU 51 has become “0”.
In this case, it is determined that the cyclically activated handler specified by the cyclically activated handler information block 1 can be activated. Based on this, the activation process of the cyclically activated handler proceeds.

[Step S3-4] In order to access the cycle time data of the cycle activation handler information block 1,
The address value of the timer queue read address register 101 is transferred to the ALU 51, and "1" is added thereto. The value is written back to the timer queue read address register 101. The contents of the timer queue write address register 102 are stored here as they are.

[Step S3-5] The address indicated by the timer queue read address register is accessed from the work memory, and the cycle time data of the cycle start handler information block 1 is written into the register 53. The address of the timer queue write address register 102 is output to the work memory, and the cycle period data of the cycle start handler information block 1 stored in the register 53 is written to the area for displaying the remaining time data. Thus, the data corresponding to the remaining time is returned to the initial value.

[Steps S3-6, 3-7] In order to access the handler ID of the cyclically activated handler information block 1, the address “1” of the timer queue read address register is transferred to the ALU, and “1” is set therein. to add. The result is written back to the timer queue read address register 101. At the same time, this value is also written to the timer queue write address register 102.

[Step S3-8] The handler ID is accessed from the work memory, and the bit matrix storage 10
Is changed to "1" in the bit matrix at the corresponding address. Thus, the task corresponding to the cyclically activated handler is set to the execution state. Since the task corresponding to the cyclically activated handler is assigned to a high priority, the task is immediately executed according to the procedure of the first embodiment.

[Step S3-9] In order to access the next cyclically activated handler information block, the address value of the timer queue read address register is transferred to the ALU 51, and "1" is added. Then, the result is written to the timer queue read address register 101 and the timer queue write address register 102.

[Step S4-0] Here, the process of the cyclically activated handler information block 2 is executed. [Step S4-1] The address indicated by the timer queue read address register 101 is accessed from the work memory, and the remaining time data of the cyclically activated handler information block 2 is written into the register 53. For example, if the content of the remaining time data is set to “0”, it indicates that the cyclically activated handler has not been activated. It is assumed that the remaining time data of the cyclically activated handler information block 2 is “0”.

[Step S4-2] The data stored in the register 53 is transferred to the ALU 51, and "1" is subtracted. [Step S4-3] The ALU 51 is detected by the 0 negative detection circuit 108.
Detects that the output result of has become negative. This indicates that the cyclically activated handler has not been activated. The result is output to the sequencer 47. In this case, the sequencer 47 operates to start accessing the next cyclically activated handler information block. That is, step S3-4 to step S3-9, or step S3
The processing of 2-4 to step S2-5 is omitted, and the operation is performed so that the addresses of the timer queue read address register 101 and the timer queue write address register 102 are jumped.

[Step S4-4] That is, the address value of the timer queue read address register 101 is read, and "3" is added in the ALU 51. Then, the result is written into the timer queue read address register 101. At the same time, the same address is written to the timer queue write address register 102.

[Step S5-0] Here, the last process of the cyclically activated handler information block 5 is executed. [Step S5-1] The end of the cyclically activated handler information block is when the address value of the timer queue write address register matches the address value of the time queue tail address register 105. As shown in FIG. 22, the address value of the last cyclically activated handler information block is stored in the time queue tail address register 105. Therefore, the content of the timer queue write address register 102 is compared by the matching circuit 106,
If they match, the handler search ends. The end result is notified to the CPU.

Therefore, as described above, when the timer 100 is started and the handler processing is started, the circuit shown in FIG. 21 automatically executes the processing until the handler ends. Then, the information of the activation of the handler is stored in the bit matrix storage unit 10. Then, like other tasks, they are processed in order of priority.

<Effect of Specific Example 4> As described above, when a cyclically activated handler exists, a memory for storing cyclically activated handler information including a remaining time and a periodic time for each handler is provided. The remaining time is decremented as an initial value, and a circuit for detecting that the remaining time has run out, and when the remaining time runs out, the priority and priority of each task so as to shift the corresponding cyclically activated handler to an executable state. Since the data for rewriting the contents of the storage circuit storing the information indicating the rank order and the circuit for outputting the write address are provided, the CPU does not need to be involved in the processing at all until the matching circuit detects the end of the handler processing. Absent. Therefore, the handler process can be performed at high speed, and the load on the CPU is sufficiently reduced. In this specific example, the same circuit as that of the specific example 3 can be used, and the periodic start processing and the event flag processing can be realized by the same hardware except for the sequencer. That is, dual use is possible.

<Example 5> When a plurality of CPUs are used and the OS
To run the application and the application
Often controls the OS and applications, and the other CPU controls the remaining applications. In this case, the CPU that controls the OS spends many cycles on system call processing from another CPU. Therefore, O
There is a problem that the application execution efficiency of the CPU controlling S is reduced.

There is also a method in which one CPU executes only the OS, and another CPU executes an application. In this case, when all applications do not call the OS system call, the CPU assigned to the OS hardly operates. That is, resources are not effectively used. Conversely, when there are a plurality of system calls from another CPU, the processing for the other system call is suspended until the processing for one system call is completed. In any case, it is not easy to efficiently execute the real-time OS by the multiprocessor.

FIG. 23 is a block diagram showing a modification of the real-time OS device. This device comprises a main memory 66,
Work memory 67, decoder 68, and multiple CPUs 60
Is provided. Further, an RTOS coprocessor 65 for realizing the OS by hardware is provided. The main memory 66 holds application programs and data of the CPU 60. Except for the case where the CPU 69 has a so-called multiprocessor configuration, the overall configuration is the same as the device of the first embodiment described with reference to FIG.

FIG. 24 shows a real-time OS according to the fifth embodiment.
FIG. 2 shows a device block diagram. Also in this example, the same 8 × 8 bit matrix storage unit 10 as in the first embodiment is used. That is,
Here, 8 × 8 elements are stored. However, each element is different from the specific example 1 and is all represented by 2 bits, and the state is assigned as follows. “00” indicates a stopped state. “01” indicates an executable state. “10” indicates a waiting state. “11” indicates an execution state.

The configuration in which the write request HRCS, data MD, and address MA are input and the configuration in which these are decoded by the decoder 72 are the same as in the first embodiment. Decoder 72
, A signal ADRN in which the priority and the priority are combined is input. The first-in first-out memory 73 stores the write request HRC
S, the data MD, the address MA, and the output of the decoder 72, and are stored and output in the order of input.
O. The output of the decoder 72 is temporarily stored in the first-in first-out memory 73, and is output as a self-clear signal through a flip-flop 75.

The differentiating circuit 71 is a circuit that receives a mode signal output at the time of mode switching and outputs a signal for controlling the update of the first-in first-out memory 73. The multiplexer 74 is a circuit that selectively controls a write address and data to be written to the bit matrix storage unit 10. The multiplexer 74 operates to select one of the output of the first-in first-out memory 73 and the output of the ADRN and supply the selected one to the bit matrix storage unit 10.

The output from the first-in first-out memory 73 is selected by a system call. On the other hand, the selection of the ADRN is performed to make a transition from the executable state to the execution state, that is, to change the state. Priority encoder 12
Has exactly the same function as the first embodiment, calculates the highest priority in the executable state, and outputs 4-bit data corresponding to the highest priority.

Flip-flop 75 also adjusts the timing of the self-clear signal. The priority register 76 stores the output of the priority encoder 12, in which the upper half holds the priority level value of the CPU0 and the lower half holds the priority level value of the CPU1.

The MIN 77 is a selector for selecting a priority having a smaller priority level value held in the priority register 76 and outputting the level value and the CPU number. The priority level value is output to the comparator 78. The output of the priority encoder 12 is applied to the other terminal of the comparator 78. The CPU number is output to the register 82. If the priority level values stored in the priority register 76 are equal, the CPU
The number of 0 and its level value are output.

The selector 81 is a multiplexer for selecting and outputting one of the level values stored in the priority register 76. The number output by the MIN 77 is stored in the register 82, and the selection operation of the selector 81 is controlled by the number stored in this register. The register 82 stores the MI
The output of N77 is stored, and the stored contents are held until the time of switching from the interrupt mode.

The comparator 78 and the OR gate 79 are described in the first embodiment.
Works the same as. That is, the comparator 78 compares the output of the priority encoder 12 with the output of the MIN 77, and outputs “1” when the output of the priority encoder 12 is large. The OR gate 79 is a circuit that calculates the logical sum of the self-clear signal and the output of the comparator 78 and outputs the result to the flip-flop 80.

The selector 83 selects the CPU0 interrupt and the CPU
This is a circuit for asserting an interrupt signal of one interrupt. The signal output from the flip-flop 80 is output to the selector 83 by the CPU 0 interrupt or CP.
Output as a U1 interrupt. The signal stored in the register 82 controls the output destination of the selector 83.

The priority-based order detection circuit 85 includes the multiplexer 18 shown in FIG. 1 and the AND gate 2 shown in FIG.
2, 23 and a circuit including the multiplexer 28 are collectively displayed. The contents are exactly the same as in the first embodiment. The multiplexer 84 is a circuit that, when the self-clear signal is asserted, selects and outputs a signal corresponding to the lower order of the write address to the bit matrix storage unit 10, that is, the priority order.

FIG. 25 is a block diagram of a stack pointer address generation circuit of the device of the fifth embodiment. This figure is different from the example 1 in a multiplexer 86 and a register 87. The multiplexer 86 is a multiplexer that selects, when the self-clear signal is asserted, a portion corresponding to the higher order of the write address of the bit matrix storage unit 10, that is, the portion corresponding to the priority.

The register 87 is a register for holding the order. This holding timing is when the save completion signal generated when the stack address of the old task is written in the stack pointer table is asserted.
The register 88 is a register that stores an address indicating the top of the stack pointer table. The function of the adder 38 is the same as that of the first embodiment.

The specific operation of the above circuit will be described below. FIG. 26A shows the initial state of the address and bit matrix of each task. (B) to (e) show the contents of tasks task0 to task3. As shown in FIG. 26A, the task task0 and the task1 have bit matrices corresponding to “01”.
As a result, both tasks are in an executable state.
On the other hand, the corresponding bit matrices of the tasks task2 and task3 are “00”. Therefore, these tasks are dormant.

For simplicity of operation, each task will use only a maximum of two system calls.
“sta-tsk” means activation of a task. The task corresponding to the task ID of the argument is changed from the stop state to the execution state. That is, in this case, the content of the bit matrix is changed from “00” to “01”. ext-tsk
Is for causing the in-task being executed to transition to the stopped state. That is, the content of the bit matrix is "1".
1 is transited to “00”.
The number between * and * / corresponds to the number of the next process.

FIG. 27 is a diagram for explaining the execution order of the tasks on each CPU. In this figure, (1) to (11)
Up to this, a time chart showing the operation status of the task in chronological order is shown. The system calls are executed in the order shown in the figure for each CPU. PRIR0 in the figure
And PRIR1 indicate the priority set in the priority level register of each CPU. Hereinafter, (1)-shown in this figure
The operation of the steps up to (11) will be described in order.

[Step (1)] First, the priority encoder 12 shown in FIG. 24 takes out the executable element having the highest priority from the bit matrix storage section 10. When the bit matrix having the contents shown in FIG. 26A is processed, the output is “1110”. The most significant bit is a bit indicating validity or invalidity as in the first example. Therefore, a signal corresponding to the priority 6 to which the task task0 is allocated is extracted and supplied to the comparator 78.

Since the priority register 76 is in the initial state, it is all 0s. Therefore, the minimum value “000” is obtained from MIN77.
"0" is output to the comparator 78. The number "0" is also output.
Is output to the register 82. The register 82 holds this number “0” until the interrupt mode is canceled. The comparator 78 determines that the output of the priority encoder 12 is larger, and outputs “1”. This signal passes through the OR gate 79 and sets the flip-flop 80.

[0206] "0" is stored in the register 82, and this is input to the selector 83. As a result, the selector 8
The output of the flip-flop 80 input to CPU 3 is
An interrupt is output to the corresponding processor. That is, the interrupt signal is asserted here. As a result, the CPU 0 executes context switching.
At the same time, CPU0 saves the register on the stack.

The output of the stack pointer table register 88 is input to the adder 38. The other inputs are initially "0", so that the addition result is the content stored in the stack pointer table register 88. Therefore, the stack pointer address output as a result is C
The evacuation processing of PU0 is performed. When the save completion signal is asserted by the CPU 0, the priority register 76 is updated.

On the other hand, the priority order detection circuit 85 fetches an executable priority line bit having a priority “6” from the bit matrix storage unit 10. This signal is supplied to the multiplexer 86 and the order register 87 shown in FIG. The order register 87 stores this signal as it is. Here, since the output of the stack pointer table register 88 and the output of the order register 87 are input to the adder 38, the value of the stack pointer address is “11”.
0010 ".

FIG. 28 shows a timing chart from the encoder to the CPU interrupt. (A) in the figure is a system clock. At the timing t1 in the figure, the priority encoder 12 starts. It is assumed that the register 82 has output a signal of “0” before this. At this time, at the rising edge of the clock at the timing t2, the interrupt signal of the CPU 0 is asserted. CPU
When the 0 interrupt signal is asserted, the old task is saved to the stack.

At the rise of the clock at tn, the save completion signal is asserted, and at the rise of the clock at tn + 1, the priority is stored in the priority register. Also,
The output from the priority order detection circuit 85 is stored in the corresponding priority order register 30. The output of the priority order detection circuit 85 is stored in the order register 87.

FIG. 29 is a diagram for explaining the switching of CPU modes and timing. FIG. 7A is a diagram for explaining the switching of the interrupt mode of the CPU. As shown in the figure, when an interrupt occurs, the mode shifts from the normal mode to the interrupt mode. In the interrupt mode, the current register is saved on the stack, and the new register is restored from the stack. When the interrupt mode ends, the mode returns to the normal mode again.

(B) is a timing chart for mode switching. When the interrupt signal is asserted at the timing t1 in the figure, the CPU enters the interrupt mode. That is, the interrupt mode signal is valid from timing t1 to t2 in the drawing. This is the interrupt mode. During this time, as shown in (a), the current register is saved to the stack and the stack is restored to the new register.

Thereafter, the mode returns to the normal mode.
At timing t2, the interrupt mode signal is negated, and the differentiating circuit 71 shown in FIG. 24 is asserted. As a result, the data and address stored first in the first-in first-out memory 73 are stored in the multiplexer 7.
4 to the bit matrix storage unit.

Thus, the contents of the bit matrix storage section 10 are updated. In the case of this example, the bit state of the element (6, 2) of the bit matrix storage unit 10 is “01”.
To "11", that is, from the executable state to the executable state.

[Step (2)] When the bit state of the element (6, 2) in the bit matrix storage section 10 is rewritten from “01” to “11”, the output of the priority encoder 12 becomes the next executable state. Output the priority level of task1. This content is “1011”. The MIN 77 outputs data without priority data, that is, data of the content “0000” and its CPU number “1”.

The comparator 78 compares the output of the priority encoder 12 with the output of the MIN 77. Since the output of the priority encoder 12 is larger, the comparator 7
8 outputs "1". This signal sets the flip-flop 80 through the OR gate 79. Register 8
2 stores “1” as described above.
This is input to the selector 83. The selector 83 sets the output of the flip-flop 80 as a CPU1 interrupt signal according to this control. That is, the CPU1 interrupt signal is asserted.

Thereafter, the processing is performed in the same manner as in step (1), and then the bit state of the element (3, 1) in the bit matrix storage unit 10 is rewritten from "01" to "11".

[Step (3)] The system call “start-t” is executed by the task “task0” operating on the CPU0.
sk (task3-id) is issued. Task3-id on the bit matrix storage unit 10 (4,0)
"01" is written to the element of. As a result, the task corresponding to this element becomes executable.

[Step (4)] The output of the priority encoder 12 is a task 3-id (4, 0).
Is the value corresponding to the element of. This content is “1100”
It is. The comparator 78 compares “1011” stored in the priority register 76 with “1100”. “101
Since "1" is smaller, it is output to the comparator 78. The comparator 78 determines that the output of the priority encoder 12 is larger, and outputs the signal of "1" again.

The MIN 77 provides the register 82 with
The signal "1" is output. Therefore, register 8
The selector 83 is controlled by the output of 2, and the CPU1 interrupt is asserted. Due to the CPU1 interrupt, the element (3, 1) of the bit matrix storage unit 10 of task1 changes from “11” to “10”. That is,
Transition the state from the execution state to the executable state. Thereafter, processing is performed in the same manner as in step (1), and the bit state of the element (4, 0) of the bit matrix
It is rewritten from "1" to "11", that is, transition from the executable state to the executable state is performed when switching from the interrupt mode.

FIG. 30 shows a system call "sta-ts".
4 shows a timing chart of the operation of k (task3-id). This figure is described in the same format as FIG.
At timing t1, the bit matrix
The element (4, 0) corresponding to k3 is updated. That is, the content is updated from “00” to “01”. at the same time,
The number output by the MIN 77 is stored in the register 82. At timing t2, the comparison in the comparator 78 is performed, and at timing t3, the interrupt signal is asserted.

When the interrupt signal is asserted, the old task is saved to the stack. When the save completion signal is asserted at the rise of the clock at tn, tn
At the rising edge of the +1 clock, the element on the bit matrix of task1 is rewritten from "11" to "10". That is, the state is switched from the execution state to the waiting state. At the same time, the contents of the priority register 76, the order register 87, and the priority order register 30 are updated.

[Step (5)] It is assumed that task0 issues an ext-tsk system call for stopping itself. In this case, the decoder 72 determines whether the address for the bit matrix matches the address of the task running on the CPU. If they match, "1" is set in the self-clearing signal storage portion of the first-in first-out memory 73. When data corresponding to the ext-tsk system call comes to the head of the first-in first-out memory 73, a write operation to the bit matrix storage unit 10 is performed. In this case, the bit matrix storage unit 1
The element (6, 2) of task task0 on “0” is “11”
To “00”. That is, a transition is made from the execution state to the stop state.

At the same time, PRIR0 of priority register 76
Clear The multiplexer 74 selects a write address according to the self-clear signal. The output of the priority order detection circuit 85 is input to the multiplexer 86 shown in FIG. The subtracter 33 subtracts the content of the multiplexer 86, and the content is stored in the priority order register 30 here. The self-clear signal is output from the multiplexer 8
The signal input from the selector 81 is sent to the subtracter 33 through the multiplexer 4 and the multiplexer 86.

The multiplexer 34 selects the output of the subtracter 33 according to the self-clear signal and outputs it to the priority order register 30. As described in the first embodiment, the writing to the priority order register 30 is controlled by the self-clear signal. On the other hand, the self-clear signal is a CPU0 interrupt signal through the OR gate 79 and the flip-flop 80 in FIG. That is, the CPU0 interrupt is asserted.

[Step (6)] When the contents of PRIR0 of the priority register 76 are cleared, MIN
From “77”, “0000” is selected and output to the comparator 78. The number “0” is output to the register 82.
The comparator 78 outputs “1” because the output of the priority encoder 12 is larger than the output of MIN77. Thus, the CPU1 interrupt signal is asserted. It should be noted that “1” is stored in PRIR0 of the priority register 76.
011 "is set, and the process is performed in the same manner as in step (1), and the bit state of the element (3, 1) in the bit matrix storage unit 10 is rewritten from" 01 "to" 11 ". It is rewritten from the executable state to the executable state.

FIG. 31 shows a system call ext-ts
6 shows a timing chart of k (task0-id).
At timing t1, the state bit corresponding to task0 stored in the bit matrix storage unit 10 is set to the stop state. At the same time, the valid bit of the priority register 76 is cleared. At timing t2, the self-clear signal is asserted, and at the same time, the contents of the priority order register 30 are updated.

The output of the priority encoder 12 changes due to the update of the contents of the bit matrix storage unit 10, and the interrupt signal is asserted at timing t3. When the interrupt signal is asserted, the old task is saved on the stack. At the rise of the clock at tn, the save completion signal is asserted, and at the rise of the clock at tn + 1, the priority register 76, the order register 87, and the priority order register 30 are updated. Δ
* 2 indicates the timing.

[Step (7)] The system call "sta-tsk" is executed by task1 indicating the CPU0 state.
(Task2-id) is issued. “01” is added to the element (3, 4) that is task2-id on the bit matrix.
That is, the information of the executable state is written. The output of the priority encoder 12 and the output of the MIN 77
Are compared. Since both are the same value, the output of the comparator 78 remains "0".

[Step (8)] Task3 issues an ext-tsk system call for stopping itself. At this time, the element (4, 0) of task0 on the bit matrix storage unit 10 is changed from “11” to “00”. At the same time, PRIR1 of the priority register 76
Clear The self-clear signal is output from the OR gate 79 to the selector 83, and the CPU1 interrupt is asserted.

[Step (9)] Since PRIR1 of the priority register 76 is cleared, the MIN 77 outputs "000" and the CPU number "1". Comparator 78
Is the output of the priority encoder 12 and MIN77
And the output of the priority encoder is large, the interrupt signal is asserted in the same manner as before. Thereafter, the same processing as in step (1) is performed, and the bit state of the element (3, 4) in the bit matrix storage unit 10 is rewritten from “01” to “11”.

[Step (10)] Task1 issues an ext-tsk system call for stopping itself. At this time, the element (3, 1) of task1 on the bit matrix storage unit 10 is changed from the execution state of “11” to the stop state of “00”. At the same time, PRIR0 of the priority register 76 is cleared. This outputs a self-clear signal to the selector 83, and the CPU 0
Interrupt is asserted.

[Step (11)] Task2 issues an ext-tsk system call for stopping itself. At this time, the element (3, 4) of task2 on the bit matrix storage unit 10 is changed from “11” to “00”.
Transition to. At the same time, the PRIR of the priority register 76
Clear 1 This clear signal is output through the selector 83, and the CPU1 interrupt is asserted.

<Effect of Specific Example 5> As described above, in this specific example, the stopped state and the executable state of each task are stored in the storage circuit storing the priority of each task and the information indicating the priority order. Includes information that distinguishes between waiting and running states.
Therefore, even for interrupts to a plurality of CPUs, hardware information is generated by refining the state information in the bit matrix storage unit and integrating information on which task is executing which CPU. Can control the execution order of tasks. As a result, the CP on which the lower priority task is running
It becomes possible to dispatch to U. Therefore, even in the multiprocessor format, the schedule processing as described in the first embodiment can be executed.

As described above, the present invention can be widely used for embedded CPUs requiring high throughput. Further, in each of the above specific examples, description has been made assuming an MPU, but any other digital signal processor can be used as long as it is a processor for executing a program. Further, the present invention can be easily implemented by changing semaphore processing by changing the processing of the event flag.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a real-time OS device according to a first embodiment.

FIG. 2 is an explanatory diagram of a configuration example of a general ready queue.

FIG. 3 is a diagram illustrating a configuration example of a general wait queue.

FIG. 4 is a block diagram of a real-time OS device according to a first embodiment;

FIG. 5 is a block diagram of a stack pointer address generation circuit.

FIG. 6 is an explanatory diagram of a configuration of a stack pointer table.

FIG. 7 is an explanatory diagram of the initial assignment status of tasks.

FIG. 8 is a diagram illustrating the contents of each task and the execution order of the tasks.

FIG. 9 shows a system call slp-tsk (t
It is a timing chart of ask0-id).

FIG. 10 is an explanatory diagram of a hardware configuration of a general interrupt controller.

FIG. 11 is an explanatory diagram of a processing example of an interrupt handler.

FIG. 12 is a block diagram of a bit matrix storage unit according to a specific example 2.

FIG. 13 is an explanatory diagram of the initial assignment status of interrupts.

FIG. 14 is a timing chart of interrupt processing.

FIG. 15 is an explanatory diagram of a configuration example of a general event flag queue.

FIG. 16 is an explanatory diagram of an example of using an event flag.

FIG. 17 is a block diagram of event flag hardware.

FIG. 18 is an explanatory diagram of an example of assignment of event flag information on a work memory.

FIG. 19 is a hardware block diagram of a cyclically activated handler.

FIG. 20 is a diagram illustrating the configuration of a cyclically activated handler queue.

FIG. 21 is a block diagram of periodic activation hardware.

FIG. 22 is an explanatory diagram of an example of allocation of cyclically activated handler information on a work memory.

FIG. 23 is a block diagram of a modification of the real-time OS device.

FIG. 24 is a block diagram of a main part of a real-time OS device according to a fifth embodiment;

FIG. 25 is a block diagram of a stack pointer address generation circuit of the device of the fifth embodiment.

FIG. 26 is an explanatory diagram of the initial assignment status of tasks.

FIG. 27 is an explanatory diagram of the execution order of tasks on each CPU.

FIG. 28 is a timing chart from an encoder to a CPU interrupt.

FIG. 29 is a diagram illustrating switching of modes and timing of a CPU.

FIG. 30 shows a system call “sta-tsk (task3)”.
It is a timing chart of -id) operation | movement.

FIG. 31 shows a system call ext-tsk (task0
It is a timing chart of -id).

[Explanation of symbols]

 10 bit matrix storage unit 11 address register 12 priority encoder 13 priority register 14 comparator 15 decoder 16 flip-flop 17 OR gate 18 multiplexer 20 stack pointer address generation circuit

Claims (8)

[Claims] 1. A storage circuit for storing information indicating the priority of each task to be scheduled and a priority order, and a task priority and a priority order of the tasks stored in the storage circuit. A circuit for reading the priority of the task having the highest priority, a circuit for comparing the priority of the task read and the priority of the task being executed, and a circuit for reading the priority which is higher than the priority of the task being executed. An interrupt signal output circuit including a circuit that outputs an interrupt signal for task switching to the processor when the priority is high; a priority of the task read from the storage circuit; and a corresponding priority stored in the storage circuit. A stack pointer that accepts the priority of tasks with higher priority among tasks and generates a stack pointer address used for task switching. Real-time OS apparatus characterized by comprising a circuit for generating address. 2. The real-time OS device according to claim 1, wherein the stack pointer address generation circuit receives the current priority of the task being executed from the interrupt signal output circuit, and receives the current priority of the task being executed. A save stack pointer address is generated and output. When a save completion signal is input from the processor, the next priority of the task newly read from the storage circuit is accepted, and the stack pointer address of the newly executed task is changed. A real-time OS device comprising a signal synthesizing circuit for generating and outputting. 3. The real-time OS device according to claim 1, wherein the priorities of the tasks saved immediately before or the tasks that have transited to the waiting state are retained by priority, and the priority of each task and the priority of each task are retained. A queue control circuit that masks a part of the priority line bit read from the storage circuit storing the information indicating the different order and selects a task at the head of the queue with the same priority as a task to be executed next; A real-time OS device. 4. The real-time OS device according to claim 1, wherein an interrupt signal is stored in a storage circuit storing information indicating the priority of each task and the priority order. 5. The real-time OS device according to claim 1, wherein an interrupt signal and an enable bit indicating the validity of the interrupt signal are stored in a storage circuit storing information indicating the priority of each task and the order of priority. A real-time OS device, characterized in that it is made to operate. 6. The real-time OS device according to claim 1, wherein when there is a task in an event flag waiting state, a memory for storing event flag information including a current flag pattern and a waiting flag pattern for each task. A circuit for comparing the current flag pattern with the wait flag pattern, and when the current flag pattern and the wait flag pattern match, the priority and priority of each task are shifted to the executable state. A real-time OS device, comprising: a circuit for rewriting data in a memory circuit storing information indicating a rank order; and a circuit for outputting a write address. 7. The real-time OS device according to claim 1, wherein when there is a cyclically activated handler, a memory for storing cyclically activated handler information including a remaining time and a cyclic time for each handler; A circuit that compares the time with the cycle time, and, when the current flag pattern and the wait flag pattern match, indicates the priority and priority order of each task so that the corresponding cyclically activated handler is shifted to the executable state. A real-time OS device comprising a circuit for rewriting data in a storage circuit storing information and a circuit for outputting a write address. 8. The real-time OS device according to claim 1, wherein each of the tasks has a stop state, an executable state, a wait state, and an execution state in a storage circuit storing information indicating the priority of each task and the order of priority. A real-time OS device including information for distinguishing from a state.