JP2001069372A - Dc clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC clamp circuit where the input conversion range of DC fluctuation, which is contained in an analog signal, is not narrowed even if the amplification rate of an analog signal is changed and the follow-up ability of a DC clamp is not changed at the time of A/D-converting an analog signal containing DC. SOLUTION: The circuit has an adder 1, a first amplification circuit 2, an A/D converter 3, a comparator 4, a D/A converter 5, a switch 6, an integrator 7 and a second amplification circuit 8. The first amplification circuit 2 and the second amplification circuit 8 can independently set an amplification rate by gain control values CONT 1 and CONT 2. At the time of setting the amplification rate of the first amplification circuit 2, the amplification rate of the second amplification circuit 8 can be set by depending on the amplification set rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC clamp circuit for fixing the DC level of an analog signal containing a DC component, such as a video signal, to a predetermined level when the analog signal is A / D converted. And a DC clamp circuit in which the frequency band is constant even if the gain changes.

[0002]

2. Description of the Related Art Conventionally, when a video signal as shown in FIG. 8A is A / D converted by an A / D converter, the DC level in the video signal is clamped to a constant value by a DC clamp circuit. There is a need to. For this clamp, a clamp pulse as shown in FIG. 8B generated based on the video signal is used. The video signal whose DC level is clamped in this manner is amplified so as to be within the dynamic range of the A / D converter, and then A / D converted by the A / D converter.

In such a DC clamp circuit, it is desired that the DC level (DC level) of the video signal does not fluctuate. As a conventional technique for realizing this, an invention described in US Pat. No. 4,473,846 is disclosed. The invention described in Japanese Patent No. 4970594 is known.

[0004]

However, in the invention described in U.S. Pat. No. 4,473,846, the stability of the loop due to the difference in the amplification factor of the amplifier circuit (amplifier) is not considered at all. In addition, since the gain of the loop increases as the gain of the amplifier circuit increases, it is necessary to set the loop constant (specifically, the integrator constant) to be stable at the maximum gain. For this reason, there is an inconvenience that when the gain is small, the follow-up performance of the loop is slow.

In the invention disclosed in Japanese Patent No. 4970594, the DC clamp loop is formed at a stage subsequent to the gain amplifier. For this reason, the frequency band of the loop is constant irrespective of the gain, but the amount of change in the DC level is also amplified, so that the allowable range of the change in the DC level is limited by input conversion, or it takes a long time to converge. There are inconveniences.

Therefore, an object of the present invention is to provide an analog-to-digital converter that includes an analog signal including a direct current component. An object of the present invention is to provide a DC clamp circuit that does not narrow down and does not change the followability of the DC clamp.

[0007]

Means for Solving the Problems In order to solve the above problems and achieve the object of the present invention, each of the inventions according to claims 1 to 5 is configured as follows. That is, claim 1
The invention described in (1) is an adding means for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal, and a first means for amplifying an output of the adding means.
Amplifying means, A / D converting means for A / D converting the output of the first amplifying means and outputting the result as an output signal, comparing means for comparing the output of the A / D converting means with a predetermined value;
An integrating means for integrating an output of the comparing means during an output period of the enable signal; and a second amplifying means for amplifying an output of the integrating means and feeding the output back to the adding means as the feedback signal. The means and the second amplifying means are capable of independently setting an amplification factor. When setting the amplification factor of the first amplifying means, the amplification factor of the second amplifying means depends on the set amplification factor. Is set.

According to a second aspect of the present invention, there is provided an adding means for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal, and a first amplifier for amplifying an output of the adding means. A means for A / D converting the output of the first amplifying means and outputting this as an output signal
/ D converting means, comparing means for comparing the output of the A / D converting means with a predetermined value, D / A converting means for D / A converting the output of the comparing means, and output of the D / A converting means Is integrated during the output period of the enable signal, and integrating means for feeding back the integrated value as the feedback signal to the adding means is provided. The amplification factor of the first amplifying means and the D / A of the D / A converting means are provided. The reference level for the A-conversion can be set independently of each other. When setting the amplification factor of the first amplification unit, the reference level of the D / A conversion unit is set depending on the set amplification factor. It is characterized by doing so.

According to a third aspect of the present invention, there is provided an amplifying means for adding an input analog signal including a direct current component and a feedback signal for clamping the input analog signal, and amplifying the added value, and the amplifying means. A / D conversion means for A / D converting the output of the A / D converter and outputting the converted signal as an output signal; comparison means for comparing the output of the A / D conversion means with a predetermined value; Integrating means for integrating during an output period and feeding back the integrated value to the amplifying means as the feedback signal, wherein the amplifying means processes the input analog signal depending on a set amplification factor; The integrated value from the means is processed independently of the set amplification factor.

According to a fourth aspect of the present invention, there is provided an adding means for adding an input analog signal including a direct current component and a feedback signal for clamping the input analog signal, and A / D converting the output of the adding means. A / D conversion means for outputting the output as an output signal, comparison means for comparing the output of the A / D conversion means with a predetermined value, and D / A conversion means for D / A converting the output of the comparison means. Integrating means for integrating the output of the D / A conversion means during the output period of the enable signal, and feeding back the integrated value to the addition means as the feedback signal. The level is inversely proportional to the amplification factor set by the adding means,
Further, the adding means processes the input analog signal based on a set gain, and processes the integrated value from the integrating means independently of the set gain. Things.

According to a fifth aspect of the present invention, in the DC clamp circuit of the first, second, third or fourth aspect, the input analog signal is a video signal and the enable signal is It is a clamp pulse generated from the input analog signal.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the first embodiment of the DC clamp circuit of the present invention. As shown in FIG. 1, the DC clamp circuit according to the first embodiment includes an adder 1 serving as an adder, a first amplifier 2 serving as a first amplifier, and an A / D converter serving as an A / D converter. A D converter 3, a comparator 4 as comparison means,
An A / A converter 5, a switch 6, an integrator 7 as an integrating means, and a second amplifier circuit 8 as a second amplifying means are provided.

Further, in the DC clamp circuit according to the first embodiment, the first amplifier circuit 2 and the second amplifier circuit 8
The gain can be set independently by the gain control values CONT1 and CONT2. When setting the gain of the first amplifier circuit 2, the gain of the second amplifier circuit 8 is set depending on the set gain. It is like that. Specifically, assuming that the gain of the first amplifier circuit 2 is G1 and the gain of the second amplifier circuit 8 is G2, each gain is set so that G1 × G2 = constant. is there.

The adder 1 adds an analog signal including a DC component such as a video signal and a feedback signal output from the second amplifier circuit 8 to clamp the analog signal, and adds the added value to a fourth signal. The signal is output to one amplifier circuit 2. The first amplifier circuit 2 amplifies the addition signal output from the adder 1 and outputs the amplified signal to the A / D converter 3.

The A / D converter 3 A / D converts an analog output signal from the first amplifier circuit 2 into a digital signal consisting of predetermined bits, and uses the A / D converted digital signal as an output signal. Output to the output terminal and output to the comparator 4 at the same time. The comparator 4 has an A / D
The digital signal output from the converter 3 is compared with a predetermined set value in a digital form, and a digital signal corresponding to the comparison is output.

Here, the predetermined set value is a value for setting an A / D conversion value (output of the A / D converter 3) of a DC component included in an analog signal when a clamp loop described later is formed. Is a value determined by D / A converter 5
Is configured to D / A convert a digital signal from the comparator 4 into an analog signal and output the analog signal to the integrator 7. The switch 6 is connected between the output side of the D / A converter 5 and the integrator 7.
The contact is openable and closable by an enable signal.

The integrator 7 integrates the output signal from the D / A converter 5 when the contact of the switch 6 is closed by the enable signal, and outputs the integrated value to the second amplifier circuit 8. Has become. The second amplifying circuit 8 receives and amplifies the output of the integrator 7 and outputs the amplified signal to the adder 1 as the above-mentioned feedback signal. Next, the operation of the DC clamp circuit according to the first embodiment having such a configuration will be described.
This will be described with reference to FIG.

When the enable signal for opening and closing the switch 6 is set at "H" level, the switch 6 is closed to form a clamp loop. At this time, adder 1
When an analog signal including a DC component such as a video signal is input to the adder 1, the analog signal and a feedback signal output from the second amplifier circuit 8 for clamping the analog signal are added by the adder 1. The added signal is the first amplifier circuit 2
Is output to

The first amplifier circuit 2 amplifies the added signal and outputs the amplified signal to the A / D converter 3. In the A / D converter 3, the output of the first amplifying circuit 2 is A / D converted into a digital signal of a predetermined bit, and the digital signal is output to the output terminal as an output signal, and is also output to the comparator 4. You. In the comparator 4, the digital signal is compared with a set value, and the comparison result is output to the D / A converter 5 as a digital signal. The D / A converter 5 D / A converts the digital signal into an analog signal. Since the switch 6 has its contact closed when the clamp loop is formed, the integrator 7 integrates the analog signal output from the D / A converter 5 during the closed state. The output signal of the integrator 7 is amplified by the second amplifier circuit 8 and fed back to the adder 1.

With such an operation, while the enable signal for forming the clamp loop is at the "H" level,
The difference between the set value of the comparator 4 and the A / D converted value of the A / D converter 3 becomes zero, and the output of the integrator 7 converges to a predetermined value. As described above, in the DC clamp circuit according to the first embodiment, the first amplifier circuit 2 and the second amplifier circuit 8 include the gain control values CONT1 and CONT.
2, the gain can be set independently of each other. When setting the gain of the first amplifier circuit 2, the gain of the second amplifier circuit 8 is set depending on the set gain. For this reason, in the first embodiment, even if the amplification factor of an input analog signal including a DC component such as a video signal is changed, the input conversion range for the DC variation is not narrowed, and the followability of the DC clamp is reduced. does not change.

Next, a DC clamp circuit according to a second embodiment of the present invention will be described with reference to FIG. The DC clamp circuit according to the second embodiment is the DC clamp circuit of FIG.
The A / A converter 5 is replaced with a D / A converter 5A shown in FIG. 2, and the first amplifier circuit 2 and the second amplifier circuit 8 independently set gains by gain control values CONT1 and CONT2. In addition, the D / A converter 5A is capable of independently setting a reference level for D / A conversion.

Further, in the second embodiment, when setting the amplification factor of the first amplification circuit 2, the amplification factor of the second amplification circuit 8 and the D / A converter 5A depend on the set amplification factor. To set the reference level. Specifically, the gain of the first amplifier circuit 2 is G1, the gain of the second amplifier circuit 8 is G2,
Assuming that the reference level RL of the D / A converter 5A is G1 × G
Each value was set so that 2 × RL = constant.

The structure of another part of the second embodiment is shown in FIG.
Therefore, the same reference numerals are given to the same parts, and the description thereof will be omitted. The operation of the second embodiment is basically the same as the operation of the first embodiment, and the description of the operation is omitted here.
According to the DC clamp circuit according to the second embodiment having the above-described configuration, the same effect as that of the first embodiment can be obtained.

In the second embodiment, the second amplifier circuit 8 is provided, but the second amplifier circuit 8 is not always necessary and can be omitted. In this case, when setting the gain of the first amplifier circuit 2, the reference level of the D / A converter 5A is set depending on the set gain. Next, a DC clamp circuit according to a third embodiment of the present invention will be described with reference to FIG.

In the DC clamp circuit according to the third embodiment, the adder 1, the first amplifier circuit 2, and the second amplifier circuit 8 shown in FIG. 1 are embodied by an amplifier circuit 11, as shown in FIG. Since the configuration of the other parts is the same as that of FIG. 1, the same parts are denoted by the same reference numerals and description thereof will be omitted as appropriate. As shown in FIG. 3, the amplifier circuit 11 includes an operational amplifier (operational amplifier) 111, capacitors 112, 113, 114, and switches 115 to 12
1 is comprised.

More specifically, an input terminal to which an analog signal such as a video signal Vi is input is connected to the switch 11.
5 and a capacitor 112 are connected to the inverting input terminal (− terminal) of the operational amplifier 111. A switch 116 and a capacitor 113 connected in series are connected in parallel to both ends of the switch 115 and the capacitor 112 connected in series. The common connection between the switch 115 and the capacitor 113 is connected to the operational amplifier 11 through the switch 117.
1 output terminal. The common connection between the switch 116 and the capacitor 113 is grounded via the switch 118.

The output Vint of the integrator 7 is
The signal is input to the inverting input terminal of the operational amplifier 111 via 0 and the capacitor 114. The common connection between the switch 120 and the capacitor 114 is the switch 1
21 is grounded. The non-inverting input terminal (+ terminal) of the operational amplifier 111 is grounded. Further, between the output terminal of the operational amplifier 111 and the non-inverting input terminal,
The switch 119 is connected. Further, the output Vo of the operational amplifier 111 is output to the A / D converter 4.

The capacity of the capacitor 112 is n × C, where n is a set gain (set amplification factor) of the operational amplifier 111.
It is assumed that the set gain n has a relationship of 0 <n ≦ 1. The capacitance of the capacitor 113 is (1-
n) × C. Further, the capacitor 11
The capacity of No. 4 is n × C ′. Switches 115, 11
The contacts 6, 119 and 120 are controlled to open and close by the sample pulse S1, and when the sample pulse S1 is at the "H" level, the contacts are closed. The contacts of the switches 117, 118, and 121 are controlled to open and close by a hold pulse S2. When the hold pulse S2 is at "H" level, the contacts are closed. The contact of the switch 6 is controlled to open and close by a clamp pulse, and the contact is closed when the clamp pulse is at “H” level.

Next, the operation of the DC clamp circuit according to the third embodiment having such a configuration will be described with reference to FIGS. First, regarding the operation of the amplifier circuit 11,
This will be described using mathematical expressions. As shown in FIG.
The video signal input to 1 is Vi, the output voltage of the amplifier circuit 11 is Vo, and the output of the integrator 7 is Vint. The charge Q at the non-inverting input terminal of the operational amplifier 111 is expressed by the following equation (1) during a sample period (sample phase) in which the contacts of the switches 115, 116, 119, and 120 are closed. Hold period (hold phase) when each contact of 121 is closed
Then, the following equation (2) is obtained.

Q = (1−n) × C × (−Vi) + n × C × (−Vi) + n × C ′ × Vint (1) Q = n × C × (−Vo) (2) and Since the charge Q is the same in the sample phase and the hold phase, the following equation (3) holds when equation (1) = (2).

Vo = (Vi / n) −Vint × (C ′ / C) (3) where n in the equation (3) is a set gain (set gain) of the amplifier circuit 11. From equation (3), amplifier circuit 1
The output voltage Vo of 1 includes an input video signal Vi that depends on the set gain n, and an output Vint of the integrator 7 that does not depend on the set gain n but depends on the gain (C ′ / C) of the clamp loop. .

Therefore, in the DC clamp circuit according to the third embodiment, the gain (C '/ C) of the clamp loop
Is appropriately selected, a clamp loop having a constant frequency band can be formed without depending on the set gain n. Next, the overall operation of the DC clamp circuit according to the third embodiment will be described with reference to FIGS.

Now, a video signal Vi as shown in FIG. 4A is input to the amplifier circuit 11, and when the clamp pulse goes to "H" level at time t1 as shown in FIG. The contact of the switch 6 is closed only for the period T1 of the "level", and a clamp loop is formed. In the period T1, the “H” level of the sample pulse S1 and the “H” level of the hold pulse S2 are alternately repeated. Therefore, when the sample pulse S1 is at the "H" level, the contacts of the switches 115, 116, 119, and 120 are closed, and the capacitors 112 and 113 are charged to a voltage corresponding to the video signal Vi, while the capacitors are charged. 1
14 is charged to a voltage corresponding to the output of the integrator 7.

On the other hand, when the hold pulse S2 is at "H" level, the switches 115, 116, 119 and 120
Are opened, and the switches 117, 118, 1
21 are closed, the capacitors 112 and 11 are closed.
3 and the potential of the capacitor 114 are
And the added signal is output to the A / D converter 3.

In the A / D converter 3, the added signal is A / D converted into a digital signal of a predetermined bit, and the digital signal is output to an output terminal as an output signal.
It is output to the comparator 4. In the comparator 4, the digital signal is compared with a set value, and the comparison result is output to the D / A converter 5 as a digital signal. The D / A converter 5 D / A converts the digital signal into an analog signal. As described above, when the crank pulse is at the "H" level, the contact of the switch 6 is closed. Therefore, the analog signal output from the D / A converter 5 during the closed period T1 is output from the integrator 7 Is integrated.

By the above operation, during the period T1 in which the clamp loop is formed, the difference between the set value of the comparator 4 and the A / D converted value of the A / D converter 3 becomes zero. As a result, the output Vint of the integrator 7 converges to a predetermined value as shown in FIG. By the way, the frequency of the sample pulse S1 and the frequency of the hold pulse S2 are several tens MHz.
Since the frequency of the clamp pulse is several KHz, the enlarged waveform of each part in the period T2 in FIG. 4 is as shown in FIG.

In a period T2 in FIG. 4, as shown in FIG. 5B, in a period T3 in which the sample pulse S1 is at the "H" level, the contacts of the switches 115, 116, 119 and 120 are closed. . At this time, the capacitors 112, 1
13 is charged with a charge corresponding to the video signal Vi shown in FIG. 5A. At this time, since the output of the integrator 7 does not change, the charging voltage of the capacitor 114 remains fixed. Therefore, during the period T3, the output voltage Vo of the amplifier circuit 11 (the operational amplifier 111) is
The voltage obtained by adding the charging voltages of the capacitors 2 and 113 and the charging voltage of the capacitor 114 becomes a voltage, and the waveform is as shown in FIG.

On the other hand, during the period T4 when the hold pulse S2 is at the "H" level, the switches 115, 116, 119, 1
20 contacts are opened, and switches 117 and 11
The contacts 8 and 121 are closed. At this time, the output voltage Vo of the amplifier circuit 11 is maintained at a voltage obtained by adding the voltages of the capacitors 112 and 113 and the voltage of the capacitor 114 as shown in FIG.

As described above, in the DC clamp circuit according to the third embodiment, as can be seen from the equation (3), the output voltage Vo of the amplifier circuit 11 is different from the input video signal Vi depending on the set gain n, The output Vint of the integrator 7 depends on the gain (C '/ C) of the clamp loop without depending on the set gain n. Therefore, in the DC clamp circuit according to the third embodiment, if the gain (C ′ / C) of the clamp loop is appropriately selected, the clamp loop having a constant frequency band without depending on the set gain n of the amplifier circuit 11 can be formed. Can be configured.

Next, a DC clamp circuit according to a fourth embodiment of the present invention will be described with reference to FIG. The DC clamp circuit according to the fourth embodiment includes an adder 1, a first amplifier circuit 2, a D / A converter 5A, and a second amplifier circuit 8 shown in FIG. 31,
This is embodied by a current output type D / A converter 32, an integrator 7 composed of an operational amplifier 71 and a capacitor 71, and the like. The other parts are the same as those shown in FIG. The same reference numerals are given and the description thereof will be omitted as appropriate.

As shown in FIG. 6, the adder circuit 31 comprises an operational amplifier 311 and resistors 312 to 314. That is, the video signal Vi is input to the inverting input terminal (−terminal) of the operational amplifier 31 via the resistor 312, and at the same time, the output of the integrator 7 is input via the resistor 313. The non-inverting input terminal of the operational amplifier 311 is grounded. A feedback resistor 314 is provided between the output terminal of the operational amplifier 311 and the inverting input terminal.
Is connected.

Here, the resistance value of the resistor 312 is R,
Assuming that the resistance value of the resistor 13 is R ′ and the resistance value of the resistor 314 is n × R, the gain set for the video signal Vi by the adding circuit 31 is (n × R) / R. Further, the gain set for the output Vint of the integrator 7 of the adder circuit 31 is (n × R) /
R ′, and the output Vint of the integrator 7 depends on the set gain.

However, the input to the integrator 7, that is, the output of the current output type D / A converter 32 depends on the set gain n. That is, the current output type D / A
The converter 32 includes a reference current generation circuit 33 that generates its own reference current (Iref). As shown in FIG. 6, the reference current generation circuit 33 includes an operational amplifier 331,
It comprises a resistor 332 having a resistance value of n × R, and PMOS transistors 333 and 334.

More specifically, the operational amplifier 331 includes:
The reference voltage Vref is supplied to the inverting input terminal, and the non-inverting input terminal is grounded via the resistor 332.
The output terminal of the operational amplifier 331 is connected to each gate of the PMOS transistors 333 and 334. MO
The source of the S transistor 333 is connected to the power supply, and the drain is connected to the non-inverting input terminal of the operational amplifier 331. The source of the MOS transistor 334 is connected to the power supply, and the drain is connected to the current output type D / A converter 32.
, A reference current of Iref = Vref / (n × R) is supplied.

The output level of the current output type D / A converter 32 thus configured is inversely proportional to the set gain n. As a result, the output Vo of the addition circuit 31
Is as shown in the following equation (4). Vo = n × Vi−α × (R / R ′) × Vint (4) where α in the expression (4) is determined by the amount of the reference current Iref and the capacitance of the capacitor 72 of the integrator 7. An arbitrary coefficient determines the gain (amplification factor) of the clamp loop.

From equation (4), the output Vo of the adder circuit 31 is
The input video signal Vi that depends on the set gain n and the gain α × (R
/ R ') depending on the output Vint of the integrator 7. Therefore, in the fourth embodiment, if α × (R / R ′) of the clamp loop is appropriately selected, a clamp loop having a constant frequency band can be configured without depending on the set gain.

Next, the operation of the DC clamp circuit according to the fourth embodiment having such a configuration will be described with reference to FIGS.
This will be described with reference to FIG. Now, the video signal Vi as shown in FIG. 7A is input to the adder 31, and when the clamp pulse goes to the “H” level at time t1 as shown in FIG. The contact of the switch 6 is closed only for the period T1.

In the period T1, the video signal Vi and the output Vint of the integrator 7 are added and amplified at the same time by the adding circuit 31, and the amplified output Vo as shown in FIG. Is obtained. In the A / D converter 3, the output Vo of the adding circuit 31 is A / D converted into a digital signal of a predetermined bit, and the digital signal is output as an output signal to an output terminal, and at the same time, is output to the comparator 4. You.

The comparator 4 compares the digital signal with a set value, and compares the comparison result with the current output type D
/ A converter 32. Current output type D / A converter 3
At 2, the digital signal is D / A converted to an analog signal. As described above, when the clamp pulse is at the “H” level, the switch 6 closes its contact. Therefore, during the period T1 of the closed state, the switch 6 outputs the current output type D / A converter 3.
The analog signal output from 2 is integrated by the integrator 7.

By such an operation, during the period T1 in which the clamp pulse for forming the clamp loop is at the "H" level, the difference between the set value of the comparator 4 and the A / D converted value of the A / D converter 3 is obtained. Becomes zero, and the output Vint of the integrator 7 converges to a predetermined value as shown in FIG. 7D. As described above, in the DC clamp circuit according to the fourth embodiment, as shown in equation (4), the output Vo of the adder circuit 31 includes the input video signal Vi depending on the set gain n and the set gain , And the output Vint of the integrator 7 which depends on the gain α × (R / R ′) of the clamp loop without depending on. Therefore, in the DC clamp circuit according to the fourth embodiment, α ××
If (R / R ') is appropriately selected, a clamp loop having a constant frequency band can be formed without depending on the set gain.

In the above embodiment, for example,
When the amplifier circuit 11 is realized with a capacitance ratio as in the third embodiment, a first stage (rough stage) for performing a relatively coarse gain step and a second stage (fine stage) for performing a relatively fine gain step ) To form a programmable gain amplifier. In this case, as a method of realizing gain control on the integrator side, the first stage is a capacitance ratio as in the third embodiment, and the second stage is a D / A conversion as in the fourth embodiment. Fine adjustment of the reference level of the vessel may be performed.

[0052]

As described above, according to the first aspect of the invention, the first amplifying means and the second amplifying means can set the amplification factors independently of each other. At this time, the amplification factor of the second amplification means was set depending on the set amplification factor. For this reason, according to the first aspect of the present invention, even when the amplification factor of the analog signal is changed during the A / D conversion of the analog signal including the DC component, the input conversion range of the DC fluctuation included in the analog signal is changed. The effect is obtained that the width is not narrowed and the followability of the DC clamp does not change.

Further, in the invention according to claim 2, the amplification factor of the first amplifying means and the reference level for D / A conversion of the D / A converting means can be set independently of each other. When the amplification factor is set, the reference level of the D / A conversion means is set depending on the set amplification factor. Therefore, the same effect as the first aspect can be obtained.

Further, in the invention according to claim 3, the amplifying means processes the input analog signal based on the set gain, and processes the integrated value from the integrating means independently of the set gain. Therefore, the same effect as the first aspect can be obtained. Further, in the invention according to claim 4, the D / A converter has an output level which is inversely proportional to a set gain of the adder, and the adder has an output level based on the set gain for the input analog signal. And the integrated value from the integrating means is processed independently of the set gain, so that the same effect as the invention according to claim 1 can be obtained.

Further, in the invention according to claim 5, since the present invention is applied to a video signal, the A of the video signal is used.
In the / D conversion, even if the amplification factor of the video signal is changed, the input conversion range for the DC fluctuation included in the analog signal is not narrowed, and the followability of the DC clamp is not changed. Is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a DC clamp circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of a DC clamp circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing an overall configuration of a DC clamp circuit according to a third embodiment of the present invention.

FIG. 4 is a waveform chart of each part in FIG. 3;

FIG. 5 is an enlarged waveform diagram of a part of FIG. 4;

FIG. 6 is a block diagram illustrating an overall configuration of a DC clamp circuit according to a fourth embodiment of the present invention.

FIG. 7 is a waveform chart of each part in FIG. 6;

FIG. 8 is a waveform chart for explaining a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 adder 2 first amplifier circuit 3 A / D converter 4 comparator 5, D / A converter 5A D / A converter 6 switch 7 integrator 8 second amplifier circuit 11 amplifier circuit 31 adder 32 current output type D / A converter 33 Reference current generation circuit

Claims (5)

[Claims] An adder for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal; a first amplifier for amplifying an output of the adder; A / D conversion means for A / D converting the output of the means and outputting the output as an output signal; comparison means for comparing the output of the A / D conversion means with a predetermined value; And a second amplifying means for amplifying the output of the integrating means and feeding it back to the adding means as the feedback signal. The first amplifying means and the second amplifying means The gain can be set independently of each other, and when setting the gain of the first amplifying means, the gain of the second amplifying means is set depending on the set gain. Characteristic DC class Pump circuit. 2. An adding means for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal, a first amplifying means for amplifying an output of the adding means, and a first amplifying means. A / D conversion means for A / D converting the output of the means and outputting this as an output signal; comparison means for comparing the output of the A / D conversion means with a predetermined value; D / A conversion means for A-to-A conversion, and integration means for integrating the output of the D / A conversion means during the output period of the enable signal, and feeding back the integrated value to the addition means as the feedback signal, The amplification factor of the first amplification means and the D / A conversion means
The reference level for / A conversion can be set independently of each other. When setting the amplification factor of the first amplifying means,
A DC clamp circuit wherein a reference level of the D / A conversion means is set depending on the set amplification factor. 3. Amplifying means for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal, and amplifying the added value, and A / D converting the output of the amplifying means. A / D conversion means for outputting the output as an output signal, comparison means for comparing the output of the A / D conversion means with a predetermined value, and integrating the output of the comparison means during the output period of the enable signal; Integrating means for feeding back the integrated value to the amplifying means as the feedback signal, wherein the amplifying means processes the input analog signal based on a set amplification factor, and sets the integrated value from the integrating means. A DC clamping circuit characterized in that it is processed independently of the amplification factor. 4. An adding means for adding an input analog signal including a DC component and a feedback signal for clamping the input analog signal, A / D converting an output of the adding means, and outputting this as an output signal. A / D conversion means for performing the operation, comparison means for comparing the output of the A / D conversion means with a predetermined value, D / A conversion means for performing D / A conversion on the output of the comparison means, and D / A conversion means And an integrating means for integrating the output value of the output signal during the output period of the enable signal and feeding back the integrated value to the adding means as the feedback signal. The D / A converting means has an output level set by the adding means. The adding means processes the input analog signal based on a set gain, and processes the integrated value from the integrating means independently of the set gain. DC clamp circuit, characterized in that is made as to. 5. The input signal according to claim 1, wherein the input analog signal is a video signal, and the enable signal is a clamp pulse generated from the input analog signal. Item 6. A DC clamp circuit according to Item 4.