JP2001069001A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit where a lock time can be reduced and a circuit to reduce the lock time does not give effect on the operation and the stability in the case of locking. SOLUTION: A phase comparator section 31 detects a phase difference between an input signal and an output signal of a voltage controlled oscillator 3, and when a detected phase difference is 360-degrees or blow, the phase comparator section 31 outputs an UP request signal UP to increase an oscillated frequency of the voltage controlled oscillated 3 or a DOWN request signal DW to decrease the oscillated frequency in response to the phase difference. This signal is used to gradually charge/discharge a capacitor included in a loop filter 32 and outputs its charge/discharge voltage to the voltage controlled oscillator 3. When the detected phase difference is 360-degrees or over, on the other hand, the phase comparator section 31 outputs UP request signals UP1,... or DOWN request signals DW1,... in response to the phase difference and this signal is used to rapidly charge/discharge the capacitor included in the loop filter 32 and outputs its charge/discharge voltage to the voltage controlled oscillator 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL which can be applied to various fields such as a motor speed control and a frequency synthesizer.
(Phase-Locked Loop) circuit,
A PL that is particularly stable and can reduce lock time
It relates to the L circuit.

[0002]

2. Description of the Related Art As a conventional PLL circuit of this type, a circuit as shown in FIG. 5 is known. This PLL
As shown in FIG. 5, the circuit includes a phase comparison circuit 1, a loop filter 2, and a voltage controlled oscillator 3. As shown in FIG. 6, the phase comparison circuit 1 has four R-
It comprises S flip-flops 11 to 14, a 4-input NAND gate 15, and four inverters 16 to 19. More specifically, the phase comparison circuit 1 has a R
The -S flip-flop 11 detects the rising of the input signal IN, the RS flip-flop 12 detects the rising of the output signal OUT of the voltage controlled oscillator 3,
When the phase of the input signal IN is ahead of the phase of the output signal OUT, the up request signal UP for increasing the frequency of the output signal OUT for a time equal to the phase difference is set to the “H” level, and conversely. When the phase of the input signal IN is behind the phase of the output signal OUT, the down request signal DW for lowering the frequency of the output signal OUT for a time equal to the phase difference is set to the “H” level. It has become.

[0003] As shown in FIG.
The current source 21, the switch 22 of the current source 21, the switch 23 of the current source 24, and the current source 24 are connected in series between the power supply and the ground. And switch 2
A capacitor C and a resistor R are connected in series between the common connection point where the switch 2 and the switch 23 are connected and the ground. The contact of the switch 22 is configured to be openable and closable by an up request signal UP output from the phase comparison circuit 1. The contact of the switch 23 is configured to be openable and closable by the down request signal DW.

[0004] The voltage controlled oscillator 3 is configured so that the oscillation frequency can be varied based on the output voltage of the loop filter 2. Next, the operation of the conventional PLL circuit having such a configuration will be described with reference to FIGS. The input signal IN and the output signal OUT of the voltage controlled oscillator 3 are input to the phase comparison circuit 1, the rising of the input signal IN is detected by the RS flip-flop 11, and the rising of the output signal OUT of the voltage controlled oscillator 3 is detected. Are detected by the RS flip-flop 12. When the phase of the input signal IN is ahead of the phase of the output signal OUT, the up request signal UP for increasing the frequency of the output signal OUT for a time equal to the phase difference becomes “H” level. Conversely, when the phase of the input signal IN is behind the phase of the output signal OUT, the down request signal DW for lowering the frequency of the output signal OUT for a time equal to the phase difference is at the “H” level. become.

In the loop filter 2, the up request signal U
When P becomes "H" level, the contact of the switch 22 is closed by this signal UP, so that the capacitor C is charged by the current from the current source 21. As a result, the output voltage of the loop filter 2 increases, whereby the oscillation frequency of the voltage controlled oscillator 3 increases, and reaches the target value. on the other hand,
When the down request signal DW becomes "H" level, the contact of the switch 23 is closed by this signal DW.
Discharged via 4. As a result, the loop filter 2
, The oscillation frequency of the voltage-controlled oscillator 3 decreases, and reaches the target value.

[0006] By the above feedback control,
The frequency of the input signal IN matches the frequency of the output signal OUT. By the way, in general, it is desired that the lock time is short in the PLL circuit, and a PLL circuit with a high-speed lock-up function described in Japanese Patent Application Laid-Open No. Hei 10-285024 is known as a conventional technique for realizing this.

In this PLL circuit, a charge pump has two current sources having different current values, a delay circuit is connected to an output of a phase comparison circuit, and a control signal for a switch in which the output of the delay circuit is connected to the current source. As a current source. Also, this P
The LL circuit outputs a current source having a large current value when the phase difference between the inputs of the phase comparison circuit is large, and outputs a current source having a small current value as the output current of the charge pump when the phase difference is small, thereby shortening the lock time. You can do it.

[0008]

By the way, the PLL circuit is required to have a short lock time and a high stability at the time of lock. However, in the above-mentioned conventional circuit, in order to shorten the lock time, it is necessary to increase the capacity of the current source of the loop filter. However, if the current source is increased, there is a disadvantage that stability is sacrificed. On the other hand, in order to increase the stability at the time of locking, it is necessary to reduce the capacity of the current source of the loop filter. However, if the current source is reduced, there is a disadvantage that the lock time becomes longer.

Further, in the PLL circuit described in the above-mentioned Japanese Patent Application Laid-Open No. 10-285024, the lock time can be shortened as described above. However, regardless of the presence or absence of the lock, since the delay circuit for shortening the lock time is always operating, there is a disadvantage that power is consumed even during the lock. Therefore, the present invention has been made under the above-mentioned background, and in addition to being able to shorten the lock time, a PLL for shortening the lock time does not affect the operation and stability at the time of locking. It is intended to provide a circuit.

[0010]

Means for Solving the Problems In order to solve the above-mentioned problems and achieve the object of the present invention, the inventions according to claims 1 to 3 are configured as follows. That is, claim 1
The invention described in (1) is a PLL circuit including a phase comparison unit, a control voltage generation unit, and a voltage controlled oscillator, wherein the phase comparison unit determines a phase difference between an input signal and an output signal of the voltage controlled oscillator. Is detected, and 1 is determined according to the detected phase difference.
Or outputting two or more frequency control signals, wherein the control voltage generating means performs charging / discharging at different speeds to the charger in accordance with the one or more frequency control signals, Is output to the voltage-controlled oscillator, and the voltage-controlled oscillator is characterized in that the oscillation frequency is variable according to the charging / discharging voltage.

The invention described in claim 2 is the first invention.
Wherein the phase comparing means detects a phase difference between the input signal and the output signal of the voltage controlled oscillator, and when the detected phase difference is equal to or less than 360 ° (2π), the phase comparison means detects the phase difference. Outputting a corresponding first frequency control signal;
When the detected phase difference is equal to or more than 360 °, a second frequency control signal is output in addition to the first frequency control signal according to the phase difference.

Further, according to a third aspect of the present invention, in the PLL circuit according to the second aspect, the control voltage generating means includes a plurality of current sources having different current amounts and a charge based on the plurality of current sources. A capacitor to be discharged, and when the first frequency control signal is output from the phase comparing means, a current source having a minimum current amount is selected from the current sources. When the capacitor is charged and discharged, and when the first and second frequency control signals are output from the phase comparison means, the current source having a larger current amount than the minimum current source And charging and discharging of the capacitor by the selected current sources.

In the present invention having such a configuration, when the phase difference between the input signal and the output signal of the voltage controlled oscillator is large, for example, when the phase difference is 360 ° (2π) or more, the charging of the charger is performed. Since the discharge speed can be changed abruptly and this charge / discharge voltage can be supplied to the voltage controlled oscillator, the lock time can be reduced as compared with the conventional PLL circuit. Further, according to the present invention, when the phase difference between the input signal and the output signal of the voltage controlled oscillator is 360 ° or less, the current source having the smallest current amount is selected, and the charging and discharging of the capacitor is performed by the selected current source. If the speed is changed slowly and the phase difference is 360 ° or more, both the minimum current source and the current source having a larger current amount are selected. As a result, the charging / discharging speed of the capacitor is rapidly changed, so that the circuit for shortening the lock time does not affect the operation and stability at the time of locking.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an overall configuration of a PLL circuit according to an embodiment of the present invention.
The PLL circuit according to this embodiment, as shown in FIG.
A phase comparison unit 31 as a phase comparison unit, a loop filter 32 as a control voltage generation unit, and a voltage controlled oscillator 3
It is composed of

The phase comparing section 31 includes a plurality of phase comparing circuits 3
1-0, 31-1... 31-n.
It is detected whether the phase of N is advanced or delayed with respect to the phase of the output signal OUT of the voltage controlled oscillator 33. If the phase is advanced, the frequency of the output signal OUT is determined according to the degree of advance. Request signal (frequency control signal) UP, UP1.
Alternatively, if two or more phases are output and the phase is delayed, the output signal OUT is output according to the degree of the delay.
, And one or more of the down request signals (frequency control signals) DW, DW1.

As shown in FIG. 3, the loop filter 32 includes a plurality of phase comparators 31-0, 31-1.
32-0, 32-1... 32 corresponding to
-N. Current source circuits 32-0, 32-1 ...
Are a current source 321 for charging, a switch 322 of the current source 321, and a switch 323 of a current source 324 for discharging.
And a current source 324 for discharging, which are connected in series between the power supply and the ground. Current source circuit 32
-0, 32-1... Between the common connection of the switch 322 and the switch 323 and the ground,
Are connected in series, and the capacitor C connected in series
And the voltage across the resistor R is output to the voltage controlled oscillator 3 as a control voltage.

Each of the contacts of the switch 322 of the current source circuits 32-0, 32-1,... Is configured to be openable and closable by an up request signal UP, UP1, UP2,. The current source circuits 32-0, 32-1
.. Are configured to be openable and closable by down request signals DW, DW1, DW2,.

The current source circuits 32-0, 32-1, 3
The current sources 321 and 324 of the current source circuit 2-2 have the smallest amount of current in the current source circuit 32-0, and the current amount increases as the current source circuit 32-1, the current source circuit 32-2,. The volume is configured to be large. The voltage controlled oscillator 3 is configured such that the oscillation frequency can be changed based on the output control voltage from the loop filter 32.

Next, a specific circuit configuration of the phase comparison section 31 will be described with reference to FIG. Phase comparator 31
Are a plurality of phase comparators 31-0, as shown in FIG.
31-1... Here, the phase comparison circuit 31
“−0” corresponds to the phase comparison circuit 1 shown in FIG.

As shown in FIG. 2, the phase comparison circuit 31-0 includes four RS flip-flops 41 to 44, a four-input NAND gate 45, and four inverters 46 to 49.
It is composed of The RS flip-flop 41 includes NAND gates 411 and 412, and the RS flip-flop 42 includes NAND gates 421 and 422. The RS flip-flop 43 includes NAND gates 431 and 432, and the RS flip-flop 44 includes NAND gates 441 and 442.

Further, the phase comparison circuit 31-0 will be specifically described. The input signal IN is input to the first input terminal of the NAND gate 411 via the inverter 46. Here, the input terminal of the NAND gate 411 is such that the uppermost input terminal in the figure is a first input terminal,
The second input terminal from the top is referred to as a second input terminal, and the same applies to the following other NAND gates.

The output terminal of the NAND gate 411 is connected to the first input terminal of the NAND gate 412, the first input terminal of the NAND gate 431, and the first input terminal of the NAND gate 45, respectively. The output terminal of the NAND gate 412 is connected to the second input terminal of the NAND gate 411 and to the input terminal of the inverter 47, and the output terminal of the inverter 47 outputs the up request signal UP
Is output.

The second input terminal of the NAND gate 431 is
It is connected to the output terminal of the NAND gate 432. The output terminal of the NAND gate 431 is connected to the NAND gate 4
32, a second input terminal of the NAND gate 45, and a second input terminal of the NAND gate 412. The second input terminal of the NAND gate 432 is connected to the first input terminal of the NAND gate 442, the third input terminal of the NAND gate 412, and the first input terminal of the NAND gate 422. The output terminal of the NAND gate 45 is the third terminal of the NAND gate 412.
, And a first output terminal of the NAND gate 422.

On the other hand, the output signal OUT of the voltage controlled oscillator 3
Is connected to the second gate of the NAND gate 421 via the inverter 48.
Input terminal. The output terminal of the NAND gate 421 is connected to the third terminal of the NAND gate 422.
, The second input terminal of the NAND gate 441, and the fourth input terminal of the NAND gate 45. The output terminal of the NAND gate 422 is connected to the first input terminal of the NAND gate 421 and to the input terminal of the inverter 49, so that the output terminal of the inverter 49 outputs the down request signal DW.

The first input terminal of the NAND gate 441 is
It is connected to the output terminal of the NAND gate 442. The output terminal of the NAND gate 441 is connected to the NAND gate 4
42, a third input terminal of the NAND gate 45, and a second input terminal of the NAND gate 422, respectively. Next, the phase comparison circuit 31-1
As shown in FIG. 2, an input signal delay circuit 51, an output signal delay circuit 52, and four RS flip-flops 5
3 to 56, a 4-input NAND gate 57, and two inverters 58 and 59.

The input signal delay circuit 51 delays the input signal IN by a predetermined time by three inverters 512 to 514 when the input signal IN rises, extracts the delayed signal from the AND gate 511, and extracts the delayed signal. Signal and up request signal U from the phase comparison circuit 31-0
The NAND operation with P is performed by the NAND gate 515, and the result is output.

When the output signal OUT rises, the output signal delay circuit 52 delays the output signal OUT by the inverters 522 to 524 for a predetermined time, extracts the delayed signal from the AND gate 521, and extracts the extracted delay. The NAND operation of the signal and the down request signal DW from the phase comparison circuit 31-0 is performed by the NAND gate 525, and the result is output.

The RS flip-flop 53 includes NAND gates 531 and 532 and an AND gate 533, and an up request signal U input to the AND gate 533.
The flip-flop operation is performed only when P is at “H” level, and the output is not changed when it is at “L” level. Therefore, the operation of the RS flip-flop 53 is controlled by the up request signal UP.

The RS flip-flop 54 includes NAND gates 541 and 542 and an AND gate 543, and performs the flip-flop operation only when the down request signal DW input to the AND gate 543 is at "H" level. The output is not changed when it is at the "L" level. Therefore, the operation of the RS flip-flop 54 is controlled by the down request signal DW.

The RS flip-flop 55 comprises NAND gates 551 and 552, and the RS flip-flop 56 comprises NAND gates 561 and 562. Further, the phase comparison circuit 31-1 will be specifically described. The input signal IN is directly input to the second input terminal of the AND gate 511, and the input signal IN is delayed by the three inverters 512 to 514. The signal is input to a first input terminal of the AND gate 511. An output terminal of the AND gate 511 is connected to a first input terminal of the NAND gate 515.

The up request signal UP from the phase comparison circuit 31-0 is input to the second input terminal of the NAND gate 515 and the first input terminal of the AND gate 533. An output terminal of the NAND gate 515 is connected to a first input terminal of the NAND gate 531;
The output terminal of the NAND gate 531 is connected to the AND gate 533.
Are connected to the second input terminal of

The output terminal of the AND gate 533 is connected to the first input terminal of the NAND gate 532, the first input terminal of the NAND gate 551, and the first input terminal of the NAND gate 57, respectively. The output terminal of the NAND gate 532 is connected to the second input terminal of the NAND gate 531 and to the input terminal of the inverter 58, and the output terminal of the inverter 58 outputs the up request signal UP.
1 is output.

The second input terminal of the NAND gate 551 is
It is connected to the output terminal of the NAND gate 552. The output terminal of the NAND gate 551 is connected to the NAND gate 5
52, a second input terminal of the NAND gate 57, and a second input terminal of the NAND gate 532, respectively. The second input terminal of the NAND gate 552 is connected to the first input terminal of the NAND gate 562, the third input terminal of the NAND gate 532, and the first input terminal of the NAND gate 542, respectively. The output terminal of the NAND gate 57 is connected to the NAND gate 53.
2 and a third input terminal of the NAND gate 542.
Output terminal.

On the other hand, the output signal OUT of the voltage controlled oscillator 3
Is directly input to the first input terminal of the AND gate 521, and the output signal OUT is delayed by the three inverters 522 to 524, so that the second signal of the AND gate 521
Input terminal. An output terminal of the AND gate 521 is connected to a first input terminal of the NAND gate 525.

The down request signal DW from the phase comparison circuit 31-0 is input to the second input terminal of the NAND gate 525 and the second input terminal of the AND gate 543, respectively. An output terminal of the NAND gate 525 is connected to a second input terminal of the NAND gate 541,
The output terminal of the NAND gate 541 is connected to the AND gate 543.
Are connected to the first input terminal of

The output terminal of the NAND gate 543 is connected to the third input terminal of the NAND gate 542, the second input terminal of the NAND gate 561, and the fourth input terminal of the NAND gate 57, respectively. An output terminal of the NAND gate 542 is connected to a first input terminal of the NAND gate 541 and to an input terminal of the inverter 59, and a down request signal DW is output from the output terminal of the inverter 59.
1 is output.

The first input terminal of the NAND gate 561 is
It is connected to the output terminal of the NAND gate 562. The output terminal of the NAND gate 561 is connected to the NAND gate 5.
62, a third input terminal of the NAND gate 57, and a second input terminal of the NAND gate 542. Next, the operation of the PLL circuit having such a configuration according to this embodiment will be described with reference to the time chart of FIG.

At time t1, as shown in FIG. 4A, when the input signal IN to the phase comparing section 31 changes from "L" level to "H" level, the rising of the input signal IN is compared with the phase. The RS flip-flop 41 of the circuit 31-0 detects this, and as a result, the phase comparator 31-0
Rises from "L" level to "H" level as shown in FIG. 4B.

Next, at time t2, as shown in FIG. 4A, when the input signal IN rises again, the output of the AND gate 511 becomes "H" level, and at this time, the up request signal UP becomes "H". Since the output is at the “H” level, the output of the NAND gate 515 is at the “L” level. As a result, the output of the flip-flop 53 becomes “L” level, and the up request signal UP output from the phase comparison circuit 31-1 is output.
1 is "H" from "L" level as shown in FIG.
Change to a level.

Here, as shown in FIG. 1, the phase comparator 31 includes phase comparators 31-1, 31-2... 31-n, and the phase comparators 31-2. The configuration is the same as that of the phase comparison circuit 31-1 shown. For this reason,
From time t3 to t5, an up request signal UP similar to the up request signal UP1 output from the phase comparison circuit 31-1.
2, UP3 and UP4 are phase comparison circuits 31-2 and 31-
3, 31-4.

In other words, during the period from time t1 to time t5, the output signal OUT from the voltage controlled oscillator 3 does not rise at the “L” level, and the phase difference between the input signal IN and the output signal OUT is 360 °. (2π) or more. Therefore, each time the phase difference differs by 360 °, that is, each time from time t2 to time t5, the up request signals UP1 to UP4 are output from the phase comparison circuits 31-1 to 31-4.
Are sequentially output.

As described above, the phase comparison circuits 31-0 to 31-
4 in response to the up request signals UP0 to UP4 output from the current source circuits 32-0 to 32-0 in the loop filter 32.
The contacts of the switches 322 of 32-4 are sequentially closed. Therefore, the capacitor C is charged by each current source 321 of the current source circuits 32-0 to 32-4. Here, since the current amount of the current source 321 is the smallest in the current source circuit 32-0 and increases as it goes to the current source circuits 32-1, 32-2,. As the phase difference of the output signal OUT is larger, a larger current flows through the capacitor C, the speed (rate of change) of the charging voltage can be increased, and the charging voltage can be output as the control voltage of the voltage controlled oscillator 3.

Thereafter, at time t6, as shown in FIG.
Changes from the “L” level to the “H” level, the output of the RS flip-flop 42 of the phase comparison circuit 31-0 changes from the “H” level to the “L” level. Down request signal DW output from comparison circuit 31-0 changes from "L" level to "H" level as shown in FIG. 4 (D). At this time, since the output of the NAND gate 45 changes from “H” level to “L” level, the output of the RS flip-flop 42 changes from “H” level to “L” level and immediately changes to “H” level. Return. Therefore, the down request signal DW becomes “L” level, and becomes a bar-shaped pulse as shown in FIG.

Further, at time t6, the output of NAND gate 45 changes from "H" level to "L" level as described above.
Changes from the “L” level to the “H” level. Therefore, the up request signal UP changes from “H” level to “L” level as shown in FIG. On the other hand, in phase comparison circuit 31-1, at time t6, when output signal OUT from voltage controlled oscillator 3 changes from “L” level to “H” level, down request signal input to NAND gate 525 at this time DW is "H"
Because of the level, the output of the NAND gate 525 temporarily changes from “H” level to “L” level. Therefore, the change changes the output of the NAND gate 57 via the RS flip-flop 54. As a result, the output of the RS flip-flop 53 changes from the “L” level to the “H” level, so that the up request signal UP1 is output as shown in FIG.
, The level changes from the “H” level to the “L” level.

At time t7, as shown in FIG. 4B, when the output signal OUT from the voltage controlled oscillator 3 rises again, this rising of the output signal OUT is compared with the RS flip-flop of the phase comparison circuit 31-0. 42 detects,
As a result, the down request signal DW output from the phase comparison circuit 31-0 rises from the "L" level to the "H" level as shown in FIG.

At time t8, as shown in FIG. 4B, when output signal OUT rises, AND gate 52
1 is at "H" level and the down request signal DW is at "H" level at this time.
5 is at the “L” level. As a result, the output of flip-flop 54 goes to "L" level, and down request signal DW1 output from phase comparison circuit 31-1 changes from "L" level to "H" level as shown in FIG. Change to a level.

Thereafter, at times t9 and t10, the down-up request signal DW output from the phase comparison circuit 31-1.
1 are output from the phase comparators 31-2 and 31-3, respectively (FIG. 1).
reference). In other words, during the period from time t7 to time t10, input signal IN remains at the “L” level, and the phase difference between input signal IN and its output signal OUT is 360 °.
(2π) or more. Therefore, the down request signals DW1 to DW3 are sequentially output from the phase comparison circuits 31-1 to 31-3 each time the phase difference differs by 360 °, that is, each time from time t8 to time t10.

As described above, the phase comparison circuits 31-0 to 31-
3 in response to the down request signals DW0 to DW3, the current source circuits 32-0 to 32-0 in the loop filter 32
The contacts of the switches 323 of 32-3 are sequentially closed. Therefore, the capacitor C is discharged by each current source 324 of the current source circuits 32-0 to 32-3. Here, the current amount of the current source 324 is the smallest in the current source circuit 32-0, and increases as the current source circuits 32-1, 32-2,. The input signal IN
The greater the phase difference between the output signal OUT and the output signal OUT, the greater the rate of change (rate of change) of the capacitor C, and the more the discharge voltage can be output as the control voltage of the voltage controlled oscillator 3.

Thereafter, at time t11, input signal I
When N changes from the "L" level to the "H" level, the down request signals DW, DW1... From the phase comparison circuits 31-0, 31-1 ... change from the "H" level to the "L" level. (See FIGS. 4D and 4F). By the above-described series of operations, at the start of the PLL operation, even when the frequency of the input signal IN and the frequency of the output signal OUT are greatly different and the phase difference is large, the phase difference gradually decreases, and the phase difference becomes smaller. Within 360 °, the phase difference can be further eliminated.

The above operations are summarized as follows. That is, the phase comparator 31 compares the phase of the input signal (reference signal) IN with the phase of the output signal OUT of the voltage controlled oscillator 3, and outputs an up request signal UP or a down request signal DW according to the comparison. Furthermore, the phase difference is 3
When the angle is 60 ° or more, the input signal IN and the output signal OU
An up request signal UP1 or a down request signal DW1 is output based on T, the up request signal UP, and the down request signal DW. Similarly, each time the phase difference differs by 360 °, an up request signal UP2... UPn or a down request signal DW2. That is, the up request signals UP1... UPn or the down request signals DW1.
n has a function of counting the phase difference when the phase difference differs by 360 °.

When the rising edge of the input signal IN is detected, the down request signals DW, DW1... DWn change from "H" level to "L" level, and the output signal OUT
Is detected, the rising request signal U
P, UP1,..., UPn change from “H” level to “L” level. In short, the input signal IN and the output signal OUT have a function of resetting the up request signals UP, UP1... UPn and the down request signals DW, DW1.

Further, when the frequency of the input signal IN and the frequency of the output signal OUT are greatly different from each other as in the rising operation of the PLL circuit and the phase difference is larger than 360 °,
, Or down request signals DW, DW1,..., Current source circuits 32-0, 32-1,.
Switch 321 or switch 323 is closed. Therefore, the capacitor C is rapidly charged by the large current from the current source 321 of the current source circuits 32-0, 32-1... Or the capacitor C is charged by the current source 324 of the current source circuits 32-0, 32-1. Is rapidly discharged, and this charge / discharge voltage can be supplied to the voltage controlled oscillator 3, and the oscillation frequency thereof can be largely changed. Therefore, the lock time can be reduced as compared with the related art.

On the other hand, when the frequency of the input signal IN is equal to the frequency of the output signal OUT, the contact of the switch 321 or the switch 323 of the current source circuit 32-0 is closed only by the up request signal UP or the down request signal DW. become. For this reason, the small-capacity current source 3 of the current source circuit 32-0 is used.
The capacitor C is slowly charged by the small current from the current source 21 or the small-capacity current source 324 of the current source circuit 32-0.
, The charge of the capacitor C is gradually discharged, and this charge / discharge voltage is supplied to the voltage controlled oscillator 3. For this reason, stability at the time of locking can be improved.

At the time of locking, the phase difference is usually 36.
0 ° or more, the up request signals UP1.
Since Pn and down request signals DW1... DWn are not output, these signals do not affect the operation at the time of locking. Therefore, a circuit for shortening the lock time does not affect the operation at the time of lock. As described above, in the embodiment of the present invention, the phase difference between the input signal and the output signal of the voltage controlled oscillator 3 is 360 ° (2π).
In the above case, the capacitor C is rapidly charged by the large current from the current sources 321 of the current source circuits 32-0, 32-1,... Or the current sources 324 of the current source circuits 32-0, 32-1,. As a result, the charge of the capacitor is rapidly discharged, and the charge / discharge voltage is supplied to the voltage controlled oscillator 3, so that the lock time can be reduced as compared with the conventional PLL circuit.

In the embodiment of the present invention, when the phase difference between the input signal and the output signal of the voltage controlled oscillator 3 is 360 ° or less, the current source 321 having the minimum current amount of the current source circuit 32-0 is used. Or 324 is selected, and the charging and discharging of the capacitor is gently performed by the selected current source. On the other hand, when the phase difference is 360 ° or more, the current amount is larger than the minimum current source. Since both current sources are selected and the capacitor is rapidly charged and discharged by both selected current sources, the circuit for shortening the lock time may affect the operation and stability when locking. Absent.

[0056]

As described above, according to the present invention, when the phase difference between the input signal and the output signal of the voltage controlled oscillator is large, for example, when the phase difference is 360 ° (2π) or more, Since the charging / discharging speed of the charger can be rapidly changed and this charging / discharging voltage can be supplied to the voltage controlled oscillator, the lock time can be reduced as compared with the conventional PLL circuit.

According to the present invention, when the phase difference between the input signal and the output signal of the voltage controlled oscillator is 360 ° or less,
The current source with the smallest amount of current is selected, and the charging / discharging of the capacitor is gradually changed by the selected current source. On the other hand, when the phase difference is 360 ° or more, the current source is selected in addition to the smallest current source. Both the current sources with a larger current than the current source are selected, and the charge / discharge of the capacitor is suddenly changed by the selected current sources. Does not affect sex.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the phase comparison unit shown in FIG.

FIG. 3 is a specific circuit diagram of the loop filter shown in FIG.

FIG. 4 is a waveform chart (time chart) showing waveforms of main parts of the circuit shown in FIG. 2;

FIG. 5 is a block diagram of the related art.

6 is a specific circuit diagram of the phase comparison circuit shown in FIG.

FIG. 7 is a specific circuit diagram of the loop filter shown in FIG.

[Explanation of symbols]

 Reference Signs List 3 voltage controlled oscillator 31 phase comparator 31-0 to 31-n phase comparator 32 loop filter 32-0 to 32-n current source circuit 41 to 44 RS flip-flop 51 input signal delay circuit 51 52 output signal delay circuit 52 53, 54 RS flip-flop 321, 324 Current source 322, 323 Switch C capacitor

Claims (3)

[Claims] 1. A phase comparison means, a control voltage generation means,
A PLL circuit comprising a voltage-controlled oscillator, wherein the phase comparing means detects a phase difference between an input signal and an output signal of the voltage-controlled oscillator, and outputs one or more frequencies according to the detected phase difference. A control signal is output, and the control voltage generation unit performs charging / discharging at different rates to the charger in accordance with the one or more frequency control signals,
A PLL circuit configured to output the charge / discharge voltage to the voltage controlled oscillator, wherein the voltage controlled oscillator has an oscillating frequency that can be varied according to the charge / discharge voltage. 2. The phase comparison means detects a phase difference between the input signal and the output signal of the voltage controlled oscillator. If the detected phase difference is 360 ° (2π) or less, the phase comparison means responds to the phase difference. Outputting a first frequency control signal, and outputting a second frequency control signal in addition to the first frequency control signal according to the phase difference when the detected phase difference is 360 ° or more. The PLL circuit according to claim 1, wherein 3. The control voltage generating unit includes: a plurality of current sources having different current amounts; and a capacitor charged and discharged based on the plurality of current sources. Is output, the current source having the smallest current amount is selected from the current sources, and the selected current source charges and discharges the capacitor. 2
When both frequency control signals are output, both the minimum current source and the current source having a larger amount of current are selected, and the capacitor is charged and discharged by the selected current sources. The PLL circuit according to claim 2, wherein: