JP2001068648A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly reliable semiconductor device which does not have any void in the space between adjacent capacitors and adjacent conductor wiring without increasing the number of photolithographic processes, and a method for manufacturing the device. SOLUTION: A first interlayer insulating film 15 is deposited on a semiconductor substrate 11 on which a transistor having a gate electrode 13a, etc., is formed and a capacitor section of a memory cell composed of storage node electrodes, etc., or a conductor wiring is formed on the insulating film 15. A step of selectively removing the part of the insulating film 15 above a peripheral circuit region and a step of depositing an insulating film 23 are performed one after another. Then side walls 23a and 23b composed of an insulator are respectively formed on the side faces of the capacitor section of the memory cell region or the conductor wiring and the side faces of the gate electrode 13a in the peripheral circuit region by etching back the insulating film 23. At the time of forming a second interlayer insulating film 25, the occurrence of voids is suppressed by the presence of the insulator sidewalls 23a and 23b of the capacitor section of the memory cell or the conductor wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a semiconductor memory device functioning as a DRAM having a charge storage capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Along with the high integration of semiconductor integrated circuits, a DRAM (Dynamic Random Access Memory) having a capacitor for storing electric charges has been developed.
Access read write memory) is also required to increase the memory capacity and reduce the memory cell area. Therefore, in recent DRAMs, in order to secure a large capacity with a small memory cell area, the capacity portion is often made three-dimensional. Examples of the three-dimensional structure of the capacitor include a stack-type capacitor in which a rectangular parallelepiped storage node electrode is formed and a capacitor insulating film serving as a capacitor is formed along the upper surface and side surfaces thereof, or a storage node electrode is formed in a cylindrical shape, And a cylindrical capacitance portion having a capacitance insulating film formed along the inner surface, the outer surface, and the bottom surface.

In a DRAM, in order to increase the capacitance, not only the shape of the storage node electrode but also the shape of the storage node electrode is increased.
The layout of capacitors and wiring is also devised. For example, in a COB (Capacitor Over Bit Line) structure, a capacitor is formed above a bit line, and there is no need to consider interference between the capacitor and the contact from the bit line to the drain region. A large capacitor can be formed. In addition, CUB (Capaci
In a torunder bit line (torr under bit line) structure, since the capacitor is formed below the bit line, the bit line and the first-layer metal wiring can be shared in the same layer. That is, the height position of the first-layer metal wiring with respect to the bit line can be aligned.
Therefore, in the CUB structure,
A connection hole for connecting the first-layer metal wiring and the gate wiring is easily opened in the interlayer insulating film. Further, since the distance between the bit line and the gate wiring is increased, the parasitic capacitance of the bit line can be suppressed.

FIGS. 9 (a) to 9 (d) and FIGS.
FIG. 2B is a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device in which a conventional DRAM having a cylindrical capacitor having a CUB structure and a CMOS device (logic) are mixed. In the figure, Rmemo indicates a memory cell area of the DRAM.
Is the drive circuit of the DRAM and M of other CMOS devices.
2 shows a peripheral circuit area where OS transistors are arranged. Further, diffusion layers serving as channel regions, source / drain regions, well regions, channel stopper regions, and the like are formed in the semiconductor substrate, but illustration and description of these diffusion layers are omitted.

First, in a step shown in FIG. 9A, a trench type element isolation region 102 is formed in a semiconductor substrate 101, and then a diffusion layer (not shown) to be a well region is formed. next,
A gate oxide film 100 and a gate oxide film 100 are formed on a substrate.
Above the gate electrode 103a, the element isolation region 10
On 2, a word line to be the gate wiring 103 b is formed. Thereafter, a diffusion layer (not shown) serving as a source / drain region is formed in the memory cell region Rmemo by implanting impurity ions using the gate electrode 103a as a mask, and a low concentration source / drain region is formed in the peripheral circuit region Rperi. A diffusion layer (not shown) is formed. further,
The gate electrode 103a and the gate wiring 10 are formed on the entire surface of the substrate.
A gate protection insulating film 104 covering 3b is formed.

Next, in the step shown in FIG. 9B, a BPSG (Boron Phosphus) having a thickness of about 950 nm is formed on the entire surface of the substrate.
ate silicate glass) film is deposited and reflowed by high-temperature treatment to form a first interlayer insulating film 105. Furthermore, by photolithography and dry etching,
First interlayer insulating film 105 in memory cell region Rmemo
After a connection hole reaching the diffusion layer (source region and drain region) of the semiconductor substrate 101 and the gate wiring 103b is opened, polysilicon is buried in the connection hole to form a polysilicon plug.

Next, in a step shown in FIG. 9C, a silicon nitride film 107 and a sacrificial interlayer insulating film 10 are formed on the entire surface of the substrate.
After depositing 8, an opening 109 for forming a storage node electrode is formed in the sacrificial interlayer insulating film 108 and the silicon nitride film 107 by photolithography and dry etching. The opening 109 is formed on the polysilicon plug 106 which is in contact with the source region of the semiconductor substrate 101.

Next, in a step shown in FIG. 9D, a polysilicon film is deposited on the substrate, a photoresist film is formed on the polysilicon film, and then the polysilicon film is patterned and sacrificial interlayer insulation is formed. By removing the film 108, a cylindrical storage node electrode 110 made of polysilicon is formed. Further, a capacitor insulating film 112 made of a silicon nitride film is formed along the exposed surfaces of the cylindrical storage node electrode 110 and the silicon nitride film 107.

Next, in a step shown in FIG. 9E, a polysilicon film 111 for a plate electrode is deposited on the capacitance insulating film 112, and then the polysilicon film 111 for the plate electrode is deposited by photolithography and dry etching. The capacitor insulating film 112 and the silicon nitride film 107 are patterned, and an exposed portion (peripheral circuit region Rperi) of the first interlayer insulating film 105 is removed by isotropic etching (wet etching). At this time, the gate protection insulating film 104 in the peripheral circuit region Rperi is exposed.

Next, in the step shown in FIG. 10A, the entire surface is etched back to form a sidewall 113 for forming an LDD structure on the side surface of the gate electrode 103a in the peripheral circuit region Rperi, The surface of the substrate 101 is exposed. After that, the peripheral circuit region Rperi
The gate electrode 103a and the side wall 11
Impurity ions are implanted using the mask 3 as a mask to form a diffusion layer (not shown) serving as a high-concentration source / drain region.

Then, in the step shown in FIG. 10B, a BPSG film having a thickness of about 1200 nm is deposited on the entire surface of the substrate, and the BPSG film is flattened by reflow to form a second BPSG film.
Is formed. Subsequently, the polysilicon plug 106 (the drain of the memory cell region Rmemo) is penetrated through the second interlayer insulating film 115, the polysilicon film 111 for the plate electrode, the capacitor insulating film 112, and the silicon nitride film 107 by photolithography and dry etching. After forming a connection hole that reaches the contact hole, a metal is buried in the connection hole to form a bit line contact 116. Further, the second interlayer insulating film 1
An aluminum wiring 117 (bit line wiring) connected to the bit line contact 116 is formed on 15.

Through the above steps, the memory cell region Rme
In mo, a memory cell having a memory cell transistor and a capacitor can be formed, and in the peripheral circuit region Rperi, a MOS transistor having an LDD structure can be formed.

[0013]

However, in the above-described semiconductor device manufacturing process, there are the following problems.

FIG. 11 is a sectional view showing a step after the step shown in FIG. 10A and before the step shown in FIG. 10B. That is, it is a cross-sectional view showing a structure of the nonvolatile semiconductor memory device when the second interlayer insulating film 115 is formed by flattening the BPSG film by reflow after depositing the BPSG film. As shown in FIG. 11, when forming the second interlayer insulating film 115, a void 122 is generated in a portion where a connection hole for forming a bit line contact 116 between adjacent capacitors is opened. I will. If a void exists at this position, a problem occurs when the connection hole is opened. For example, if a collision with a void occurs during the etching, the bottom of the void may be recognized as the end point of the etching at that point, and the etching may be stopped.

The cause of such voids is that the area of the memory cell region Rmemo is reduced and the second interlayer insulating film 1 is formed.
This is because the space for embedding the BPSG film of No. 15 has also become smaller. That is, before the BPSG film is completely embedded in the gap between the adjacent capacitors, the upper part of the gap is closed by the deposited BPSG film. In particular, the sacrificial interlayer insulating film 1 as shown in FIG.
When the opening 109 is formed at 08 and the storage node electrode is not formed vertically and has a taper due to the influence of the oxide film etching, the portion in which the BPSG is buried has a smaller diameter toward the top and a smaller diameter toward the bottom. It has a wider shape and is increasingly difficult to embed.

Such a problem is caused by a COB type DRAM.
In the semiconductor device provided with the above, the same can occur when the bit line wiring interval is reduced. That is, when the gap between the bit line wiring and the bit line wiring is narrow, a void may be generated.

An object of the present invention is to provide means for suppressing generation of voids when forming a connection hole for connecting a storage node or a bit line wiring to a substrate in a memory cell region in a second interlayer insulating film. Another object of the present invention is to provide a semiconductor device for obtaining a highly reliable device even when the density is increased, and a method for manufacturing the same.

[0018]

A first semiconductor device according to the present invention comprises a semiconductor substrate and a memory cell transistor provided on a part of the semiconductor substrate and having a gate insulating film, a gate electrode and source / drain regions. , A gate insulating film, a gate electrode, L
A peripheral circuit transistor having a DD insulator sidewall and source / drain regions; a first interlayer insulating film formed above the memory cell transistor; and a first interlayer insulating film formed on the first interlayer insulating film; A memory cell capacitor portion formed of a storage node electrode, a capacitor insulating film, and a plate electrode that is in contact with one of the source / drain regions of the memory cell transistor; and an LDD formed on the side surface of the memory cell capacitor portion,
An insulator sidewall made of the same material as at least a part of the insulator side wall, above the conductor wiring of the memory cell transistor, above the gate electrode of the peripheral circuit transistor, and above the LDD insulator side wall. A plug member formed by filling a connection hole penetrating the second interlayer insulating film and connected to the other of the source / drain regions of the memory cell transistor; It has.

As a result, on the side of the memory cell capacitance portion,
When the wedge-shaped sidewalls spreading downward are formed, the gap between the memory cell capacitor portions is narrowed, or the cylindrical storage node electrode of the memory cell capacitor portion has an inverted tapered shape. In addition, generation of voids in the second capacitor insulating film in the gap between them is suppressed. Therefore, the non-penetration state of the connection hole in the second interlayer insulating film can be effectively eliminated, and a highly reliable semiconductor device can be obtained.

In the first semiconductor device, the first semiconductor device
Is further provided with a silicon nitride film interposed between the first interlayer insulating film in the memory cell region and the first insulating film in the memory cell region. Can be suppressed from occurring in the second interlayer insulating film due to removal of a part of the interlayer insulating film.

According to a second semiconductor device of the present invention, a semiconductor substrate and a gate insulating film provided on a part of the semiconductor substrate are provided.
A memory cell transistor having a gate electrode and a source / drain region, and a peripheral circuit transistor provided on another portion of the semiconductor substrate and having a gate insulating film, a gate electrode, an LDD insulator sidewall, and a source / drain region. A first interlayer insulating film provided above the memory cell transistor, a conductor wiring provided on the first interlayer insulating film and in contact with one of source / drain regions of the memory cell transistor; An insulator sidewall formed on a side surface of the conductor wiring and made of the same material as at least a part of the LDD insulator sidewall of the peripheral circuit transistor; an upper part of the conductor wiring of the memory cell transistor; Above gate electrode of circuit transistor and insulator sidewall for LDD A plug member formed by filling a connection hole penetrating the second interlayer insulating film and connected to the other of the source / drain regions of the memory cell transistor; It has.

Thus, similar to the first semiconductor device,
Even when the gap between the conductor wirings becomes narrow, generation of voids in the second interlayer insulating film in the gap can be suppressed, and a highly reliable semiconductor device can be obtained.

In the second semiconductor device, the first semiconductor device
It is preferable to further include a silicon nitride film interposed between the interlayer insulating film and the conductor wiring.

The semiconductor device may further include a conductor protection film made of silicon nitride provided on the conductor wiring, wherein the insulator sidewall of the conductor wiring is made of silicon nitride. Even when the position of photolithography is displaced in the connection hole penetrating through the semiconductor device, the connection hole does not come into contact with the conductor wiring, and a highly reliable semiconductor device can be obtained.

The first method of manufacturing a semiconductor device according to the present invention comprises:
(A) forming a gate insulating film, a gate electrode, a gate wiring, and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate, and depositing a first interlayer insulating film on the substrate ( b) forming, on the first interlayer insulating film, a storage node electrode which is in contact with one of the source / drain regions of the memory cell transistor, a capacitor insulating film, and a memory cell capacitor portion including a plate electrode; Forming (c), selectively removing only a portion of the first interlayer insulating film located above the peripheral circuit region, and depositing a sidewall insulating film on the substrate After that, the sidewall insulating film is etched back, and an insulator layer is formed on the side surface of the capacitor in the memory cell region and the side surface of the gate electrode in the peripheral circuit region. Forming a second interlayer insulating film over the entire surface of the substrate (f); forming a second interlayer insulating film on the entire surface of the substrate; (G) forming a connection hole connected to the other of the drain regions.

According to this method, in the step (f) of forming the second interlayer insulating film, the occurrence of voids is suppressed by the presence of the insulator sidewall formed on the side surface of the memory cell capacitor. It is possible to reliably prevent the connection hole from being unpenetrated in the step (g).
Therefore, a highly reliable semiconductor device can be easily formed without increasing the number of photolithography steps.

In the first method of manufacturing a semiconductor device, after performing the step (a) and before performing the step (b), a gate protection insulating film covering at least the gate electrode and the gate wiring is deposited. In the step (e), the gate protective insulating film and the sidewall insulating film may be etched back to form the insulator sidewall on the side surface of the peripheral circuit transistor.

In the first method of manufacturing a semiconductor device, a silicon nitride film is formed on the first interlayer insulating film after performing the step (b) and before performing the step (c). It is preferable that the method further includes a step of selectively removing the portion of the silicon nitride film located above the peripheral circuit region in the step (d).

According to the second method of manufacturing a semiconductor device of the present invention,
Forming a gate insulating film, a gate electrode, a gate wiring, and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate, and depositing a gate protection insulating film covering at least the gate electrode and the gate wiring; (B), a step (c) of depositing a first interlayer insulating film on the substrate, and a step (c) of depositing the first interlayer insulating film on the substrate.
Forming a storage node electrode in contact with one of the source / drain regions of the memory cell transistor, and sequentially depositing a capacitor insulating film, a conductor film for a plate electrode, and an insulating film for a sidewall on the substrate (d) And (e) selectively removing only the portion of the side wall insulating film, plate electrode conductor film, capacitor insulating film, and first interlayer insulating film located above the peripheral circuit region. Etching back the sidewall insulating film in the peripheral circuit region and the gate protection insulating film in the peripheral circuit region to form a side surface of the capacitor portion in the memory cell region and a side surface of the gate electrode in the peripheral circuit region; (F) forming an insulator sidewall, (g) depositing a second interlayer insulating film on the substrate, A connection hole penetrating Enmaku,
(H) forming a plug member connected to the other of the source / drain regions of the memory cell transistor by filling the connection hole.

According to this method, similarly to the first method for manufacturing a semiconductor device, a highly reliable semiconductor device can be easily formed without increasing the number of photolithography steps.

In the second method of manufacturing a semiconductor device, a silicon nitride film is formed on the first interlayer insulating film after performing the step (c) and before performing the step (d). It is preferable that the method further includes a step of selectively removing the portion of the silicon nitride film located above the peripheral circuit region in the step (e).

According to a third method of manufacturing a semiconductor device of the present invention,
(A) forming a gate insulating film, a gate electrode, a gate wiring, and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate, and depositing a first interlayer insulating film on the substrate ( b), forming a conductor wiring in contact with one of the source / drain regions of the memory cell transistor on the first interlayer insulating film, and (c) forming the conductive wiring on the first interlayer insulating film; (D) selectively removing only a portion located above the peripheral circuit region, and depositing a sidewall insulating film on the substrate, and then etching back the sidewall insulating film. (E) forming insulator sidewalls on the side surface of the capacitor portion in the memory cell region and on the side surface of the gate electrode in the peripheral circuit region, respectively.
Depositing a second interlayer insulating film (f) and forming a connection hole penetrating through the second interlayer insulating film and connected to the other of the source / drain regions of the memory cell transistor (g) ).

According to this method, in the step (f) of forming the second interlayer insulating film, the occurrence of voids is suppressed by the presence of the insulator sidewall formed on the side surface of the conductor wiring. The non-penetration of the connection hole in g) can be reliably prevented. Therefore, a semiconductor device having high reliability and including a COB type DRAM can be easily formed without increasing the number of photolithography steps.

In the third method of manufacturing a semiconductor device, after performing the step (a) and before performing the step (b), a gate protection insulating film covering at least the gate electrode and the gate wiring is deposited. In the step (e), the gate protective insulating film and the sidewall insulating film may be etched back to form the insulator sidewall on the side surface of the peripheral circuit transistor.

In the third method of manufacturing a semiconductor device, a silicon nitride film is formed on the first interlayer insulating film after the step (b) and before the step (c). It is preferable that the method further includes a step of selectively removing the portion of the silicon nitride film located above the peripheral circuit region in the step (d).

In the third method of manufacturing a semiconductor device, in the step (c), a conductor protection film made of a silicon nitride film for protecting the upper surface of the conductor wiring is also formed, and the step (e) is performed. In (2), it is more preferable to form a silicon nitride film as the sidewall insulating film.

According to a fourth method of manufacturing a semiconductor device of the present invention,
Forming a gate insulating film, a gate electrode, a gate wiring, and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate, and depositing a gate protection insulating film covering at least the gate electrode and the gate wiring; (B), a step (c) of depositing a first interlayer insulating film on the substrate, and a step (c) of depositing the first interlayer insulating film on the substrate.
After forming a conductor wiring that contacts one of the source and drain regions of the memory cell transistor,
Step (d) of depositing an insulating film for a sidewall on the substrate
(E) selectively removing only a portion of the side wall insulating film and the first interlayer insulating film located above the peripheral circuit region; and (e) forming a side wall insulating film in the peripheral circuit region. And etching back the gate protection insulating film in the peripheral circuit region to form insulator sidewalls on the side surface of the capacitor in the memory cell region and on the side surface of the gate electrode in the peripheral circuit region, respectively. (F), a step (g) of depositing a second interlayer insulating film on the substrate, a connection hole penetrating the second interlayer insulating film, and a source of the memory cell transistor by filling the connection hole. And (h) forming a plug member connected to the other of the drain region.

According to this method, similarly to the third method for manufacturing a semiconductor device, a highly reliable device including a COB type DRAM can be easily formed without increasing the number of photolithography steps. .

In the fourth method of manufacturing a semiconductor device, a silicon nitride film is formed on the first interlayer insulating film after the step (c) and before the step (d). It is preferable that the method further includes a step of selectively removing the portion of the silicon nitride film located above the peripheral circuit region in the step (e).

In the fourth method of manufacturing a semiconductor device, in the step (d), a conductor protection film made of a silicon nitride film for protecting an upper surface of the conductor wiring is also formed, and More preferably, a silicon nitride film is formed as the insulating film.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIGS.
(D) and FIGS. 2 (a) to 2 (d) show a DRAM according to a first embodiment of the present invention having a cylindrical capacitor with a CUB structure.
FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device in which a semiconductor device and a CMOS device are mixed. In the figure, Rmemo indicates a memory cell area of the DRAM, Rperi indicates a driving circuit of the DRAM,
It shows a peripheral circuit area where MOS transistors of other CMOS devices are arranged.

First, in the step shown in FIG. 1A, a trench-type element isolation region 12 is formed in a silicon substrate 11, and then the element isolation region is implanted into each transistor formation region in the silicon substrate 11 by implanting impurity ions. Well regions 11a, 11b, and 11c are formed below the lower region 12. Each of the well regions 11a, 11b, and 11c is a p-type region in an n-transistor formation region, and is an n-type region in a p-type transistor formation region. Note that the memory cell region Rme
In mo, all the memory cell transistors are n-type M
The well region 11a is a p-type region because it is constituted by an OS transistor. Also, in the peripheral circuit region Rperi shown in FIG.
Type MOS transistors are formed adjacent to each other,
For example, the well region 11b is a p-type region, and the well region 11c is an n-type region.

Next, a gate oxide film 1 having a thickness of about 12 nm is formed on the exposed silicon substrate 11 by a thermal oxidation method.
After forming 0, a first polysilicon film doped with impurities and having a thickness of about 200 nm is deposited on the entire surface of the substrate by CVD. Then, the first polysilicon film is patterned by photolithography and dry etching to become a gate electrode 13 a on the gate oxide film 10 and a gate wiring 1 on the element isolation region 12.
A word line 3b is formed.

Thereafter, for each of the regions Rmemo and Rperi, an n-type or p-type low-concentration source / drain region 30 is formed in the peripheral circuit region Rperi by implanting impurity ions using the gate electrode 13a as a mask. An n-type source / drain region 31 is formed in the memory cell region Rmemo. Thereafter, a gate protection insulating film 14 formed by laminating a silicon oxide film having a thickness of about 20 nm and a silicon nitride film having a thickness of about 80 nm so as to cover the gate electrode 13a and the gate wiring 13b is formed on the entire surface of the substrate. .

Next, in the step shown in FIG. 1B, a BPSG (Boron Phosph
ate Silicate Glass) film, 650 ℃, 30mi
n after the heat treatment of CMP (Chemical Mechanical
Polishing) to form the interlayer insulating film 15. Furthermore, by photolithography and dry etching,
After opening a connection hole reaching the source / drain region 31 and the gate wiring 13b in the first interlayer insulating film 15 in the memory cell region Rmemo, a thickness of about 250
A second polysilicon film having a thickness of 10 nm is deposited, and an unnecessary portion of the second polysilicon film is removed by performing etch-back, thereby forming a polysilicon plug 16 for filling the connection hole.
To form Note that this etch back is one means used to remove an unnecessary portion of the second polysilicon film deposited on the first interlayer insulating film 15 and is performed by using another means such as CMP. It doesn't matter.

Next, in the step shown in FIG. 1C, a silicon nitride film 17 having a thickness of about 50 nm and a BPSG film having a thickness of about 700 nm are deposited on the entire surface of the substrate.
A heat treatment for 30 minutes is performed to form a sacrificial interlayer insulating film 18. Further, the sacrificial interlayer insulating film 18 and the silicon nitride film 1 are formed by photolithography and dry etching.
7, an opening 1 for forming a storage node electrode
9 is formed. The opening 19 is formed on the polysilicon plug 16 that is in contact with the source region of the semiconductor substrate 11.

Next, in the step shown in FIG. 1D, a third polysilicon film having a thickness of about 70 nm is deposited on the substrate, and covers the storage electrode formation region on the third polysilicon film. After the formation of the photoresist film, the third polysilicon film is patterned and the sacrificial interlayer insulating film 18 is removed to form a cylindrical storage node electrode 20 made of polysilicon. The height of the cylindrical storage node electrode 20 is about 550 nm. Then, the polysilicon HS is applied to the storage node electrode 20 to increase the capacitance.
G (Hemi Spherical Grain) is seeded and grown at 620 ° C. to increase the surface area of the storage node electrode 20. Further, a capacitance insulating film 22 made of a silicon nitride film having a thickness of about 6 nm is formed along the exposed surfaces of the storage node electrode 20 and the silicon nitride film 17.

Next, in the step shown in FIG. 2A, after depositing a fourth polysilicon film having a thickness of about 100 nm, a photoresist film 40 covering the memory cell region Rmemo is formed. A part of the fourth polysilicon film, the capacitor insulating film 22, and the silicon nitride film 17 is removed by anisotropic etching using 40 (see broken line) as a mask to form a plate electrode 21 made of polysilicon. Further, after removing the photoresist film 40, the first interlayer insulating film 15 is removed in the peripheral circuit region Rperi by wet etching using the silicon nitride film 17 as a mask, and the gate protection insulating film 14 is exposed.

Next, in a step shown in FIG. 2B, a silicon oxide film 23 for a sidewall having a thickness of about 100 nm is deposited on the entire surface of the substrate by the CVD method.

Next, in the step shown in FIG. 2C, the entire surface is etched back by anisotropic etching, so that the plate electrode 21 is formed in the memory cell region Rmemo.
Is formed on the side surface of the silicon oxide film 23. In the peripheral circuit region Rperi, on the side surface of the gate electrode 13a, a laminated film sidewall 14a composed of the remaining portion of the gate protection insulating film 14 and an oxide film sidewall 23b composed of the remaining portion of the silicon oxide film 23 are formed. At the same time, the surface of the silicon substrate 11 is exposed. The plate electrode 21 and the silicon nitride film 1 in the memory cell region Rmemo
7. An oxide film sidewall 23c is also formed on the end surface of the first interlayer insulating film 15 and the like.

Thereafter, in the peripheral circuit region Rperi, impurity ions are implanted using the gate electrode 13a, the stacked film sidewalls 14a and the oxide film sidewalls 23b as masks, so that the high-concentration source / drain regions 30 are exposed outside the low-concentration source / drain regions 30. A source / drain region 33 is formed.

Then, in the step shown in FIG. 2D, a BPSG film having a thickness of about 1200 nm is deposited on the entire surface of the substrate and subjected to a heat treatment at 650 ° C. for 30 minutes, followed by CM.
The second interlayer insulating film 25 is formed by flattening with P. Subsequently, the second interlayer insulating film 25 and the plate electrode 2 are formed by photolithography and dry etching.
1. After forming a connection hole that reaches the polysilicon plug 16 (that contacts the drain region of the memory cell region Rmemo) through the capacitor insulating film 22 and the silicon nitride film 17, an oxide film is formed in the connection hole. After the sidewalls are formed, tungsten is buried to form a tungsten plug 26. Further, after depositing an aluminum alloy film on the substrate, the aluminum alloy film is patterned to form an aluminum wiring 27 (bit line wiring) connected to the tungsten plug 26 on the second interlayer insulating film 25. .

By the above steps, the memory cell region Rme
In mo, a memory cell having a memory cell transistor and a capacitor can be formed, and in the peripheral circuit region Rperi, a MOS transistor having an LDD structure can be formed.

In this embodiment, only one CVD step is added to the conventional manufacturing process, and the second interlayer insulating film 2 is formed.
5 can suppress generation of voids. That is, in the step shown in FIG. 2C, since the oxide film sidewall 23a is formed on the side surface of the capacitance portion including the cylindrical storage node electrode 20, the capacitor insulating film 22, and the plate electrode 21, the cylindrical storage node electrode 20 is formed. The reverse taper on the side surface of the capacitor due to the step of forming the node electrode 20 is offset by the wedge shape of the insulator sidewall. Therefore,
Even if the gap between the capacitance parts of each memory cell is narrowed, it is possible to suppress the occurrence of voids in the gap when the second interlayer insulating film 25 is formed.

On the other hand, FIG.
The process shown in FIG. 10C is different from the process shown in FIG.
Although the number of steps for forming the silicon oxide film 23 by the method D is increasing, the number of photolithography steps is not increased, so that the shape accuracy of the semiconductor device is not adversely affected, and the manufacturing cost is slightly increased.

Further, since a two-layer insulating film including the first interlayer insulating film 15 and the silicon nitride film 17 is formed,
When removing the sacrificial interlayer insulating film 18 for forming the storage node electrode 20, the first interlayer insulating film 15 in the memory cell region Rmemo does not need to be removed. as a result,
In the memory cell region Rmemo, generation of voids when forming the silicon oxide film 23 and the second interlayer insulating film 25 can be more reliably prevented.

(Second Embodiment) FIGS. 3A to 3D
FIG. 7 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device in which a DRAM and a CMOS device according to a second embodiment of the present invention having a CUB structure and having a cylindrical capacitor are mixedly mounted. In the figure, Rmemo indicates a memory cell area of the DRAM.
Indicates a peripheral circuit region composed of MOS transistors.

In this embodiment, the steps shown in FIGS. 1A to 1D in the above-described first embodiment are performed, and then the steps shown in FIG. 3A are performed.
Therefore, in the present embodiment, description will be made from the step shown in FIG.

In the step shown in FIG. 3A, the capacitance insulating film 22
A fourth polysilicon film having a thickness of about 100 nm and a silicon oxide film for sidewalls 23 having a thickness of about 100 nm are sequentially deposited thereon by CVD.

Next, in a step shown in FIG. 3B, a photoresist film 41 covering the memory cell region Rmemo is formed, and this photoresist film 41 (see a broken line) is used as a mask.
A portion of the side wall silicon oxide film 23, the fourth polysilicon film, the capacitor insulating film 22, and the silicon nitride film 17 is removed to form a plate electrode 21 made of polysilicon. Further, after removing the photoresist film 41, the first interlayer insulating film 1 is formed in the peripheral circuit region Rperi by wet etching using the silicon nitride film 17 as a mask.
5 is removed to expose the gate protection insulating film 14.

Next, in the step shown in FIG. 3C, the entire surface is etched back by anisotropic etching, so that the plate electrode 2 is formed in the memory cell region Rmemo.
On one side surface, an oxide film sidewall 23a formed of the remaining portion of the silicon oxide film 23 is formed. In the peripheral circuit region Rperi, on the side surface of the gate electrode 13a,
The laminated film sidewalls 14a including the remaining portions of the gate protection insulating film 14 are formed, and the surface of the silicon substrate 11 is exposed.

Thereafter, in the peripheral circuit region Rperi, impurity ions are implanted using the gate electrode 13a and the stacked film side wall 14a as masks, so that the high-concentration source / drain regions 33 are formed outside the low-concentration source / drain regions 30. Form.

Then, in the step shown in FIG. 3D, a BPSG film having a thickness of about 1200 nm is deposited on the entire surface of the substrate and subjected to a heat treatment at 650 ° C. for 30 minutes.
The second interlayer insulating film 25 is formed by flattening with P. Subsequently, the second interlayer insulating film 25 and the plate electrode 2 are formed by photolithography and dry etching.
1. After forming a connection hole that reaches the polysilicon plug 16 (that contacts the drain region of the memory cell region Rmemo) through the capacitor insulating film 22 and the silicon nitride film 17, an oxide film is formed in the connection hole. After the sidewalls are formed, tungsten is buried to form a tungsten plug 26. Further, after an aluminum alloy film is deposited on the substrate, the aluminum alloy film is patterned to form an aluminum wiring 27 (bit line wiring) connected to the tungsten plug 26 on the second interlayer insulating film 25. .

By the above steps, the memory cell region Rme
In mo, a memory cell having a memory cell transistor and a capacitor can be formed, and in the peripheral circuit region Rperi, a MOS transistor having an LDD structure can be formed.

In the second embodiment, the generation of voids in the second interlayer insulating film 25 can be suppressed only by adding one CVD process to the conventional manufacturing process. That is, in the step shown in FIG. 3C, the cylindrical storage node electrode 20, the capacitor insulating film 22, and the plate electrode 2
Oxide film sidewalls 23b
Is formed, the cylindrical storage node electrode 20 is formed.
The reverse taper on the side surface of the capacitor portion due to the step of forming the first layer is almost eliminated. Therefore, even when the gap between the capacitor portions of each memory cell is narrowed, it is possible to suppress the occurrence of voids in the gap when the second interlayer insulating film 25 is formed.

In this method, since the plate electrode 21 is hardly etched as compared with the first embodiment, the fourth polysilicon film serving as the plate electrode 21 is set to about 30 nm smaller than the value described in this example. It can be formed as thin as possible.

The effect obtained by forming the insulating film having a two-layer structure with the first interlayer insulating film 15 and the silicon nitride film 17 is the same as that of the first embodiment.

(Third Embodiment) FIGS. 4 (a) to 4 (d) and FIGS. 5 (a) to 5 (d) show a DRAM according to a third embodiment of the present invention having a CUB structure and having a cylindrical capacitor. And CMO
FIG. 9 is a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device in which an S device is mixed. In the figure, Rmemo indicates a memory cell area of a DRAM, and Rperi indicates a peripheral circuit area including MOS transistors.

First, in the step shown in FIG. 4A, a trench-type element isolation region 12 is formed in a silicon substrate 11, and then the element isolation region is implanted into each transistor formation region in the silicon substrate 11 by implanting impurity ions. Well regions 11a, 11b, and 11c are formed below the lower region 12. The conductivity type of each of the well regions 11a, 11b, 11c is the first type.
As described in the embodiment.

Next, the gate oxide film 1 having a thickness of about 12 nm is formed on the exposed silicon substrate 11 by a thermal oxidation method.
After forming 0, a first polysilicon film doped with impurities and having a thickness of about 200 nm is deposited on the entire surface of the substrate by CVD. Then, the first polysilicon film is patterned by photolithography and dry etching to become a gate electrode 13 a on the gate oxide film 10 and a gate wiring 1 on the element isolation region 12.
A word line 3b is formed.

Thereafter, an n-type or p-type low-concentration source / drain region 30 is formed in the peripheral circuit region Rperi by implanting impurity ions using the gate electrode 13a as a mask for each of the regions Rmemo and Rperi. An n-type source / drain region 31 is formed in the memory cell region Rmemo. Here, in the present embodiment, the gate protection insulating film 1 as shown in FIG.
4 is not formed.

Next, in the step shown in FIG. 4B, a BPSG film having a thickness of about 950 nm is deposited on the entire surface of the substrate.
After performing a heat treatment at 50 ° C. for 30 minutes, the interlayer insulating film 15 is formed by performing CMP. Further, a connection hole reaching the source / drain region 31 and the gate wiring 13b is opened in the first interlayer insulating film 15 in the memory cell region Rmemo by photolithography and dry etching. Then, an unnecessary portion of the second polysilicon film is removed by etching back to form a polysilicon plug 16 for filling the connection hole.

Next, in the step shown in FIG. 4C, a silicon nitride film 17 having a thickness of about 50 nm and a BPSG film having a thickness of about 700 nm are deposited on the entire surface of the substrate.
A heat treatment for 30 minutes is performed to form a sacrificial interlayer insulating film 18. Further, the sacrificial interlayer insulating film 18 and the silicon nitride film 1 are formed by photolithography and dry etching.
7, an opening 1 for forming a storage node electrode
9 is formed. The opening 19 is formed on the polysilicon plug 16 that is in contact with the source region of the semiconductor substrate 11.

Next, in the step shown in FIG. 4D, a third polysilicon film having a thickness of about 70 nm is deposited on the substrate, and the storage electrode formation region is covered on the third polysilicon film. After the formation of the photoresist film, the third polysilicon film is patterned and the sacrificial interlayer insulating film 18 is removed to form a cylindrical storage node electrode 20 made of polysilicon. The height of the cylindrical storage node electrode 20 is about 550 nm. Then, the polysilicon HS is applied to the storage node electrode 20 to increase the capacitance.
G (Hemi Spherical Grain) is seeded and grown at 620 ° C. to increase the surface area of the storage node electrode 20. Further, a capacitance insulating film 22 made of a silicon nitride film having a thickness of about 6 nm is formed along the exposed surfaces of the storage node electrode 20 and the silicon nitride film 17.

Next, in a step shown in FIG. 5A, after depositing a fourth polysilicon film having a thickness of about 100 nm, a photoresist film 42 (see a broken line) covering the memory cell region Rmemo is formed. Using the photoresist film 42 as a mask, the fourth polysilicon film, the capacitor insulating film 22, and a part of the silicon nitride film 17 are removed to form the plate electrode 21 made of polysilicon. Further, a photoresist film 42
After removing the first interlayer insulating film 15 in the peripheral circuit region Rperi by wet etching using the silicon nitride film 17 as a mask, the gate electrode 13a is exposed.

Next, in a step shown in FIG. 5B, a silicon oxide film 23 for a sidewall having a thickness of about 100 nm is deposited on the entire surface of the substrate by the CVD method.

Next, in the step shown in FIG. 5C, the entire surface is etched back by anisotropic etching, so that the plate electrode 21 is formed in the memory cell region Rmemo.
Is formed on the side surface of the silicon oxide film 23. Also in the peripheral circuit region Rperi, an oxide film sidewall 23b composed of a remaining portion of the silicon oxide film 23 is formed on the side surface of the gate electrode 13a, and the surface of the silicon substrate 11 is exposed. An oxide film sidewall 23c is also formed on the end surfaces of the plate electrode 21, the silicon nitride film 17, the first interlayer insulating film 15, and the like in the memory cell region Rmemo.

Thereafter, in the peripheral circuit region Rperi, impurity ions are implanted using the gate electrode 13a and the oxide film side wall 23b as a mask, so that the high concentration source / drain region 33 is formed outside the low concentration source / drain region 30. Form.

Then, in a step shown in FIG. 5D, a BPSG film having a thickness of about 1200 nm is deposited on the entire surface of the substrate, and after a heat treatment at 650 ° C. for 30 minutes, a CM is formed.
The second interlayer insulating film 25 is formed by flattening with P. Subsequently, the second interlayer insulating film 25 and the plate electrode 2 are formed by photolithography and dry etching.
1. After forming a connection hole which reaches the polysilicon plug 16 (which is in contact with the drain region of the memory cell region Rmemo) through the capacitor insulating film 22 and the silicon nitride film 17, a side surface of the connection hole is formed. After the oxide film sidewalls are formed, tungsten is buried therein to form tungsten plugs 26. Further, after depositing an aluminum alloy film on the substrate, the aluminum alloy film is patterned to form an aluminum wiring 27 (bit line wiring) connected to the tungsten plug 26 on the second interlayer insulating film 25. .

Through the above steps, the memory cell region Rme
In mo, a memory cell having a memory cell transistor and a capacitor can be formed, and in the peripheral circuit region Rperi, a MOS transistor having an LDD structure can be formed.

In the present embodiment, similarly to the first and second embodiments, the oxide film sidewall 23a is formed on the side surface of the capacitance portion composed of the cylindrical storage node electrode 20, the capacitance insulating film 22, and the plate electrode 21. Is formed, the reverse taper on the side surface of the capacitor portion due to the step of forming the cylindrical storage node electrode 20 is substantially eliminated. Therefore, even when the gap between the capacitor portions of each memory cell is narrowed, it is possible to suppress the occurrence of voids in the gap when the second interlayer insulating film 25 is formed.

Further, in the present embodiment, the generation of voids in the second interlayer insulating film 25 can be suppressed by the same number of steps as the conventional manufacturing steps. That is, FIG.
By the step shown in (b), the oxide film side wall 23b required for the LDD structure in the peripheral circuit region Rperi,
By forming a silicon oxide film 23 that can be shared with an oxide film sidewall 23a necessary for suppressing voids in the memory cell region Rmemo, the gate protection insulating film 14 formed in the first and second embodiments is formed. Is not required.

Since a two-layer insulating film including the first interlayer insulating film 15 and the silicon nitride film 17 is formed,
As in the first and second embodiments, it is possible to more reliably prevent the occurrence of voids when forming the silicon oxide film 23 and the second interlayer insulating film 25 in the memory cell region Rmemo. .

The present embodiment can be used on the premise that the polysilicon plug 16 does not contact the gate electrode 13a or the gate wiring 13b.

In this method, since the plate electrode 21 is hardly etched, the fourth polysilicon serving as the plate electrode is reduced by about 30 n from the value described in this example.
m can be formed as thin as possible.

Since the insulating film having a two-layer structure including the interlayer insulating film 15 and the silicon nitride film 17 is formed, generation of voids when forming the silicon oxide film 23 and the second interlayer insulating film 25 is prevented. This is similar to the first and second embodiments.

(Fourth Embodiment) FIGS. 6A to 6D and FIGS. 7A to 7D show a DRAM according to a fourth embodiment of the present invention having a cylindrical capacitor with a COB structure. And CMO
FIG. 9 is a cross-sectional view illustrating an example of a manufacturing process of a semiconductor device in which an S device is mixed. In the figure, Rmemo indicates a memory cell area of a DRAM, and Rperi indicates a peripheral circuit area including MOS transistors. Here, FIGS. 6 (a) to 6 (d)
FIGS. 7A to 7D show cross sections parallel to the word lines in the memory cell region Rmemo.

First, in the step shown in FIG. 6A, a trench-type element isolation region 12 is formed in a silicon substrate 11, and then the element isolation region is implanted into each transistor formation region in the silicon substrate 11 by implanting impurity ions. Well regions 11a, 11b, and 11c are formed below the lower region 12. The conductivity type of each of the well regions 11a, 11b, 11c is as described in the first embodiment.

Next, a gate oxide film 1 having a thickness of about 12 nm is formed on the exposed silicon substrate 11 by a thermal oxidation method.
After forming 0, a first polysilicon film doped with impurities and having a thickness of about 200 nm is deposited on the entire surface of the substrate by CVD. Then, the first polysilicon film is patterned by photolithography and dry etching to become a gate electrode 13 a on the gate oxide film 10 and a gate wiring 1 on the element isolation region 12.
A word line 3b is formed.

Thereafter, an n-type or p-type low-concentration source / drain region 30 is formed in the peripheral circuit region Rperi by implanting impurity ions using the gate electrode 13a as a mask for each of the regions Rmemo and Rperi. An n-type source / drain region (not shown) is formed in the memory cell region Rmemo. Thereafter, a thickness of about 20 is formed on the entire surface of the substrate so as to cover the gate electrode 13a and the gate wiring 13b.
A gate protection insulating film 14 is formed by laminating a silicon oxide film having a thickness of about 80 nm and a silicon nitride film having a thickness of about 80 nm.

Next, in the step shown in FIG. 6B, a BPSG film having a thickness of about 950 nm is deposited on the entire surface of the substrate.
After performing a heat treatment at 50 ° C. for 30 minutes, the first interlayer insulating film 15 is formed by performing CMP. Furthermore, the first
After a silicon nitride film 17 having a thickness of about 50 nm is deposited on the interlayer insulating film 15 of FIG. 1, the source nitride is deposited on the silicon nitride film 15 and the first interlayer insulating film 15 in the memory cell region Rmemo by photolithography and dry etching.
A connection hole (bit line contact hole) reaching the drain region is opened. Then, the thickness is about 25 on the entire surface of the substrate.
A second polysilicon film having a thickness of 0 nm is deposited, and an unnecessary portion of the second polysilicon film is removed by performing an etch back to form a polysilicon top plug (see a broken line) that fills the connection hole.

Next, in the step shown in FIG. 6C, after depositing a third polysilicon film on the silicon nitride film 17,
The third polysilicon film is patterned by photolithography and etching to form a bit line wiring 50 on a polysilicon plug connected to the drain region.

Next, in a step shown in FIG. 6D, a photoresist film 43 covering the memory cell region Rmemo (see a broken line)
Is formed, a part of the silicon nitride film 17 is removed by anisotropic etching using the photoresist film 43 as a mask. Further, after removing the photoresist film 43, the first interlayer insulating film 15 is removed in the peripheral circuit region Rperi by wet etching using the silicon nitride film 17 as a mask, and the gate protection insulating film 14 is exposed.

Next, in the step shown in FIG. 7A, a silicon oxide film 23 for a sidewall having a thickness of about 100 nm is deposited on the entire surface of the substrate by the CVD method.

Next, in the step shown in FIG. 7B, the entire surface is etched back by anisotropic etching, so that the bit line wiring 50 is formed in the memory cell region Rmemo.
Is formed on the side surface of the silicon oxide film 23. In the peripheral circuit region Rperi, on the side surface of the gate electrode 13a, a laminated film sidewall 14a composed of the remaining portion of the gate protection insulating film 14 and an oxide film sidewall 23b composed of the remaining portion of the silicon oxide film 23 are formed. At the same time, the surface of the silicon substrate 11 is exposed. Note that an oxide film sidewall 23c is also formed on the end surfaces of the silicon nitride film 17, the first interlayer insulating film 15, and the like in the memory cell region Rmemo.

Thereafter, in the peripheral circuit region Rperi, impurity ions are implanted using the gate electrode 13a, the stacked film sidewalls 14a and the oxide film sidewalls 23b as masks, so that the high-concentration source / drain regions 30 are exposed outside the low-concentration source / drain regions 30. A source / drain region 33 is formed.

Then, in the step shown in FIG. 7 (c), a BPSG film having a thickness of about 1200 nm is deposited on the entire surface of the substrate, and is subjected to a heat treatment at 650 ° C. for 30 minutes.
The second interlayer insulating film 25 is formed by flattening with P. Subsequently, a connection hole that penetrates through the second interlayer insulating film 25 and reaches the polysilicon plug (contacting the source region of the memory cell region Rmemo) is formed by photolithography and dry etching.
Tungsten is buried in the connection hole to form a tungsten plug (see a broken line). Further, a cylindrical storage node electrode 51 made of polysilicon is formed on the tungsten plug.

Although the subsequent steps are omitted, polysilicon HSG (Hemi Spheric) is applied to the storage node electrode 51.
al Grain) and grown at 620 ° C. to increase the surface area of the storage node electrode 51, and thereafter, a capacitance insulating film, a plate electrode, an aluminum wiring, and the like are formed as in the above embodiments.

By the above steps, the memory cell region Rme
In mo, a memory cell having a memory cell transistor and a capacitor can be formed, and in the peripheral circuit region Rperi, a MOS transistor having an LDD structure can be formed.

In this embodiment, only one CVD step is added to the conventional manufacturing process, and the second interlayer insulating film 2 is formed.
5 can suppress generation of voids. That is, since the oxide film sidewalls 23a are formed on the side surfaces of the bit line wiring 50 in the step shown in FIG. 7C, even if the gap between the bit line wirings 50 is narrowed, the second interlayer insulating film is formed. The generation of voids in the gap during the formation of 25 can be suppressed.

On the other hand, FIG.
The process shown in FIG. 10C is different from the process shown in FIG.
Although the number of steps for forming the silicon oxide film 23 by the method D is increasing, the number of photolithography steps is not increased, so that the shape accuracy of the semiconductor device is not adversely affected, and the manufacturing cost is slightly increased.

Since the two-layer structure of the first interlayer insulating film 15 and the silicon nitride film 17 is formed, when the first interlayer insulating film 15 is removed by wet etching, the first layer in the peripheral circuit region Rperi is removed. Only the interlayer insulating film 15 can be selectively removed, and the first interlayer insulating film 15 in the memory cell region Rmemo can be left. for that reason,
The generation of voids when forming the silicon nitride film 53 and the second interlayer insulating film 25 is prevented.

(Fifth Embodiment) FIGS. 8A to 8E
FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a semiconductor device in which a DRAM and a CMOS device according to a fifth embodiment of the present invention having a COB structure and having a cylindrical capacitor are mixedly mounted. In the figure, Rmemo indicates a memory cell area of the DRAM.
Indicates a peripheral circuit region composed of MOS transistors. Here, FIGS. 8A to 8E illustrate the memory cell region R
In memo, a cross section parallel to the word line is shown.

First, FIG. 6 in the fourth embodiment
By performing the same steps as the steps shown in (a) and (b), the same members as described in the fourth embodiment are formed. Thereafter, the step shown in FIG.

Next, in the step shown in FIG. 8A, after a third polysilicon film and a silicon nitride film are sequentially deposited on the silicon nitride film 17, the third polysilicon film is formed by photolithography and etching. By patterning the film and the silicon nitride film, the bit line wiring 5 is formed on the polysilicon plug connected to the drain region.
0 and a bit line protection film 52 are formed.

Next, in the step shown in FIG. 8B, a photoresist film 44 covering the memory cell region Rmemo is formed, and then the silicon film is anisotropically etched using the photoresist film 44 (see broken line) as a mask. A part of the nitride film 17 is removed. Further, after removing the photoresist film 44, the first interlayer insulating film 15 is removed in the peripheral circuit region Rperi by wet etching using the silicon nitride film 17 as a mask, and the gate protection insulating film 14 is exposed.

Next, in a step shown in FIG. 8C, a silicon nitride film 53 for a sidewall having a thickness of about 100 nm is deposited on the entire surface of the substrate by the CVD method.

Next, in the step shown in FIG. 8D, the entire surface is etched back by anisotropic etching, so that the bit line wiring 50 is formed in the memory cell region Rmemo.
And a silicon nitride film 5 on the side surface of the bit line protection film 52.
A nitride film sidewall 53a consisting of the remaining portion of No. 3 is formed. In the peripheral circuit region Rperi, on the side surface of the gate electrode 13a, a laminated film sidewall 14a including the remaining portion of the gate protection insulating film 14 and the silicon nitride film 5 are formed.
3 and a nitride film sidewall 53b formed of the remaining portion, and the surface of the silicon substrate 11 is exposed. Note that nitride film sidewalls 53c are also formed on the end surfaces of the silicon nitride film 17, the first interlayer insulating film 15, and the like in the memory cell region Rmemo.

Thereafter, in the peripheral circuit region Rperi, impurity ions are implanted using the gate electrode 13a, the laminated film sidewalls 14a and the nitride film sidewalls 53b as masks, so that the high-concentration source / drain regions 30 are exposed outside. A source / drain region 33 is formed.

Then, in the step shown in FIG. 8E, a BPSG film having a thickness of about 1200 nm is deposited on the entire surface of the substrate and subjected to a heat treatment at 650 ° C. for 30 minutes.
The second interlayer insulating film 25 is formed by flattening with P. Subsequently, a connection hole that penetrates through the second interlayer insulating film 25 and reaches the polysilicon plug (contacting the source region of the memory cell region Rmemo) is formed by photolithography and dry etching.
Tungsten is buried in the connection hole to form a tungsten plug (see a broken line). Further, a cylindrical storage node electrode 51 made of polysilicon is formed on the tungsten plug.

Although the subsequent steps are omitted, the storage node electrode 51 is formed of polysilicon HSG (Hemi Spheric).
al Grain) and grown at 620 ° C. to increase the surface area of the storage node electrode 51, and thereafter, a capacitance insulating film, a plate electrode, an aluminum wiring, and the like are formed as in the above embodiments.

Through the above steps, the memory cell region Rme
In mo, a memory cell having a memory cell transistor and a capacitor can be formed, and in the peripheral circuit region Rperi, a MOS transistor having an LDD structure can be formed.

In the present embodiment, the second interlayer insulating film 2 is formed only by adding two CVD processes to the conventional manufacturing process.
5, and the generation of voids can be suppressed. The connection hole for forming the storage node can be formed in a self-aligned manner. That is, since the periphery of the bit line 50 is covered with the bit line protection film 52 and the nitride film sidewall 53a formed of the silicon nitride film, the misalignment of the storage node formation connection hole occurs. Even in such a case, there is an advantage that an electrical short circuit caused by contact between the storage node and the bit line wiring 50 can be reliably prevented.

That is, in the step shown in FIG. 8E, since the nitride film sidewall 53a is formed on the side surface of the bit line wiring 50, even if the gap between the bit line wirings 50 is narrowed, the second It is possible to suppress the generation of voids in the gap when the interlayer insulating film 25 is formed.

In this method, the bit line wiring 50 is hardly etched at the time of wet etching for removing the first interlayer insulating film 15, so that the third polysilicon to be the bit line wiring 50 is removed. It can be formed thinner than the thickness shown in the example.

Since the two-layer structure of the first interlayer insulating film 15 and the silicon nitride film 17 is formed, when the first interlayer insulating film 15 is removed by wet etching, the first interlayer insulating film 15 in the peripheral circuit region Rperi is removed. Only the interlayer insulating film 15 can be selectively removed, and the first interlayer insulating film 15 in the memory cell region Rmemo can be left. for that reason,
The generation of voids when forming the silicon nitride film 53 and the second interlayer insulating film 25 is prevented. On the other hand, the number of steps of forming two silicon nitride films by the CVD method is increased from the step shown in FIG. 9A to the step shown in FIG. 10A in the conventional manufacturing method. Since it does not increase, the shape accuracy of the semiconductor device is not adversely affected, and the increase in the manufacturing cost is slight.

(Other Embodiments) In each of the above embodiments, the silicon nitride film 17 is provided on the first interlayer insulating film. However, even if the silicon nitride film 17 is not formed, the effects of the present invention can be obtained. It is possible to demonstrate to some extent.

In the first to third embodiments, the cylindrical storage node electrode 20 having the reverse taper is formed. However, the fourth to fifth embodiments are also applied to the first to third embodiments. As in the embodiment, a cylindrical storage node having almost no taper may be formed. Further, the storage node may have a stack type structure instead of the cylindrical structure. In these cases as well, if the gap between the storage nodes is narrowed, voids may be generated when the second interlayer insulating film is formed. However, the presence of the oxide film sidewall or the nitride film sidewall causes a positive taper. This is because the shape can suppress the generation of voids.

In the fourth embodiment, as in the second embodiment, a silicon nitride film and a first interlayer insulating film in the peripheral circuit region Rperi are formed by first depositing a sidewall insulating film on the entire surface. May be selectively removed.

In the fourth embodiment, the formation of the gate protection insulating film 14 may be omitted.

In each of the above embodiments, the high-concentration source / drain regions 33 and the low-concentration source / drain regions 30 are provided for the MOS transistors in the peripheral circuit region Rperi.
It is not necessary to have any kind of diffusion layer. For example, there is a MOS transistor in which a high concentration impurity is introduced into a formation region of the low concentration source / drain 30 in each embodiment.

In each of the above embodiments, in the memory cell region Rmemo, the connection hole penetrating the second interlayer insulating film 25 reaches the polysilicon plug filling the connection hole penetrating the first interlayer insulating film 15. However, before this step, the connection holes are not formed in the first interlayer insulating film 15 and the second interlayer insulating film 25 and the silicon nitride film 17 are formed.
And forming a connection hole penetrating the first interlayer insulating film 15,
A plug member that fills this connection hole may be formed.

[0123]

According to the semiconductor device of the present invention or the method of manufacturing the same, as a semiconductor device having a memory cell region and a peripheral circuit region or a method of manufacturing the same, the first interlayer insulating film is left only in the memory cell region. When the capacitor portion or the conductor wiring is provided thereon, the insulator sidewall is left on the side surface of the capacitor portion or the conductor wire in the memory cell region and the side surface of the gate electrode of the peripheral circuit transistor. A highly reliable and miniaturized semiconductor device can be obtained without increasing the number of semiconductor devices.

[Brief description of the drawings]

FIGS. 1A to 1D show a CU according to a first embodiment;
It is sectional drawing which shows the first half part of the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 2A to 2D are CUs according to the first embodiment;
It is sectional drawing which shows the latter half part of the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 3A to 3D are diagrams illustrating a CU according to a second embodiment;
It is sectional drawing which shows the latter half part of the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 4A to 4D show CUs according to a third embodiment;
It is sectional drawing which shows the first half part of the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 5A to 5D show a CU according to a third embodiment;
It is sectional drawing which shows the latter half part of the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 6 (a) to 6 (d) are views showing CO according to a fourth embodiment;
It is sectional drawing which shows the first half part of the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 7 (a) to 7 (c) show CO according to a fourth embodiment.
It is sectional drawing which shows the latter half part of the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 8A to 8E show CO according to a fifth embodiment;
It is sectional drawing which shows the manufacturing process of the semiconductor device which has a cylindrical capacitor by B structure.

FIGS. 9A to 9E are cross-sectional views showing a first half of a manufacturing process of a semiconductor device having a conventional CUB structure and having a cylindrical capacitor.

FIGS. 10A and 10B are cross-sectional views showing a latter half of a manufacturing process of a semiconductor device having a conventional CUB structure and having a cylindrical capacitor.

FIG. 11 is a cross-sectional view showing a state in which voids are formed when a second interlayer insulating film is formed in a manufacturing process of a semiconductor device having a cylindrical capacitor having a conventional CUB structure.

[Explanation of symbols]

 Rmemo Memory cell region Rperi Peripheral circuit region 11 Silicon substrate 11a to 11c Well region 12 Silicon oxide film 13a Gate electrode 13b Gate wiring 14 Gate protective insulating film 14a Stacked film sidewall 15 First interlayer insulating film 16 Polysilicon plug 17 Silicon nitride Film 18 sacrificial interlayer insulating film 19 opening 20 storage node electrode 21 plate electrode 22 capacitive insulating film 23 silicon oxide film 23a to 23c oxide film sidewall 25 second interlayer insulating film 26 tungsten plug 27 aluminum wiring 30 low concentration source / drain Region 31 source / drain region 33 high-concentration source / drain region 40 to 44 photoresist film 50 bit line wiring 51 storage node electrode 52 bit line protective film 53 silicon nitride for sidewall Film 53a-53c Nitride film sidewall

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihito Uno 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Noritaka Hibi 1-1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Industry Co., Ltd. (72) Inventor Kazushi Nii 1-1 Sachicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 5F038 AC05 AC09 AC10 DF05 EZ15 EZ17 EZ18 5F083 AD24 AD49 AD62 JA39 JA56 KA05 MA06 MA17 MA20 PR06 PR10 PR29 PR33 PR39 PR40 PR43 PR45 PR53 PR54 PR55 ZA05 ZA06

Claims (17)

[Claims] A semiconductor substrate, a memory cell transistor provided on a part of the semiconductor substrate and having a gate insulating film, a gate electrode, and a source / drain region; and a gate provided on another part of the semiconductor substrate. Insulating film,
A peripheral circuit transistor having a gate electrode, an LDD insulator sidewall and a source / drain region; a first interlayer insulating film formed above the memory cell transistor; and a first interlayer insulating film formed on the first interlayer insulating film. A storage node electrode in contact with one of the source / drain regions of the memory cell transistor; a capacitor insulating film; a memory cell capacitor comprising a plate electrode; and a memory cell capacitor formed on a side surface of the memory cell capacitor. An insulator sidewall made of the same material as at least a part of the LDD insulator sidewall of the peripheral circuit transistor; a portion above the conductor wiring of the memory cell transistor; a gate electrode of the peripheral circuit transistor and an LDD insulator; A second interlayer insulating film provided over the side wall; And a plug member formed to fill a connection hole penetrating the second interlayer insulating film and connected to the other of the source / drain regions of the memory cell transistor. 2. The semiconductor device according to claim 1, further comprising a silicon nitride film interposed between said first interlayer insulating film and said memory cell capacitor. 3. A semiconductor substrate, a memory cell transistor provided on a part of the semiconductor substrate and having a gate insulating film, a gate electrode, and a source / drain region; and a gate provided on another part of the semiconductor substrate. Insulating film,
A peripheral circuit transistor having a gate electrode, an LDD insulator sidewall, and a source / drain region; a first interlayer insulating film provided above the memory cell transistor; and a first interlayer insulating film provided on the first interlayer insulating film. A conductor wiring contacting one of the source / drain regions of the memory cell transistor; and a material formed on a side surface of the conductor wiring and made of the same material as at least a part of an LDD insulator sidewall of the peripheral circuit transistor. A second interlayer insulating film provided over the conductor sidewall of the memory cell transistor, over the gate electrode of the peripheral circuit transistor, and over the LDD insulator sidewall; The memory cell transistor is formed by filling a connection hole penetrating the second interlayer insulating film. A semiconductor device and a plug member which is connected to the other of the source and drain regions of the register. 4. The semiconductor device according to claim 3, further comprising a silicon nitride film interposed between said first interlayer insulating film and said conductor wiring. 5. The semiconductor device according to claim 3, further comprising a conductor protection film provided on the conductor wiring and made of silicon nitride, wherein the insulator sidewall of the conductor wiring is made of silicon nitride. A semiconductor device characterized in that: 6. A step (a) of forming a gate insulating film, a gate electrode, a gate wiring and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate, and forming a first interlayer insulating film on the substrate. (B) depositing, on the first interlayer insulating film, a storage node electrode in contact with one of the source / drain regions of the memory cell transistor; a capacitor insulating film; and a plate electrode. (C) forming a memory cell capacitor portion, and (d) selectively removing only a portion of the first interlayer insulating film located above the peripheral circuit region; After depositing the insulating film for the wall, the insulating film for the sidewall is etched back so that the side surface of the memory cell capacitance portion and the side surface of the gate electrode in the peripheral circuit region are etched. A step (e) of forming an insulator side wall, a step (f) of depositing a second interlayer insulating film on a substrate, and a step of penetrating the second interlayer insulating film to form the memory cell transistor. (G) forming a connection hole connected to the other of the source / drain regions. 7. The method of manufacturing a semiconductor device according to claim 6, wherein after performing the step (a), the step (b) includes the step of forming a gate protection insulating film covering at least the gate electrode and the gate wiring. The method further includes a step of depositing, wherein in the step (e), the gate protection insulating film and the sidewall insulating film are etched back to form the insulator sidewall on a side surface of a peripheral circuit transistor. Semiconductor device manufacturing method. 8. The method for manufacturing a semiconductor device according to claim 6, wherein after performing the step (b) and before performing the step (c), a silicon is formed on the first interlayer insulating film. A method of manufacturing a semiconductor device, further comprising a step of forming a nitride film, wherein in the step (d), a portion of the silicon nitride film located above a peripheral circuit region is also selectively removed. 9. A step (a) of forming a gate insulating film, a gate electrode, a gate line, and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate, and a gate covering at least the gate electrode and the gate line. A step (b) of depositing a protective insulating film; a step (c) of depositing a first interlayer insulating film on the substrate; and a source / drain of the memory cell transistor on the first interlayer insulating film. Forming a storage node electrode in contact with one of the regions, and sequentially depositing a capacitor insulating film, a conductor film for a plate electrode, and an insulating film for a sidewall on the substrate; Film, conductor film for plate electrode,
(E) selectively removing only a portion of the capacitive insulating film and the first interlayer insulating film located above the peripheral circuit region; and a sidewall insulating film in the peripheral circuit region;
(F) etching back the gate protection insulating film in the peripheral circuit region to form insulator sidewalls on the side surface of the memory cell capacitance portion and the side surface of the gate electrode in the peripheral circuit region, respectively. (G) depositing a second interlayer insulating film on the substrate; connecting holes penetrating the second interlayer insulating film; and filling the connection holes with a source / drain region of the memory cell transistor. And (h) forming a plug member connected to the other side. 10. The method of manufacturing a semiconductor device according to claim 9, wherein after performing the step (c) and before performing the step (d), a silicon nitride film is formed on the first interlayer insulating film. A method of manufacturing a semiconductor device, characterized in that in the step (e), a portion of the silicon nitride film located above a peripheral circuit region is also selectively removed. 11. A step of forming a gate insulating film, a gate electrode, a gate wiring, and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate (a).
(B) depositing a first interlayer insulating film on the substrate; and conductive wiring contacting one of the source / drain regions of the memory cell transistor on the first interlayer insulating film. (C), selectively removing only a portion of the first interlayer insulating film located above the peripheral circuit region, and (d) forming a sidewall insulating film on the substrate. (E) forming an insulator sidewall on the side surface of the memory cell capacitor and the side surface of the gate electrode in the peripheral circuit region by etching back the insulating film for the sidewall after the deposition. (F) depositing a second interlayer insulating film on the substrate; and forming a connection hole penetrating the second interlayer insulating film and connected to the other of the source / drain regions of the memory cell transistor. Form The method of manufacturing a semiconductor device and a step (g). 12. The method for manufacturing a semiconductor device according to claim 11, wherein after performing the step (a) and before performing the step (b), a gate protection insulating film covering at least the gate electrode and the gate wiring. Further comprising the step of: depositing the gate protection insulating film and the sidewall insulating film in the step (e) to form the insulator sidewall on the side surface of the peripheral circuit transistor. Manufacturing method of a semiconductor device. 13. The method for manufacturing a semiconductor device according to claim 11, wherein after performing the step (b) and before performing the step (c), a silicon is formed on the first interlayer insulating film. A method of manufacturing a semiconductor device, further comprising a step of forming a nitride film, wherein in the step (d), a portion of the silicon nitride film located above a peripheral circuit region is also selectively removed. 14. The method of manufacturing a semiconductor device according to claim 11, wherein in the step (c), a conductor protection film made of a silicon nitride film for protecting an upper surface of the conductor wiring is provided. A method of manufacturing a semiconductor device, further comprising forming a film, and forming a silicon nitride film as the sidewall insulating film in the step (e). 15. A step of forming a gate insulating film, a gate electrode, a gate wiring, and a source / drain region in a memory cell region and a peripheral circuit region of a semiconductor substrate (a).
(B) depositing a gate protective insulating film covering at least the gate electrode and the gate wiring; (c) depositing a first interlayer insulating film on a substrate; Forming a conductor wiring in contact with one of the source and drain regions of the memory cell transistor, and then depositing a sidewall insulating film on the substrate; (E) selectively removing only a portion of the first interlayer insulating film located above the peripheral circuit region; and a sidewall insulating film in the peripheral circuit region;
(F) etching back the gate protection insulating film in the peripheral circuit region to form insulator sidewalls on the side surface of the memory cell capacitance portion and the side surface of the gate electrode in the peripheral circuit region, respectively. (G) depositing a second interlayer insulating film on the substrate; connecting holes penetrating the second interlayer insulating film; and filling the connection holes with a source / drain region of the memory cell transistor. And (h) forming a plug member connected to the other side. 16. The method of manufacturing a semiconductor device according to claim 15, wherein after performing the step (c) and before performing the step (d), a silicon nitride film is formed on the first interlayer insulating film. A method of manufacturing a semiconductor device, characterized in that in the step (e), a portion of the silicon nitride film located above a peripheral circuit region is also selectively removed. 17. The method for manufacturing a semiconductor device according to claim 15, wherein in the step (d), a conductor protection film made of a silicon nitride film for protecting an upper surface of the conductor wiring is also formed. Forming a silicon nitride film as the sidewall insulating film.