JP2001068479A - Hetero-bipolar transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable low voltage operation and rapid operation while keeping reliability of a hetero-bipolar transistor high, by specifying average lattice strain of an Si, Ge and C-base second semiconductor layer whose band gap is smaller than that of an Si-base first semiconductor layer. SOLUTION: A second semiconductor layer 4 which comprises an SiGeC layer, has a band gap which is smaller than that of a first semiconductor layer 20 and has average lattice strain of 1.0% or less, is formed on a first conductivity first semiconductor layer 20 whose element is Si and which functions as a collector layer. A third semiconductor layer 5 which comprises Si and has a band gap which is larger than that of the second semiconductor layer 4 is further formed thereon, a conductor layer containing first conductivity impurities which comes into contact with a part of the semiconductor layer 5 is formed, a base layer 8a is formed by introducing second conductivity impurities to a part of the second semiconductor layer 4, first conductivity impurities in a conductive layer are diffused to the third semiconductor layer 5 by heat treatment, and an emitter diffusion layer 9a is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hetero bipolar transistor having a base layer including a SiGeC layer within a range where lattice distortion is small.

[0002]

2. Description of the Related Art Conventionally, at any one of junctions between an emitter, a base and a collector, a hetero barrier formed at a boundary between energy bands of two semiconductor materials having different band gaps is provided, and this hetero barrier is used. Hetero bipolar transistors (HBTs) that attempt to improve carrier accumulation and current amplification factor are taking advantage of their excellent high-frequency characteristics and are being used as active devices in the microwave / millimeter wave band. For example, HBTs using III-V group compound semiconductors such as GaAs have been most intensively researched and developed. In recent years, SiBT-based materials, which are IV-IV group compounds that can be formed on silicon substrates, have been used. HBT (SiGe-HBT) has attracted attention.
In addition, SiGe-HBT has a higher S than Si-BJT.
Attention has also been paid to the fact that a small band gap of a base layer made of an iGe layer enables operation at a low voltage.

Conventionally, as a SiGe-HBT for achieving a high speed, a graded composition base layer in which the Ge content of a SiGe base layer is gradually increased in a direction from an emitter layer side to a collector layer side has been proposed. (L. Harameet al., "Optimization of
SiGe HBT Technology for High Speed Analog and Mixe
d-Signal Applications, "IEDM Tech. Dig. 1993, p.7
1.), with a structure in which the Ge content of the base layer and the doping concentration of impurities in the base layer are increased, and the thickness of the base layer is made extremely thin (Reference Document 2) (A. Schuppen et al., "En.
hanced SiGe Heterojunction Bipolar Transistors wit
h 160 GHz-fmax, "IEDM Tech. Dig. 1995, p. 743.).

[0004] In the former transistor having a gradient composition base layer, carriers injected into the base layer are accelerated by an electric field generated by the gradient composition, and drift travel through the base layer. Since the traveling of the carrier by the drift electric field is faster than the traveling by the diffusion of the carrier, by the transistor having the gradient composition base structure,
Time required to travel through the base layer (base travel time)
, And good high-frequency characteristics are obtained.

On the other hand, the latter hetero-bipolar transistor includes a base layer having a narrow band gap and made of SiGe having a high Ge content and a uniform composition. By doping the base layer with a high-concentration carrier impurity, the base layer is made thinner while suppressing punch-through between the emitter and the collector, thereby shortening the base traveling time. In this case, since the band gap of the base layer is smaller than the band gap of the emitter layer, the built-in potential of the PN junction between the emitter and the base is reduced, so that a large collector current and sufficient high-frequency characteristics can be obtained at a low voltage. Can be.

[0006]

However, each of the above-mentioned conventional heterobipolar transistors has the following disadvantages.

First, in the hetero bipolar transistor having the above-described gradient composition base structure, it is necessary to increase the composition gradient in order to increase the drift electric field due to the gradient composition. That is, it is necessary to reduce the Ge content in the region in contact with the emitter layer in the base layer and increase the Ge content in the region in contact with the collector layer. For this reason, the region in contact with the emitter layer in the base layer is usually made of only Si without Ge. At this time, since the PN junction between the base and the emitter is a homo junction of silicon and silicon, low voltage operation cannot be expected. Further, in order to further shorten the base transit time and improve the high-frequency characteristics, it is necessary to further increase the Ge content in a region of the base layer in contact with the collector layer. However, in the SiGe layer formed on the Si substrate, if the Ge content is too large, dislocations occur in the base layer due to the difference in lattice constant between Si and Ge (lattice mismatch), thereby deteriorating reliability. Therefore, there is a limit to the increase in the Ge content. Reference 3
(SR Stiffler et.al., "The thermal stability of S
iGe films deposited by ultrahigh-vacuum chemical v
apor deposition, "J. Appl. Phys., 70 (3), pp. 1416-142
0,1991.), The upper limit of the practical Ge content used for the base layer of a hetero-bipolar transistor is 10%.
%. Therefore, it is currently difficult to further increase the frequency and lower the voltage by increasing the composition gradient in the base layer.

On the other hand, in the conventional heterobipolar structure using the latter uniform composition base, as described above, the critical film thickness at which dislocations occur due to the difference in lattice constant becomes a problem. In fact, SiGe described in Reference 2
Since the HBT has a high Ge content, the HBT is manufactured without using a process requiring a high-temperature treatment, and the generation of dislocations is suppressed. Therefore, it cannot be applied to a silicon process that requires a high-temperature process.
It is impossible to realize an embedded device such as an S device or an integrated circuit. Therefore, there is a limit to further low-voltage operation by further reducing the built-in potential.

An object of the present invention is to provide a means for reducing the amount of lattice distortion in the base layer even if the difference between the band gap of the collector layer or the average band gap of the emitter layer and the band gap of the base layer is increased. Accordingly, it is an object of the present invention to provide a hetero bipolar transistor which can operate at a lower voltage and operate at a higher speed while maintaining high reliability.

[0010]

According to the present invention, there is provided a heterobipolar transistor comprising: a first semiconductor layer made of a semiconductor material having Si as a component;
A second semiconductor layer composed of an upper layer, a center layer, and a lower layer composed of a semiconductor material having Ge and C as components and having a smaller band gap than that of the first semiconductor layer; A third semiconductor layer made of a semiconductor material having a band gap larger than that of the first semiconductor layer, and a hetero barrier is formed between the first semiconductor layer and the second semiconductor layer. And a collector layer formed on the first semiconductor layer and containing a first conductivity type impurity; a base layer formed on the second semiconductor layer and containing a second conductivity type impurity; And an emitter layer containing a first conductivity type impurity, wherein the second semiconductor layer has an average lattice strain of 1.0
% Or less.

Thus, for example, Si _1-xy Ge _x C _y
By adjusting the Ge and C contents of the second semiconductor layer represented by (the Ge content is x and the C content is y),
Low voltage operation can be realized by reducing the built-in potential of the PN junction between the emitter and the base, and operation speed can be improved by the gradient composition base structure. At this time, unlike the SiGe layer epitaxially grown on the Si layer, a strict upper limit of the Ge content is not caused for preventing generation of lattice defects due to lattice mismatch. That is, Si, Ge
And the second semiconductor layer having C as a component,
While suppressing the average lattice distortion caused by lattice mismatch with the first and third semiconductor layers made of Si or the like to 1.0% or less,
It is possible to increase the band gap difference between the first and third semiconductor layers. Therefore, it is possible to obtain a highly reliable heterobipolar transistor having excellent functions.

In the heterobipolar transistor, when the second semiconductor layer is subjected to compressive strain, the band gap of the second semiconductor layer made of SiGeC and the first semiconductor layer are reduced while reducing the C content. The difference from the band gap can be made sufficiently large, and the reliability can be improved and the function can be improved.

In the hetero bipolar transistor, the band gap of the second semiconductor layer is 1.04e
V or less, the band gap is 1.12 eV
, The band gap difference from Si is sufficiently large, and the above-described function can be exhibited.

In the above hetero-bipolar transistor, the first semiconductor layer is made of Si single crystal, and the second semiconductor layer has a composition of the second semiconductor layer of Si _1-xy Ge _x C _y (The content of Ge is x, C
Is represented by y), on a two-dimensional orthogonal coordinate system where the horizontal axis is the Ge content and the vertical axis is the C content, a straight line: y = 0.122x-0.032 A straight line: y = 0.1245x + 0.028 Straight line: y = 0.332x−0.0233 (C content is 22% or less) Straight line: y = 0.0622x + 0.0127 (C content is 22% or less) By having the composition of the region surrounded by the straight line, the lattice distortion can be suppressed to 1.0% or less.

In the above hetero-bipolar transistor, since the central layer of the second semiconductor layer has a uniform composition, a large band gap difference between the first and third semiconductor layers can be ensured.

In the hetero-bipolar transistor in which the central layer has a uniform composition, the C content in the upper layer of the second semiconductor layer gradually increases in the direction from the third semiconductor layer toward the central layer. In this case, a smoothly changing band structure with almost no band offset such as a notch at the emitter-base junction can be obtained, and a hetero-bipolar transistor having good high-frequency characteristics can be obtained.

In the hetero-bipolar transistor in which the center layer has a uniform composition, in the upper layer of the second semiconductor layer interposed between the center layer and the third semiconductor layer, the content of C and Ge Is increased in the direction from the third semiconductor layer to the central layer, a more smoothly changing band structure is obtained at the emitter-base junction.

In the hetero-bipolar transistor in which the central layer has a uniform composition, the C content in the lower layer of the second semiconductor layer decreases in the direction from the central layer to the first semiconductor layer. In this case, a smoothly changing band structure with almost no band offset such as a notch can be obtained at the base-collector junction.

In the hetero bipolar transistor in which the central layer has a uniform composition, the C and Ge contents in the lower layer of the second semiconductor layer decrease in the direction from the central layer to the first semiconductor layer. In this case, a band structure that changes more smoothly at the base-collector junction is obtained.

In the above-mentioned basic structure of the hetero bipolar transistor, in the central layer of the second semiconductor layer,
When the band gap decreases in the direction from the third semiconductor layer toward the first semiconductor layer, a function of accelerating carriers by an electric field in the base layer is obtained.
It is possible to obtain a hetero bipolar transistor in which the base transit time is reduced and which operates at high speed.

The following structure is used as a structure for reducing the band gap in the direction from the third semiconductor layer to the first semiconductor layer in the second semiconductor layer.

The third semiconductor layer is composed only of Si, and the composition of the upper layer of the second semiconductor layer changes continuously with the central layer, and the portion in contact with the third semiconductor layer is Si. The central layer and the upper layer of the second semiconductor layer such that the content of at least one of Ge and C increases in the direction from the third semiconductor layer toward the first semiconductor layer. What is necessary is just to make it have the composition which inclines.

In this case, in the central layer and the upper layer of the second semiconductor layer, by increasing the content ratio of Ge and C while keeping the content ratio of both constant, the function of accelerating carriers by an electric field is improved. Can be strengthened more.

In the hetero bipolar transistor in which the second semiconductor layer has a graded composition, the C content, or C and G, may be formed below the second semiconductor layer.
When the content of e decreases in the direction from the central layer toward the first semiconductor layer, as described above, it smoothly changes without a band offset such as a notch at the base-collector junction. A band structure can be obtained.

In the hetero bipolar transistor in which the second semiconductor layer has a graded composition, when the upper layer of the second semiconductor layer is made of Si containing at least one of Ge and C, Or C
May be changed in the direction from the third semiconductor layer to the first semiconductor layer.

The following is an example of a structure having such a gradient composition.

When the center layer of the second semiconductor layer has a composition that undergoes compressive strain, the C content is constant and G
e has a gradient composition in which the e content increases in the direction from the third semiconductor layer to the first semiconductor layer, but the Ge content is constant and the C content is from the third semiconductor layer to the third semiconductor layer. Although it has a gradient composition that decreases in the direction toward the first semiconductor layer, the Ge content increases and the C content decreases in the direction from the third semiconductor layer toward the first semiconductor layer. And a graded composition in which the contents of Ge and C increase in the direction from the third semiconductor layer to the first semiconductor layer.

In the case where the center layer of the second semiconductor layer has a composition which undergoes tensile strain, the C content is constant and the Ge content is changed from the third semiconductor layer to the first semiconductor layer. Has a gradient composition that decreases in the direction toward the substrate, and has a gradient composition in which the Ge content is constant and the C content increases in the direction from the third semiconductor layer toward the first semiconductor layer. Those having a gradient composition in which the content of Ge decreases and the content of C increases in the direction from the third semiconductor layer to the first semiconductor layer; 1
And the like having a gradient composition in which the Ge content increases and the C content increases in the direction toward the semiconductor layer.

As described above, by giving the center layer of the second semiconductor layer a gradient composition in a region having only one of the compressive strain and the tensile strain, the center layer made of SiGeC is lattice-matched. Since the SiGeC content changes without passing through such a region, it is possible to avoid problems such as occurrence of an opposite band gap gradient in the central layer of the second semiconductor layer.

It should be noted that even in a hetero-bipolar transistor in which the center layer of the second semiconductor layer has a graded composition, the C content,
Alternatively, it is preferable that the contents of C and Ge increase in the direction from the third semiconductor layer toward the central layer.

In the lower layer of the second semiconductor layer, it is preferable that the content of C, or the content of C and Ge, decreases in the direction from the central layer toward the first semiconductor layer.

According to the method of manufacturing a hetero bipolar transistor of the present invention, a SiGeC is formed on a first conductive type first semiconductor layer having Si as a component and functioning as a collector layer.
(A) forming a second semiconductor layer including a layer and having a band gap smaller than that of the first semiconductor layer and having an average lattice distortion of 1.0% or less;
Forming a third semiconductor layer containing at least Si and having a larger band gap than the second semiconductor layer (b).
Forming a conductor layer containing a first conductivity type impurity in contact with a part of the third semiconductor layer; and introducing a second conductivity type impurity into at least a part of the second semiconductor layer. (D) forming an emitter diffusion layer by diffusing a first conductivity type impurity in the conductor layer into the third semiconductor layer by heat treatment to form an emitter diffusion layer. Contains.

According to this method, when the above-mentioned hetero bipolar transistor is formed, the crystallinity of the second semiconductor layer containing Si, Ge and C has an average lattice distortion of 1.0.
%, It was confirmed that good crystallinity was maintained even after the heat treatment in step (e) was performed. That is, the diffusion of the first conductivity type impurity from the conductor layer makes it possible to provide the emitter diffusion layer only in a local portion of the third semiconductor layer, and the hetero bipolar transistor having excellent electrical characteristics such as high frequency characteristics. Can be formed.

An Si layer is used as the first semiconductor layer,
In the step (a), Si is used as the second semiconductor layer.
_{1-xy Ge x C y (} Ge x the content of the content of C y) layer is formed, in the step (b), it is preferable to form a Si layer as the third semiconductor layer.

In the step (a), the second semiconductor layer is formed on a two-dimensional orthogonal coordinate system in which the abscissa represents the Ge content and the ordinate represents the C content. -0.032 Straight line: y = 0.1245x + 0.028 Straight line: y = 0.332x-0.0233 (C content is 22% or less) Straight line: y = 0.0622x + 0.0127 (C content is 22 % Or less) is preferable.

In the step (b), the first conductivity type impurity is doped into the third semiconductor layer at the same time as the epitaxial growth, and the step (b) is performed while avoiding the influence of the impurity concentration in many regions. Together with the introduction of the impurity in e), the impurity concentration in the third semiconductor layer can be further increased.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS-Advantages of Forming Base Layer by SiGeC Layer-Before describing each embodiment, a hetero-bipolar transistor is formed by a SiGeC layer which is a ternary mixed crystal semiconductor containing Si, Ge and C. Advantages of forming the base layer will be described.

FIG. 18 is a characteristic diagram showing the relationship between the Ge content of the SiGe film formed on the Si layer in a conventional SiGe-HBT or the like, lattice strain, and critical film thickness. H
Considering that the minimum base layer thickness practical for BT is about 25 nm, it is understood that it is necessary to select a composition in which the lattice distortion is within 0.5% in the SiGe film.

On the other hand, regarding the band gap of the SiGeC ternary mixed crystal semiconductor, see Reference 4 (K. Brunner et.
l., "SiGeC: Band gaps, band offsets, optical proper
ties, and potential applications, "J.Vac.Sci.Techn
ol. B 13 (3), pp. 1701-1706, 1998). According to the report, the SiGeC ternary mixed crystal semiconductor is made of Si
It can be seen that a semiconductor layer having a smaller band gap than a single crystal and having a small lattice distortion can be formed by forming a SiGeC layer on a Si single crystal.

Here, FIG. 19 shows data obtained by the experiments of the present inventors, and has the general formula Si _1-xy Ge _x
For SiGeC crystal layer is represented by C _y, it is data indicating the crystallinity of the change when subjected heat treatment between 15sec and (RTA) under 950 ° C.. In the figure, the horizontal axis represents the Ge content, the vertical axis represents the C content, and the straight line represents the composition conditions under which the strain amount (including the compressive strain and the tensile strain) and the band gap are constant. I have. The circles in the figure indicate Ge, whose crystallinity was well maintained.
The C content indicates the value of the C content, and the X mark in the same figure indicates that the crystallinity of G is deteriorated.
The values of e and C contents are shown. As it can be seen from the figure, when the Si _1-xy Ge _x C _y crystal layer, even beyond strain 0.5%, better retention without crystallinity is lost if it is within 1.0% You can see that it is dripping. In FIG.
Although only data for a case where a compressive strain is generated are shown, in principle, a similar strain amount is considered to be a critical value for a tensile strain.

FIGS. 20A to 20D show Si _1-x Ge _x
Is a graph showing changes in X-ray diffraction spectrum by heat treatment in the composition of the crystal layer and Si _1-xy Ge _x C _y crystal layer. Among them, FIGS. 20A and 20D respectively show Ge
FIG. 20 (b) shows only the X-ray diffraction spectrum of the Si _1-x Ge _x crystal layer having a content of 13.2% and 30.5.
(C) shows the change in the X-ray diffraction spectrum of the Si _1-xy Ge _{x Cy} crystal layer and the Si _1-x Ge _x crystal layer at a Ge content of 21.5% and 26.8% by heat treatment. FIG. Si _1-xy G shown in FIGS. 20 (b) and 20 (c)
The composition of the e _x C _y crystal layer are included in the measurement point in FIG. 19.

For example, referring to FIG. 20A, the secondary, tertiary,... Diffraction peaks on both sides of the zero-order diffraction peak do not change much (do not collapse) even after the heat treatment. Therefore, it is considered that the crystallinity of the Si _1-x Ge _x crystal layer is kept relatively good. This composition has a Si _1- as shown in FIG.
It corresponds to the composition of the _x Ge _x crystal layer. FIG. 20 (d)
As shown in Fig. 5, when the Ge content becomes 30.5%, after the heat treatment, the secondary, tertiary, ... diffraction peak patterns on both sides of the zero-order diffraction peak are almost unknown. It is considered that the crystallinity of the Si _1-x Ge _x crystal layer has deteriorated. This composition has a Si _1-x Ge _x having a strain of 1.0% or more shown in FIG.
It corresponds to the composition of the crystal layer.

On the other hand, referring to FIG. 20 (b), the in Si _1-xy Ge _x C _y crystal layer the C content is 0.33%, the secondary on both sides of the 0 order diffraction peak, tertiary Since the diffraction peaks of,... Do not change much (have not collapsed) even after the heat treatment, Si _1-xy
The crystallinity of the Ge _x C _y crystal layer is kept relatively good. However, if the content of C is 0, i.e. Si _1-x Ge _x crystal layer, after heat treatment was carried out, the secondary on both sides of the 0 order diffraction peak, tertiary, ... is unclear diffraction peak pattern of This indicates that the crystallinity of the Si _1-x Ge _x crystal layer has deteriorated. The same applies to FIG.

FIG. 1 shows a ternary mixed crystal semiconductor of SiGeC.
Between the Ge and C contents and the band gap and lattice strain
It is a state diagram which shows an engagement. In the same figure, the horizontal axis contains Ge
The vertical axis represents the C content, and the amount of distortion (compression strain)
And tensile strain) and band gap
The constant composition conditions are indicated by straight lines. FIG.
9, supported by the data shown in FIGS.
As shown in FIG. 1, in FIG.
Lattice strain in the SiGeC layer on the Si layer is 1.0%
Within the conventional practical SiGe
(Ge content about 10%) smaller than the band gap
It is an area that can be removed. This region is _1-xy Ge_x C
_y In the SiGeC represented by
When the contents of x and C are y, the following four straight lines: y = 0.122x-0.032 straight line: y = 0.1245x + 0.028 straight line: y = 0.332x-0.0233 (Ge Including
Straight line: y = 0.0622x + 0.0127 (including Ge)
(The percentage is 22% or less). In the figure, the lattice distortion
A SiGeC layer with a linear composition marked 0%
It is lattice-matched with the underlying Si layer.

Therefore, in the hetero bipolar transistor including the emitter layer, the base layer, and the collector layer, the base layer is formed of SiGeC having the composition of the region indicated by the dot hatching in FIG. A narrow band gap base, which was a practical problem due to distortion, can be realized.

Therefore, according to the present invention, by selecting a SiGeC ternary mixed crystal semiconductor material as a material having a small band gap and a small lattice distortion in the base layer, high reliability, low voltage operation, A hetero bipolar transistor capable of high-speed operation can be realized.

FIG. 1 shows that the underlayer of the SiGeC layer is S
FIG. 3 is a phase diagram in the case of having an i-single composition.
Even if i contains some Ge or C, the lattice distortion of the SiGeC layer is 1.0% or less, and the SiGeC layer
As long as a large difference between the C layer and the band gap can be ensured, the same effect can be exerted.

-Example of Overall Structure and Manufacturing Process of Hetero-Bipolar Transistor-FIG. 2 shows one example to which the present invention can be applied, a hetero-type having a collector layer made of Si crystal and a base layer made of SiGeC crystal. FIG. 3 is a sectional view of a bipolar transistor.

As shown in FIG. 2, on the Si substrate 1,
A first active region Re1 and a second active region Re2 surrounded by the LOCOS film 2 are provided. A sub-collector layer 3a containing an n-type impurity is formed in the Si substrate 1, and the sub-collector layer 3a is formed between the first active region Re1 and the second active region Re2 in the Si substrate 1. Spans. Further, in the Si substrate 1, the sub-collector layer 3
a on top of the first layer formed by epitaxial growth.
Of the Si epitaxial layer 20, a collector layer 3b is provided in a first active region Re1 and a second active region Re2 is provided in the first active region Re1.
Is provided with a collector wall layer 3c. Further, on the first active region Re1 of the Si epitaxial layer 20, a SiGeC layer 4 as a second semiconductor layer and a Si layer 5 as a third semiconductor layer formed sequentially by epitaxial growth are formed. ing. However,
The SiGeC layer 4 and the Si layer 5 are single-crystal films on portions of the substrate where the Si epitaxial layer 20 is exposed, but are polycrystalline films on the LOCOS film 2. S
The region located above the collector layer 3b in the iGeC layer 4 is an intrinsic base layer 8a containing a p-type impurity, and the regions beside the intrinsic base layer 8a are the SiGeC layers 4, 4, the Si layer 5, and the Si substrate. An external base layer 8b is formed over each of the portions 8x, 8y, and 8z in 1. Further, an emitter layer 9 containing an n-type impurity is formed in a region of the Si layer 5 located above the intrinsic base layer 8a.

Here, the intrinsic base layer 8a and the collector layer 3
Although the boundary with b is shown by a single line in FIG. 2, the PN junction serving as the boundary between the base and the collector actually changes according to the state in which the impurity is introduced.
Therefore, the boundary between the intrinsic base 8a and the collector layer 3b hardly coincides with the boundary between the Si epitaxial layer 20 and the SiGeC layer 4. Intrinsic base layer 8
The same applies to the positional relationship between the boundary between the a-emitter layer 9 and the boundary between the SiGeC layer 4 and the Si layer 5. The positional relationship between the boundary between the Si epitaxial layer 20, the SiGeC layer 4, and the Si layer 5 and the boundary between the collector layer 3b, the intrinsic base layer 8a, and the emitter layer 9 will be described later in detail.

Further, a BSG (Boron Silicate Glass) film 6 containing a high concentration of p-type impurities is provided on the Si layer 5, and the BSG film is provided on the external base layer 8b.
Boron, which is a p-type impurity diffused from the film 6, is doped. An insulator sidewall 10 is formed on a side surface of the opening of the BSG film 6, and an emitter electrode 11 made of polysilicon containing a high-concentration n-type impurity (for example, phosphorus) is formed in the opening. . Then, a high-concentration emitter layer 9a formed by diffusing an n-type impurity (for example, phosphorus) from the emitter electrode 11 into the emitter layer 9 is formed. The emitter layer 9 has n
Type impurities (phosphorus or arsenic)
It may be introduced by -situ doping.

The second active region Re2 in the Si substrate 1
A collector electrode 12 containing an n-type impurity (for example, phosphorus) is formed on the substrate. On the collector wall layer 3c, a collector contact layer 14 containing an n-type impurity diffused from the collector electrode 12 is formed.

Further, an interlayer insulating film 13 made of silicon oxide is formed on the main surface of the substrate, and the above-described emitter electrode 11 and Si layer 5 are formed through contact holes formed in this interlayer insulating film 13. , Collector wires 12 connected to Al wirings 21, 22, 23, respectively. Here, the polycrystalline film portion of the Si layer 5 and the SiGeC layer 4 is connected to the external base layer 8b formed in the crystal film portion, and functions as a base electrode. ing.

The hetero-bipolar transistor in this example has an impurity-doped BSG having an opening on SiGeC layer 4 and Si layer 5 grown epitaxially.
A film 6 is formed, and boron as a p-type impurity is diffused from the BSG film 6 to form an external base layer 8b.
An n-type impurity is diffused into the emitter layer 9 from the emitter electrode 11 formed in the opening of the SG film 6 to form a high-concentration emitter layer 9a. That is, the external base layer 8b
And the high-concentration emitter layer 9a are formed in the opening of the BSG film 6 in a self-aligned manner. However, the external base layer 8b and the high-concentration emitter layer 9a are not necessarily both BS
It is not necessary to form the opening in the G film 6 in a self-aligned manner.

Next, a method for manufacturing the hetero bipolar transistor according to the present embodiment will be described with reference to FIGS.

First, in the step shown in FIG. 3A, a sub-collector layer 3a in which a high concentration n-type impurity is implanted is formed in a Si substrate 1, and then a low concentration n-type impurity is formed by LP-CVD.
The LOCOS film 2 surrounding the first and second active regions Re1 and Re2 is formed on the Si epitaxial layer 20 containing the type impurity by epitaxial growth. The epitaxially grown Si epitaxial layer 20 becomes the collector layer 3b in the first active region Re1, and the collector wall layer 3c in the second active region Re2.
It has become.

Next, in a step shown in FIG. 3B, a p-type S layer having a thickness of about 50 nm doped with boron in portions other than the upper and lower ends by UHV-CVD is formed on the entire surface of the substrate.
An iGeC layer 4 and a non-doped Si layer 5 having a thickness of about 20 nm are sequentially formed by epitaxial growth. At this time, the SiGeC layer 4 and the Si layer 5 are single-crystal films on portions where the silicon surface is exposed, and are polycrystalline films on the LOCOS film 2. At this time, when growing the SiGeC layer 4, the flow rate of disilane (Si ₂ H ₆ ) was set to 7.5 ml / min. In the UHV-CVD apparatus. And the flow rate of germane (GeH ₄ ) was 20 ml / min. , The flow rate of methylsilane (10% SiH ₃ CH ₃ / H ₂ ) was 10 ml
/ Min. The growth temperature is 500 ° C., and the growth pressure is about 0.53 Pa (4 × 10 ⁻³ Torr). Also,
When growing the Si layer 5 is in a UHV-CVD apparatus, a flow rate of 7.5 ml / mi of disilane (Si ₂ H ₆₎
n. At a growth temperature of 550 ° C. and a growth pressure of about 0.
27 (2 × 10 ⁻³ Torr). And SiGe
By controlling the timing of introducing boron when the C layer 4 is epitaxially grown, the positional relationship between the collector / base junction and the boundary between the Si layer 5 and the SiGeC layer 4 can be appropriately adjusted as described later. it can.

When the Si layer 5 (Si single crystal film and Si polycrystal film) is epitaxially grown, a relatively high concentration of n-type impurity (phosphor or arsenic) may be introduced by in-situ doping. Good.

Next, in the step shown in FIG.
The remaining portions of the C layer 4 and the Si layer 5 are removed by dry etching except for the portion functioning as the active base layer and the extraction base electrode.

Next, in a step shown in FIG. 3D, an approximately 200 nm thick BS containing about 8% boron is formed on the entire surface of the substrate.
After depositing a G (Boron Silicate Glass) film 6 by a normal pressure CVD method, the BSG film 6 is patterned by a photolithography process and a dry etching process,
The second active region Re2 of the SG film 6 is entirely removed, while an opening 6a for forming an emitter electrode is formed on the first active region Re1 of the BSG film 6.

Next, in the step shown in FIG. 3E, a protective nitride film 7 having a thickness of about 100 nm is deposited on the entire surface of the substrate by the CVD method. When boron is diffused from the BSG film 6 in the next step, boron escapes from the BSG film 6 into the gas phase, adheres to the exposed silicon surface, and diffuses into the substrate. It works to prevent

Next, in the step shown in FIG.
(Rapid Thermal Anneal) method, heat treatment is performed at 950 ° C. for 10 seconds to remove boron in the BSG film 6 from the Si layer 5.
Out of the BSG film 6 (that is, the opening 6
a), the BS of the SiGeC layer 4
It is diffused to a portion located below the G film 6 and a portion of the collector layer 3b located below the BSG film 6. By this step, BSG of the Si layer 5 and the collector layer 3b is
The portions 8x and 8z located below the film 6 (that is, the openings 6a
) Becomes p-type, and the SiGeC layer 4
Among them, the portion 8y located below the BSG film 6 has a higher p-type impurity concentration and lower resistance. As a result, in the portion located around the opening 6a, the Si layer 5, S
Each part 8x, 8 in iGeC layer 4 and collector layer 3b
An external base layer 8b covering y and 8z is formed. At this time, as shown in FIGS. 19 and 20 (a) to (d) described above, the crystallinity of the SiGeC layer of the present invention is maintained well without deterioration.

Next, in the step shown in FIG. 3G, the protective nitride film 7 is etched back by anisotropic dry etching to form sidewalls 10 on the side surfaces of the BSG film 6. The sidewall 10 is for ensuring a sufficient withstand voltage between the high-concentration emitter layer formed later and the external base layer.

Next, in the step shown in FIG. 3H, after a polysilicon film doped with a high concentration of phosphorus to be an emitter electrode and a collector electrode is deposited by LPCVD,
This polysilicon film is patterned by dry etching to form an emitter electrode 1 on the first active region Re1.
1 and a collector electrode 12 is formed on the second active region Re2.

Next, in a step shown in FIG. 3I, an interlayer insulating film 13 made of silicon oxide is deposited by a CVD method.

Next, in the step shown in FIG.
By performing a heat treatment (RTA) at 15 ° C. for 15 seconds, phosphorus is diffused from the emitter electrode 11 to the upper end portions of the emitter layer 9 and the SiGeC layer 4 to form a high-concentration emitter layer 9a, and from the collector electrode 12 to the inside of the collector wall layer 3c. The collector contact layer 14 is formed by diffusing phosphorus. Also at this time, the above-mentioned FIGS.
As shown in (d), the crystallinity of the SiGeC layer of the present invention is maintained well without deterioration.

Next, in the step shown in FIG. 3 (k), the emitter electrode 11 is formed on the interlayer insulating film 13 by dry etching.
After forming contact holes reaching the Si layer 5 and the collector electrode 12, the Al wirings 21, 22, and 2 are formed in each contact hole and over the interlayer insulating film 13.
Form 3

In each of the following embodiments, the structure shown in FIG. 2 and the process shown in FIGS. 3A to 3K will be described with reference to the characteristics such as the composition, tensile strain, and band gap shown in FIG. The structure of the emitter, the base and the collector will be described by taking a hetero bipolar transistor formed by the above as an example. However, the structure and manufacturing process of the hetero bipolar transistor of the present invention are the same as those shown in FIG. 2 and FIG.
The present invention is not limited to the manufacturing steps shown in FIGS.

(First Embodiment) First, the intrinsic base layer 8
a is a SiG layer composed of a SiGeC layer 4 having a uniform composition.
A first embodiment regarding eC-HBT will be described.

FIGS. 4A to 4C respectively show an energy band structure of a conventional NPN-type Si-BJT and a conventional NPN-type SiGe-HB having a uniform composition base layer.
Energy band structure of T, homogeneous composition Si according to the present invention
It is a band figure which shows the energy band structure of NPN type SiGeC-HBT which has a GeC base layer, respectively.

As shown in FIG. 4A, in the conventional NPN type Si-BJT, the potential difference A1 between the conduction bands between the emitter and the base and the potential difference B1 between the valence bands are equal to each other. The potential difference A2 between the conduction bands between the base and the collector and the potential difference B2 between the valence bands are equal to each other.

On the other hand, as shown in FIG. 4B, in the conventional NPN-type SiGe-HBT, the potential difference B1 between the valence bands is larger than the potential difference A1 between the conduction bands between the emitter and the base. . In other words, the built-in potential can be reduced. Therefore, the voltage required to secure a constant flow rate of carriers (here, electrons) flowing from the emitter to the base can be reduced, and low-voltage operation can be realized.

However, as described above, the Ge content of the SiGe base layer is generally 10% or less in order to suppress the occurrence of dislocation due to lattice mismatch. Therefore, the band gap difference between the SiGe layer and the Si layer cannot be so large, and the potential differences B1, B2 between the valence bands and the potential differences A1, A between the conduction bands.
Also, the differences (B1-A1) and (B2-A2) from 2 cannot be so large. Therefore, there is a limit to low-voltage operation.

On the other hand, as shown in FIG. 4C, in the NPN type SiGeC-HBT of the present invention, the emitter layer 9
The difference (B1-A1) between the potential difference B1 between the valence bands and the potential difference A1 between the conduction bands between the intrinsic base layer 8a and the intrinsic base layer 8a-collector layer 3b
The difference (B2-A2) between the potential difference B2 between the valence bands and the potential difference A2 between the conduction bands between them can be made larger than that of the conventional NPN-type SiGe-HBT. That is, in the present embodiment, the composition of the SiGeC layer 4 including the intrinsic base layer 8a is set to the composition in the dot-hatched region in FIG. 1 to reduce the lattice distortion in the intrinsic base layer 8a. It can be suppressed to 1.0% or less, and the band gap of the intrinsic base layer 8a can be made smaller than that of a conventional practical SiGe layer (Ge content is about 10%). Therefore, the above-described low-voltage operation can be more remarkably advanced.

Here, the conventional Si-BJT and the conventional Si-BJT
The difference in band gap between Si, SiGe, and SiGeC constituting the base layer in the Ge-HBT and the SiGeC-HBT of the present invention will be described.

For example, in the present embodiment, the composition of SiGeC constituting the base layer is such that the Ge content is 30% and the C content is 2.1%. As shown in FIG. 1, in this composition, the lattice strain is 1.0% or less. Comparing the band gaps of Si, practical SiGe, and SiGeC in the present embodiment, Si: 1.12 eV SiGe (Ge Content: 10%): 1.04 eV SiGeC (Ge content: 30%, C content: 2.1%): 0.95 eV. Therefore, SiGe having such a composition
A hetero bipolar transistor having an intrinsic base layer constituted by a C layer can realize a base layer having a smaller band gap as compared with a bipolar transistor having a base layer constituted by not only Si but also SiGe. As a result, FIG.
As shown in FIG. 5, the difference (B1-A1) between the potential difference B1 between the valence bands between the emitter layer 9 and the intrinsic base layer 8a and the potential difference A1 between the conduction bands and the difference between the intrinsic base layer 8a and the collector layer 3b. In this case, a difference (B2-A2) between the potential difference B2 between the valence bands and the potential difference A2 between the conduction bands is extremely large, and a low-voltage-operated heterobipolar transistor can be obtained.

FIG. 5 is a graph showing the dependence of the base-collector current on the base voltage (Gummel plot) of the hetero-bipolar transistor according to this embodiment according to the conventional Si-BJT, S
It is a figure shown in comparison with iGe-HBT. By providing a base layer made of SiGeC having a small band gap in the hetero-bipolar transistor as in the present embodiment, the built-in potential at the PN junction between the emitter and the base is reduced, which is lower than that of the conventional uniform composition SiGeHBT. A large collector current can be obtained with a voltage. That is, the SiGeC-HBT of the present embodiment
, An unprecedented low-voltage operation is realized.

FIGS. 21 and 22 show that the Ge content was 2%.
Si at 1.5% and 26.8% _1-x Ge_x Crystal layer
And Si_1-xy Ge_x C_y Having a crystal layer as a base layer
V at common emitter of bipolar transistor_CE 
-I_C Characteristics (collector-emitter voltage and collector current
FIG. You can see from Figures 21 and 22
Yeah, Si_1-x Ge_x Bipolar transformer using crystal layer
In a transistor, the collector current IC is almost flat
Is almost nonexistent, and the collector current V_CEDepend
Very viable. That is, this bipolar transistor
Difficulty performing normal amplification
I understand. That is, Si_1-x Ge_x Ba using crystal layer
In the bipolar transistor, the Ge content is 10%.
Is a practical limit.

[0079] In contrast, in the bipolar transistor using the Si _1-xy Ge _x C _y crystal layer, there is a region comprising a collector current I _C is almost flat, V _CE dependence of the collector current is not so large . Therefore, the bipolar transistor using the Si _1-xy G _x C _y crystal layer of the present embodiment as the base layer is stable even if the Ge content is an extremely high value of 21.5% or 26.8%. It is shown that a bipolar operation can be performed.

-Structure near the boundary between the Si layer and the SiGeC layer-Here, the emitter layer 9 containing phosphorus and boron (B) of the NPN heterobipolar transistor according to the present embodiment.
Base layer 8a containing phosphorus and collector layer 3b containing phosphorus
Formation position, Si epitaxial layer 20, SiGeC
FIG. 6 shows the relationship between the formation positions of the layer 4 and the Si layer 5.
This will be described with reference to FIGS. 9 (a) and 9 (b) to 9 (a) and 9 (b). 6 (a) and 6 (b) to 9 (a) and 9 (b), the formation positions of the Si epitaxial layer 20, the SiGeC layer 4 and the Si layer 5 are distinguished by the presence or absence of Ge and C, and the emitter layer 9 is formed. , Intrinsic base layer 8a and collector layer 3
The formation position of b is distinguished by the presence or absence of boron. That is, G is applied to the Si epitaxial layer 20 and the Si layer 5.
Since neither e nor C is introduced, four SiGeC layers in which the Ge content and the C content are described;
The boundary between the Si epitaxial layer 20 and the Si layer 5 is clearly shown. Further, since boron is not introduced into the emitter layer 9 and the collector layer 3b, the boundary between the intrinsic base layer 8a in which the boron concentration profile is described and the emitter layer 9 and the collector layer 3b is clearly shown. . 6 (a), 7 (a), 8 (a) and 9 (a), the concentration of phosphorus introduced into the emitter layer 9 and the collector layer 3b is not described.

FIGS. 6 (b), 7 (b), 8
9B and FIG. 9B show only the shapes of the conduction band edge and the valence band edge over the emitter layer, the intrinsic base layer, and the collector layer.

FIG. 6A shows a SiG having a uniform composition as a whole.
The Si epitaxial layers 20 and S of the hetero bipolar transistor in which the eC layer 4 is provided and boron for forming the base layer 8a is wider than the SiGeC layer 4, that is, doped in the Si epitaxial layers 20 and 5.
FIG. 4 is a diagram showing a relationship between the position of an i-layer 5 and the positions of an intrinsic base layer 8a, an emitter layer 9, and a collector layer 3b. FIG.
FIG. 6B is an energy band diagram of the transistor having the impurity profile shown in FIG. FIG.
As shown in (b), there are an emitter-base junction and a base-collector junction outside the SiGeC layer 4 and the Si-S
When the heterojunction interface between iGeCs is formed as a steep interface in a stepwise manner, a parasitic barrier as shown in FIG. 6A occurs at each junction, hindering the traveling of carriers and deteriorating high-frequency characteristics. Let it. In addition, the voltage required for injecting carriers from the emitter increases, which hinders lowering the voltage. This is because the silicon emitter layer and the silicon collector layer having a large band gap are p-type. Therefore, it is not appropriate to form the intrinsic base layer 8a or the SiGeC layer 4 over a wide range.

FIG. 7A shows a SiG having a uniform composition as a whole.
The position of the Si epitaxial layer 20 and the Si layer 5 of the hetero bipolar transistor in which the eC layer 4 is provided and boron for forming the base layer 8a is doped only in the SiGeC layer 4, the intrinsic base layer 8a, the emitter layer 9 and FIG. 9 is a diagram showing a relationship with a position of a collector layer 3b. FIG. 7 (b)
FIG. 8 is an energy band diagram of a transistor having the impurity profile shown in FIG. As shown in FIG. 7B, in this case, no parasitic barrier is formed in the hetero barrier as shown in FIG. 7A, but a notch is generated in the depletion layer region of each junction. This notch also becomes a factor that hinders the traveling of carriers (here, electrons). This is not seen in the conventional SiGe-HBT. For a conventional Si / SiGe heterojunction, the band gap difference is mainly due to the band offset Δ in the valence band.
It appears as Ev, and there is almost no potential step in the conduction band. On the other hand, in the case of the Si / SiGeC heterojunction, a band offset ΔEc also occurs in the conduction band. In addition, the conduction band offset generated in the Si / SiGeC heterojunction increases as the C content increases. Therefore, the flow of carriers (electrons in this case) from the emitter layer 9 to the collector layer 3b via the intrinsic base layer 8a is not so much inhibited, but the flow of carriers is slowed down by the amount of carriers accumulated in the parasitic notch. That is, the structure shown in FIG. 7A is preferable in that boron is introduced only into the SiGeC layer 4, but the C content and the Ge content of the SiGeC layer 4 are kept constant and the SiGeC layer 4 is entirely formed. It is not appropriate to have a uniform composition.

Note that a p-type impurity such as boron is
Even if the p-type region extends outside the C layer 4, the p-type region is SiGeC because the region into which the n-type impurity is introduced and the region into which the p-type impurity is introduced overlap.
What is necessary is just to be included in the layer 4.

FIG. 8A shows that the central layer 4a has a uniform composition,
The lower layer 4b and the upper layer 4c, which are both end regions, are provided with the SiGeC layer 4 having a gradient composition, and boron for forming the base layer 8a is doped only in the SiGeC layer 4 into the Si epitaxial layer 20 of the hetero bipolar transistor. The position of the Si layer 5, the intrinsic base layer 8a and the emitter layer 9
FIG. 4 is a diagram showing a relationship between the position of a collector layer 3b. S
In the lower layer 4b of the iGeC layer 4, the Ge content and the C content gradually decrease in the direction from the central layer 4a toward the Si epitaxial layer 20. In the upper layer 4c of the SiGeC layer 4, the Ge content and the C content
From the central layer toward the central layer. The intrinsic base layer 8a, which is the region where B is introduced,
The e content and the C content are contained in the central layer 4a having a uniform composition.

However, the change of the Ge content or the C content may be a step-like change instead of a continuous change. The same applies to each embodiment described later.

FIG. 8B is an energy band diagram of a transistor having the impurity profile shown in FIG. As shown in FIG. 8B, in this case, neither a parasitic barrier nor a parasitic notch appears in the hetero barrier. That is, G
As the e content and the C content gradually change, no clear potential step occurs at the conduction band edge, and the energy band structure shows a smooth transition of the conduction band edge. This is because in the lower layer 4b and the upper layer 4c of the SiGeC layer 4, C which causes a band offset at the conduction band edge is gradually changing. as a result,
The action of carriers (here, electrons) flowing from the emitter to the collector via the intrinsic base is not hindered, and the flow of carriers is not slowed down. That is,
The intrinsic base layer 8a is included in the central layer 4a of the SiGeC layer 4, and in the lower layer 4b of the SiGeC layer 4 adjacent to the Si epitaxial layer 20, the Ge content and the C content are changed from the central layer 4a to the Si epitaxial layer 20.
Is gradually reduced in the direction toward the SiGeC layer 4 in the conduction band of the hetero bipolar transistor.
Therefore, it is possible to effectively prevent the occurrence of a parasitic barrier or a notch in a portion connected to the Si epitaxial layer 20 from the above. Similarly, the intrinsic base layer 8a is included in the central layer 4a of the SiGeC layer 4, and the S
In the upper layer 4c adjacent to the i-layer 5, the Ge content and C
By gradually increasing the content in the direction from the Si layer 5 toward the central layer 4a, it is possible to effectively prevent the occurrence of a parasitic barrier or a notch in a portion from the SiGeC layer 4 to the Si layer 5 in the conduction band of the hetero bipolar transistor. Can be prevented.

Even if the intrinsic base layer 8a, which is a region where B is introduced, straddles both ends 4b and 4c of the SiGeC layer 4, as long as the intrinsic base layer 8a does not protrude from the SiGeC layer 4, the parasitic barrier remains. It does not occur, and the occurrence of notches can be suppressed.

The lower layer 4b and the upper layer 4 of the SiGeC layer 4
In c, the Ge content and the C content do not necessarily have to increase linearly as shown in FIG. 8A, and may have some bending or the like. In particular, the intrinsic base layer 8
When “a” is included in the central layer 4 a of the SiGeC layer 4, even if there is a step-like portion in the shape in which the Ge content and the C content change in the end regions 4 b and 4 c of the SiGeC layer 4. Good.

FIG. 9A shows that the central layer 4a has a uniform composition and the lower layer 4b and the upper layer 4c have the graded composition (only C) of the SiGeC layer 4, and the boron for forming the base layer 8a is Si.
FIG. 3 is a diagram showing the positions of the Si epitaxial layer 20 and the Si layer 5 and the positions of the intrinsic base layer 8a, the emitter layer 9, and the collector layer 3b of the hetero bipolar transistor doped only in the GeC layer 4. Lower layer 4 of SiGeC layer 4
In b, the Ge content is constant, and the C content gradually decreases in the direction from the Si epitaxial layer 20 toward the central layer 4a. In the upper layer 4c of the SiGeC layer 4, the Ge content is constant and the C content gradually increases in the direction from the Si layer 5 toward the central layer 4a. The intrinsic base layer 8a in which B is introduced is included in the central layer 4a having a uniform composition in which the Ge content and the C content are constant.

FIG. 9B is an energy band diagram of a transistor having the impurity profile shown in FIG. 9A. As shown in FIG. 9B, in this case, neither a parasitic barrier nor a parasitic notch appears in the hetero barrier. That is, C
When the content gradually changes, no clear potential step occurs at the conduction band edge, and the energy band structure shows a smooth transition of the conduction band edge. this is,
This is because in the lower layer 4b and the upper layer 4c of the SiGeC layer 4, C causing a band offset at the conduction band edge is gradually changing. As a result, the action of carriers flowing from the emitter to the collector via the intrinsic base is not hindered, and the flow of carriers is not slowed down. That is, the intrinsic base layer 8a is replaced with the SiGeC layer 4
In the lower layer 4b of the SiGeC layer 4 adjacent to the Si epitaxial layer 20, the C content is constant even if the Ge content is constant.
By gradually decreasing in the direction from a to the Si epitaxial layer 20, it is possible to effectively prevent the occurrence of a parasitic barrier or a notch in a portion connecting the SiGeC layer 4 to the Si epitaxial layer 20 in the conduction band of the hetero bipolar transistor. be able to. Similarly, the intrinsic base layer 8a is included in the central layer 4a of the SiGeC layer 4, and in the upper layer 4c of the SiGeC layer 4 adjacent to the Si layer 5, the C content is reduced even if the Ge content is constant. 5 from the SiGeC layer 4 to the Si layer 5 in the conduction band of the hetero-bipolar transistor.
, The occurrence of a parasitic barrier or a notch in the portion leading to the above can be effectively prevented.

Even if the intrinsic base layer 8a, in which B is introduced, straddles the lower layer 4b and the upper layer 4c of the SiGeC layer 4, a parasitic barrier does not occur as long as it does not protrude from the SiGeC layer 4. And notches can also be suppressed.

As described above, the SiGeC layer 4 and the Si layer 5
Alternatively, a gradient composition in which the C content and the Ge content gradually change at the heterojunction interface with the Si end crystal film 20 does not hinder the movement of carriers (electrons), It is possible to form a practical heterobipolar transistor having excellent high-frequency characteristics and operating at a low voltage without causing an increase.

The lower layer 4b and the upper layer 4b of the SiGeC layer 4
In c, the C content does not necessarily need to increase linearly, and may have some bending. In particular,
When the intrinsic base layer 8a is included in the central layer 4a of the SiGeC layer 4, the lower layer 4b,
There may be a step-like portion in the profile in which the content in the upper layer 4c changes.

In this embodiment, the intrinsic base layer 8a
Has a Ge content of 30%, a C content of 2.1% and a balance of S
SiGeC made of i (Si _0.679 Ge _0.30 C _0.021 )
It consists of. When a SiGeC layer having this composition is epitaxially grown on a Si layer, SiGeC
The layer is under a compressive strain of about 1.0%.
The reason for selecting such a composition in a state subjected to the compressive strain is that the system subjected to the compressive strain has a low Ge content and a low C content as compared with the lattice matching system. Lattice matched S with high Ge or C content
This is because a band gap similar to the band gap of the iGeC layer can be obtained. Specifically, the band gap of the Si _0.679 Ge _0.30 C _0.021 layer subjected to the compressive strain in this embodiment is 0.95 eV, but when a band gap as small as this is realized by the lattice matching system,
It is necessary to make the Ge content 42% and the C content 5.1%. That is, it is necessary to increase both the Ge content and the C content, and there is a possibility that the crystallinity is deteriorated with the increase in the C content. In addition, the above-mentioned notch is likely to occur when the C content increases.

FIG. 10 is a simplified state diagram of FIG. 1 described above, and is a state diagram showing a region that receives a compressive strain of 1.0% or less. Then, in the region Ra with dot hatching in FIG. 10, the lattice distortion does not include the lattice matching condition.
This is a region that receives a compression strain of 0% or less. As described above, in order to provide the intrinsic base layer with a band gap small enough to exhibit an effective effect while suppressing an increase in the C content, the region Ra shown by dot hatching in FIG. It is desirable to form the base layer using a SiGeC layer having the following composition.

As described above, in the hetero bipolar transistor having the SiGeC layer 4 formed by epitaxial growth on the Si epitaxial layer 20,
The SiGeC layer 4 is made of SiGeC having a uniform composition including Ge and C under the condition that the band gap becomes small within 1.0% of lattice strain, provided with the intrinsic base layer 8a included in the iGeC layer 4. Thus, a hetero-bipolar transistor which can operate at a low voltage and has a high operation speed can be realized. In addition, such Si /
Since a SiGeC-based heterobipolar transistor can be easily formed by using a silicon process that is currently widely used, it can be easily integrated on a silicon substrate.

In this embodiment, the collector layer 3b and the emitter layer 9 are made of a crystal having a single Si composition, but the present invention is not limited to this embodiment. For example, the Si epitaxial layer 20,
Even if Ge or C is included in the Si layer 5, as long as the lattice distortion of the SiGeC layer 4 is 1.0% or less, the same effect as in the present embodiment can be exerted.

(Second Embodiment) Next, the intrinsic base layer 8
a is a SiGeC- composed of a gradient composition SiGeC-
A second embodiment relating to the HBT will be described.

FIGS. 11A to 11C are energy band diagrams of a conventional SiGe-HBT having a base layer having a gradient composition, and energy bands of a SiGeC-HBT having a base layer having a gradient composition according to the present embodiment. FIG. 3 is a diagram showing the Ge content, the C content, and the B (boron) concentration of the SiGeC-HBT of the present embodiment.

As shown in FIG. 11A, a conventional SiG
In an e-hetero bipolar transistor, for example, the Ge content at the end of the base layer contacting the emitter layer is the smallest (eg, 0%), and the Ge content at the end of the base layer contacting the collector layer is the largest (eg, 10%).
%), The band gap of the portion in contact with the emitter layer in the SiGe base layer is a maximum value C1,
The band gap of the portion in contact with the collector layer in the SiGe base layer can be configured to have the minimum value C2. In the base layer made of SiGe having such a gradient composition, an electric field is generated which accelerates carriers in the direction toward the collector layer due to the inclination of the conduction band edge. In the case of such drift traveling, the traveling speed is higher than the traveling due to carrier diffusion, so that the operation speed of the hetero bipolar transistor can be further improved. However, S with a conventional tilted base structure
In the iGe-HBT, the Ge content of the portion in contact with the collector in the base layer could be increased only up to about 20% due to the restriction that the average lattice strain was 0.5%. It was difficult to reduce the value C2 to 0.97 eV or less. Therefore, the degree of inclination of the conduction band edge in the base layer is also (1.
12−0.97) (eV) /t=0.15 eV / t (t
Cannot be larger than the thickness of the base layer).

On the other hand, as shown in FIGS. 11B and 11C, SiGe including the intrinsic base layer 8a of this embodiment is used.
The central layer 4a of the C layer 4 has a Ge content and a C content of 0 (that is, a composition of Si alone) in a portion in contact with the Si layer 5 (emitter layer), and the Si crystal film 20 (collector layer).
In the portion in contact with, the Ge content is 40% and the C content is 1%. Then, in the SiGeC layer 4,
The structure is such that the Ge content and the C content increase linearly and greatly in the direction from the Si layer 5 to the Si epitaxial layer 20. However, the Ge in the SiGeC layer 4
The ratio between the content and the C content is kept constant (40: 1). In the lower layer 4b of the SiGeC layer 4, G
The e content and the C content gradually decrease in the direction from the central layer 4a toward the Si epitaxial layer 20. However, in the present embodiment, the SiGeC layer 4 includes Si
Since the portion in contact with the layer 5 has a single Si composition, the central layer 4
a and the upper layer 4c have a continuous composition and are integrated.

In this case, the band gap of the SiGeC layer having a Ge content of 40% and a C content of 1.0% is 0.83.
eV. Therefore, (1.12-0.83) (e
V) /t=0.29 eV (290 meV) / t (t is the thickness of the base layer), and the slope of the conduction band edge can be realized. The inclination of the conduction band edge in the SiGeC layer 4 can be further increased by changing the Ge content and the C content. Therefore, in the intrinsic base layer composed of the SiGeC layer of the present invention, the average lattice distortion (1.0%) that does not cause the generation of dislocations.
The inclination of the band gap can be further increased within the range of (maximum lattice distortion 2.0%).

That is, according to the hetero bipolar transistor of the present embodiment, by adjusting the Ge content and the C content, the band gap of the portion of the intrinsic base layer 8a in contact with the collector layer while suppressing the lattice distortion in the intrinsic base layer 8a. Can be made extremely small, it is possible to realize an HBT having a high degree of inclination in which the band gap decreases in a direction from the emitter side to the collector side and having a high function of accelerating carriers by an electric field.

In particular, as in the present embodiment, the SiGeC layer 4 is formed so that the Ge content and the C content in the direction from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side).
By using a gradient composition structure in which the content increases linearly, it is possible to realize an HBT having a high gradient electric field acceleration function in which the band gap decreases linearly in the direction from the emitter side to the collector side. it can. Specifically, due to the composition of the SiGeC layer 4 as described above, the lattice distortion of the portion of the SiGeC layer 4 that is in contact with the Si layer 5 is 1.2%. This value is a value larger than the average lattice distortion of 1.0% so as not to cause the above-described dislocation. However, when the SiGeC layer 4 constituting the intrinsic base layer 8a has a graded composition structure, the average lattice strain over the entire SiGeC layer 4 is an important value. In the SiGeC layer 4 of the present embodiment, the average lattice strain of the SiGeC layer 4 is 0.6.
%, Which is 1.0% or less, so that dislocations do not occur in the intrinsic base layer 8a, and there is no problem. Then, SiG forming the intrinsic base layer 8a
By making the eC layer 4 have such a gradient composition structure,
Since a band gap change of as much as 290 meV can be obtained from the emitter side end to the collector side end of the SiGeC layer 4, a stronger electric field accelerating function for carriers (here, electrons) can be exhibited, and ultra-high speed operation can be achieved. A possible SiGeC-HBT can be obtained.

The shape in which the energy gap increases in the direction from the Si layer 5 toward the Si epitaxial layer 20 in the SiGeC layer 4 is not necessarily linear. 4
A constant acceleration can always be given to the carrier within the inside, and the function of accelerating the carrier is particularly large.

Here, the state where the average lattice strain over the entire area of the SiGeC layer 4 is 1.0% or less refers to the following cases. For example, as shown in FIG. 11C, the SiGeC layer 4 constituting the intrinsic base layer 8a has
The portion in contact with the layer 5 (the end on the emitter side) has a single composition of Si, and Ge in the SiGeC layer 4 is directed from the portion in contact with the Si layer 5 to the portion in contact with the Si crystal film 20 (the end on the collector side). When the content and C content have a triangular profile that increases linearly,
This is the case where the amount of lattice distortion of the composition at the collector-side end of the central layer 4a where the Ge content and the C content peak, is 2% or less.

In the present embodiment, the case where the SiGeC layer 4 having the composition in the region Ra (see FIG. 10) where the SiGeC layer 4 is subjected to compressive strain has the graded composition has been described. It is necessary to keep in mind.

FIG. 12 shows the contents of Ge and C, the band gap, and the Ge content in the same SiGeC ternary mixed crystal semiconductor as in FIG.
It is a figure which shows the relationship of a lattice distortion, and shows the change direction of a composition when changing Ge content rate and C content rate linearly, making the ratio of both constant. FIG.
As can be seen from FIG. 12, in a state where the SiGeC layer 4 is lattice-matched (a portion on a straight line where the lattice distortion is 0% in FIG. 12).
When the band gap is inclined, the SiGeC layer 4
If the composition is not sufficiently controlled, if the composition slightly deviates from the specification, the band gap changes in a direction almost perpendicular to the contour line, so that the band gap fluctuates greatly and there is a problem in reproducibility. . Therefore, a structure in which the band gap is tilted in a lattice-matched state is avoided, and S
It is desirable that only the region of the iGeC layer 4 subjected to the compressive strain or the region subjected to the tensile strain has a gradient composition. Also, from the viewpoint of crystal growth, it is preferable to use a gradient composition in a region subjected to compressive strain to obtain Ge or C.
Is desirable in that a smaller band gap can be realized while reducing the content of as small as possible.

As described above, the SiGeC layer 4 constituting the intrinsic base layer 8a of the present embodiment does not include a portion that satisfies the lattice matching conditions (a portion on a straight line having a lattice distortion of 0% in FIG. 12). In addition, it is desirable to change the Ge content and the C content in a region where the average lattice strain over the entire region of the SiGeC layer 4 receives a compressive strain of 1.0% or less.

In this embodiment, FIG.
As shown in (c), the Ge content and the C content in the lower layer 4b of the SiGeC layer 4 are gradually reduced in the direction from the central portion 4a toward the Si epitaxial layer 20, so that the first embodiment differs from the first embodiment. Similarly, at the base-collector junction interface (heterobarrier between the SiGeC layer 4 and the Si epitaxial layer 20), generation of a parasitic barrier (see FIG. 6A) and a notch (see FIG. 7A) is suppressed. A smooth band structure can be obtained by suppressing the generation of a clear potential step in the conduction band.

However, only the C content in the lower layer 4b may be gradually reduced in the direction from the central layer to the Si epitaxial layer 20. Further, in a bipolar transistor of a type in which a band offset such as a notch does not cause a serious problem, the lower layer 4b does not necessarily have to have a gradient composition.

As described above, the intrinsic base layer 8a composed of the SiGeC layer 4 having the graded composition according to the present embodiment.
In the SiGeC-HBT provided with
By using a gradient composition in which the C content and the Ge content change at the SiGeC heterojunction interface, a practical heterobipolar transistor having excellent high-frequency characteristics can be formed without hindering the traveling of carriers.

(Third Embodiment) Next, the intrinsic base layer 8
a is composed of a graded composition SiGeC, and the built-in potential between the emitter and the base is reduced.
A third embodiment related to GeC-HBT will be described.

FIGS. 13A and 13B are an energy band diagram, a Ge content, a C content, and a B (boron) concentration of the gradient composition SiGeC-HBT in this embodiment, respectively. In the present embodiment, a portion of the central layer 4a of the SiGeC layer 4 constituting the intrinsic base layer 8a, which is in contact with the Si layer 5 constituting the emitter, is formed of Si.
Instead of a single composition, it is made of SiGe or SiGeC having a smaller band gap than Si. The central layer 4a of the SiGeC layer 4 constituting the intrinsic base layer 8a
Of which, the Si epitaxial layer 20 constituting the collector
Is in contact with Si, the band gap of which is smaller than that of Si.
It is composed of GeC. In the lower layer 4b of the SiGeC layer 4, the Ge content and the C content gradually decrease in the direction from the central layer 4a toward the Si epitaxial layer 20. Further, also in the upper layer 4c of the SiGeC layer 4, the Ge content and the C content gradually increase in the direction from the Si layer 5 toward the central layer 4a.

The potential difference A1 between the conduction bands of the SiGeC layer 4 and the Si layer 9 is equal to the potential difference A1 between the SiGeC layer 4 and the Si layer.
The potential difference between the valence bands with the i-layer 9 is smaller than B1. That is, the built-in potential of the PN junction between the emitter and the base is reduced, and low-voltage operation is enabled. Note that, as in the second embodiment, Si
The potential difference A2 between the conduction bands between the GeC layer 4 and the Si epitaxial layer 20 is the potential difference B2 between the valence bands between the SiGeC layer 4 and the Si epitaxial layer 20.
Less than.

In the SiGeC layer 4, the band gap C1 at a portion in contact with the Si layer 5 is larger than the band gap C2 at a portion in contact with the Si epitaxial layer 20. That is, the SiGeC forming the intrinsic base layer 8a
The band gap of the layer 4 is equal to S band from the Si layer 5 (emitter side).
It decreases linearly in the direction toward the i-epitaxial layer 20 (collector side). In other words, the SiGeC layer 4 has a graded composition, which generates a graded electric field in the intrinsic base layer 8a, and gives acceleration to the carriers traveling in the intrinsic base layer 8a to enable high-speed operation. Note that S
The composition is selected such that the average strain over the entire iGeC layer is 1.0% or less. With such a configuration, a hetero-bipolar transistor which can operate at a low voltage and has excellent high-frequency characteristics can be realized.

Next, the SiG used in this embodiment is
A specific composition of the eC layer 4 will be described. For example, S
The Ge content of the portion (emitter side) of the iGeC layer 4 in contact with the Si layer 5 (emitter side) is 30%, the C content is 3.3%,
The Ge content of the portion in contact with the Si epitaxial layer 20 (collector side) is 40%, and the C content is 3.3%. That is, the C contents at both ends of the SiGeC layer 4 are equal to each other. In the SiGeC layer 4, the Ge content linearly increases in the direction from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side).

Note that, also in the present embodiment, SiGeC
In the layer 4, the energy gap is changed from the Si layer 5 to Si.
The shape that increases in the direction toward the epitaxial layer 20 does not necessarily need to be linear, but if it increases linearly, a constant acceleration can always be applied to the carrier in the SiGeC layer 4 to accelerate the carrier. The ability to do is particularly large.

At this time, in the portion (Ge 30%, C3.3%) of the SiGeC layer 4 which is in contact with the Si layer 5, the band gap is 0.99 eV and the lattice distortion is 0.1%. In a portion (Ge 40%, C 3.3%) of the SiGeC layer 4 which is in contact with the Si epitaxial layer 20, the band gap is 0.91 eV and the lattice strain is 0.5%. With such a structure, the average lattice distortion over the entire area of the SiGeC layer 4 is about 0.3%, and there is no problem in practical use. By forming the intrinsic base layer 8a with the SiGeC layer 4 having such a composition, the conventional SiG
SiGeC-HBT which has a smaller bandgap on the emitter side than e-HBT, can operate at low voltage, and can operate at high speed
Can be obtained.

From the viewpoint of crystal growth, it is better to use a gradient composition in a region subjected to compressive strain than to have no strain, from the viewpoint of crystal growth.
Since a smaller band gap can be realized in a state where the content of C is small, the intrinsic base layer 8a is also formed of compressive strained SiGeC in this embodiment. As described above, as can be seen from FIG.
If the band gap is inclined in the GeC layer 4 in a lattice-matched state, if the composition is not sufficiently controlled, the band gap fluctuates greatly when the composition is slightly shifted, and there is a problem in reproducibility. Therefore, the composition of the SiGeC layer 4 is changed to the Si layer 5 in either the compression-strained region Ra or the tensile-strained region Rb while avoiding the inclined band gap structure in a lattice-matched state.
It is desirable to have a graded composition that changes from the (emitter side) toward the Si epitaxial layer 20 (collector side). However, the compression-strained region Ra
It should be noted that the directions of inclination of the Ge and C contents are different between the case where the band gap is inclined and the case where the band gap is inclined in the region Rb subjected to tensile strain. Hereinafter, the composition gradient method for tilting the band gap will be described separately for a region Ra subjected to compressive strain and a region Rb subjected to tensile strain.

-Example of Composition Gradient Method in Compressively Strained Region-FIG. 14 shows an example of a preferable composition gradient method for inclining the band gap in the compressively strained region Ra in the phase diagram of the SiGeC layer 4. It is a figure for explaining. In order to reduce the band gap, the straight line Co1 ~
There are several ways as shown in Co4.

FIGS. 15A to 15D show straight lines C in FIG.
It is a figure which shows the composition gradient method respectively corresponding to o1-Co4.

FIG. 15A shows that the C content in the SiGeC layer 4 is constant along the straight line Co1 shown in FIG.
It is a figure which shows the Ge content and the C content when the Ge content is linearly increased in the direction from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side).

FIG. 15B shows that the Ge content in the SiGeC layer 4 is constant along the straight line Co2 shown in FIG. 14, and the C content is changed from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side). FIG. 7 is a diagram showing the Ge content and the C content when linearly decreasing in the direction toward ().

FIG. 15C shows that the Ge content in the SiGeC layer 4 is changed along the straight line Co3 shown in FIG.
(Emitter side) linearly increases in the direction from the Si epitaxial layer 20 (collector side), and the C content increases linearly from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side). It is a figure which shows Ge content rate and C content rate at the time of reducing to a certain extent.

FIG. 15D shows that the Ge content in the SiGeC layer 4 is changed along the straight line Co4 shown in FIG.
From the (emitter side) to the direction toward the Si epitaxial layer 20 (collector side), the C content is linearly increased from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side). It is a figure which shows the Ge content rate and C content rate in the case of having increased tentatively.

-Example of Composition Gradient Method in Tensile Strained Region-FIG. 16 shows an example of a preferred composition gradient method for inclining the band gap in the tensile strained region Rb in the state diagram of the SiGeC layer 4. It is a figure for explaining. To reduce the band gap, the straight line T
There are several methods as shown in e1 to Te4.

FIGS. 17A to 17D show straight lines T in FIG.
It is a figure which shows the composition gradient method respectively corresponding to e1-Te4.

FIG. 17A shows that the C content in the SiGeC layer 4 is constant along the straight line Te1 shown in FIG.
It is a figure which shows the Ge content and the C content when the Ge content is linearly reduced in the direction from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side).

FIG. 17B shows that the Ge content in the SiGeC layer 4 is constant along the straight line Te2 shown in FIG. 16 and the C content is changed from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side). FIG. 7 is a diagram showing the Ge content and the C content when linearly increasing in the direction toward ()).

FIG. 17C shows that the Ge content in the SiGeC layer 4 is changed along the straight line Te3 shown in FIG.
(Emitter side) linearly decreases in the direction from the Si epitaxial layer 20 (collector side), and the C content is reduced in the direction from the Si layer 5 (emitter side) toward the Si epitaxial layer 20 (collector side). It is a figure which shows Ge content and C content when it increases linearly.

FIG. 17D shows that the Ge content in the SiGeC layer 4 is changed along the straight line Te4 shown in FIG.
From the (emitter side) to the direction toward the Si epitaxial layer 20 (collector side), the C content is linearly increased from the Si layer 5 (emitter side) to the Si epitaxial layer 20 (collector side). It is a figure which shows the Ge content rate and C content rate in the case of having increased tentatively.

As described above, the Si layer 5 of the SiGeC layer 4
When the composition of the portion in contact with the (emitter side) is set to match the lattice matching condition (on a straight line with a strain of 0%),
If the composition of SiGeC is not accurately controlled, SiGe
Depending on the inclination direction of the composition of C, the bandgap may have an opposite gradient (a gradient in which the bandgap decreases from the collector side to the emitter side).
The composition of the portion in contact with the i-layer 5 is shifted from the lattice matching condition,
It is desirable that the composition of the SiGeC layer 4 be inclined only in one of the region Ra subjected to the compressive strain and the region Rb subjected to the tensile strain.

According to the present embodiment, the SiGeC-HBT
Of the SiGeC layer 4 constituting the intrinsic base layer 8a of FIG.
The composition of the portion of the emitter layer 9 that is in contact with the Si layer 5 is not a composition of Si alone but a composition containing at least one of Ge and C. 5, the SiGeC-HBT is reduced by reducing the built-in potential of the PN junction between the emitter and the base, in addition to the same effect as in the second embodiment.
Can be operated at a low voltage.

Note that, also in this embodiment, SiGeC
The composition of SiGeC is selected such that the average strain over the entire area of the layer 4 is 1.0% or less. With this configuration, it is possible to realize a hetero-bipolar transistor that can operate at a low voltage and has excellent high-frequency characteristics.

In this embodiment, SiGeC
Although the composition of the portion of the layer 4 in contact with the Si layer 5 is a composition containing Si, Ge and C, as can be seen from FIGS. May be a composition containing Si and Ge without containing C, or a composition containing Si and C without containing Ge when performing the gradient composition control in the tensile strained region Rb.

Further, in the present embodiment, FIG.
As shown in (b), the Ge content and the C content in the lower layer 4b of the SiGeC layer 4 are gradually reduced in the direction from the central portion 4a toward the Si epitaxial layer 20, and
Since the Ge content and the C content in the upper layer 4c of the SiGeC layer 4 are gradually increased in the direction from the Si layer 5 toward the central portion 4a, the base layer and the base layer are similar to the first embodiment.
At the collector junction interface (heterobarrier between the SiGeC layer 4 and the Si epitaxial layer 20) and the emitter-base junction interface, generation of a parasitic barrier (see FIG. 6A) and a notch (see FIG. 7A) is suppressed. In addition, the generation of a clear potential step in the conduction band can be suppressed, and a smooth band structure can be obtained.

However, only the C content in the lower layer 4b and the upper layer 4c is determined from the central layer to the Si epitaxial layer 20 or S layer.
It may be gradually reduced in the direction toward the i-layer 5. Also,
In a type of bipolar transistor in which a band offset such as a notch does not cause a serious problem, it is not always necessary to provide the lower layer 4b and the upper layer 4c with a gradient composition.

As described above, the intrinsic base layer 8a composed of the SiGeC layer 4 having the graded composition of the present embodiment.
In the SiGeC-HBT provided with
By using a gradient composition in which the C content and the Ge content gradually change at the SiGeC heterojunction interface, a practical heterobipolar transistor having excellent high-frequency characteristics can be formed without hindering the traveling of carriers. .

In each of the above embodiments, measures for improving the characteristics have been described on the premise of the structure of the single hetero bipolar transistor shown in FIG. 2. However, it is needless to say that the B and the CMOS in which the bipolar transistor and the CMOS are integrated are integrated.
The bipolar transistor of the iCMOS device may be constituted by the SiGeC-HBT according to the present invention.

In the embodiment of the present invention, the NPN type S
Although the description has been made by taking the iGeC-HBT as an example, the present invention is applied to a P
Needless to say, the present invention can be applied to an NP-type SiGeC-HBT.

[0143]

According to the hetero bipolar transistor of the present invention, the emitter layer including the first semiconductor layer and the Si layer having a smaller band gap than the first semiconductor layer are formed on the substrate.
A base layer formed in the second semiconductor layer made of GeC crystal; and a collector layer including a third semiconductor layer having a band gap larger than that of the second semiconductor layer. Since the lattice distortion is set to 1.0% or less, the band gap difference between the second semiconductor layer and the first and third semiconductor layers is increased without causing lattice mismatch.
It is possible to realize an increase in current amplification factor due to a reduction in the built-in voltage, an improvement in operation speed due to the gradient composition base structure, and the like, thereby providing a highly reliable heterobipolar transistor having excellent functions.

[Brief description of the drawings]

FIG. 1 is a state diagram showing the relationship between the contents of Ge and C, a band gap, and lattice distortion in a ternary mixed crystal semiconductor of SiGeC.

FIG. 2 is a cross-sectional view of the hetero bipolar transistor according to the embodiment of the present invention.

FIGS. 3A to 3K are cross-sectional views illustrating steps of manufacturing a hetero bipolar transistor according to the embodiment of the present invention.

FIGS. 4 (a) to 4 (c) respectively show a conventional NP
FIG. 3 is an energy band diagram of an N-type Si-BJT, an energy band structure of a conventional NPN-type SiGe-HBT having a uniform composition base layer, and an energy band diagram of an NPN-type SiGeC-HBT having a uniform composition SiGeC base layer of the present embodiment. .

FIG. 5 is a graph showing the dependence of the base-collector current on the base voltage (Gummel plot) of the hetero-bipolar transistor according to the embodiment of the present invention using conventional Si-BJT and SiGe.
It is a figure shown in comparison with -HBT.

FIGS. 6A and 6B respectively show, in order, the position of each crystal layer and the base of a heterobipolar transistor in which boron for a base layer is doped in a wider range than a SiGeC layer having a uniform composition as a whole; FIG. 4 is a diagram showing the relationship between the position of the transistor, the emitter and the collector, and the energy band diagram of the transistor.

FIGS. 7A and 7B respectively show the positions of base layers, emitters and collectors of respective crystal layers of a hetero bipolar transistor in which boron for a base layer is doped in a SiGeC layer having a uniform composition throughout; And the energy band diagram of the transistor.

8 (a) and 8 (b) show a hetero-bipolar transistor in which boron for a base layer is doped only in a SiGeC layer having a uniform composition in a central layer and lower and upper layers on both sides in a gradient composition, respectively. 3A and 3B are diagrams illustrating a relationship between positions of respective crystal layers and positions of a base, an emitter, and a collector, and an energy band diagram of a transistor.

9 (a) and 9 (b) are heterobipolar transistors in which boron for the base layer is doped only in the SiGeC layer having a uniform composition in the central layer and lower and upper layers on both sides having a gradient composition (only C). FIG. 3 is a diagram showing a relationship between the position of each crystal layer and positions of a base, an emitter, and a collector, and an energy band diagram of a transistor.

FIG. 10 shows the same parameters as in FIG.
It is a state diagram which shows the area | region which receives the following compression strains.

FIGS. 11A to 11C are energy band diagrams of a SiGe-HBT having a conventional base layer having a gradient composition, and energies of a SiGeC-HBT having a base layer having a gradient composition according to the second embodiment. FIG. 7 is a band diagram and a diagram showing a Ge content, a C content, and a B (boron) concentration of the SiGeC-HBT of the second embodiment.

FIG. 12 is a state diagram showing a direction in which the composition changes when the Ge and C contents are changed linearly while keeping the ratio between the two in the second embodiment for the same parameters as in FIG. 1;

FIGS. 13A and 13B are an energy band diagram, a Ge content, a C content, and a B (boron) concentration of the gradient composition SiGeC-HBT in the third embodiment, respectively. .

FIG. 14 is a diagram for explaining an example of a preferable composition gradient method for gradient band in a region subjected to compressive strain in the phase diagram of the SiGeC layer.

15A to 15D show straight lines Co1 to Co4 in FIG.
FIG. 3 is a diagram showing a composition gradient method corresponding to each of FIGS.

FIG. 16 is a diagram for explaining an example of a preferred composition gradient method for inclining a band gap in a region subjected to tensile strain in a phase diagram of a SiGeC layer.

17 (a) to (d) show straight lines Te1 to Te4 in FIG.
FIG. 3 is a diagram showing a composition gradient method corresponding to each of FIGS.

FIG. 18 shows the Ge content and lattice distortion of a SiGe film formed on a Si layer in a conventional SiGe-HBT or the like;
FIG. 4 is a characteristic diagram showing a relationship with a critical film thickness.

FIG. 19 shows Si represented by the general formula Si _1-xy Ge _x C _y
It is data showing a change in crystallinity when a heat treatment (RTA) is performed on a GeC crystal layer at 950 ° C. for 15 seconds.

[Figure 20] (a) ~ (d) are views showing changes in X-ray diffraction spectrum by heat treatment in the composition of the Si _1-x Ge _x crystal layer and Si _1-xy Ge _x C _y crystal layer.

FIG. 21 shows a Si content of 21.5%._1-x Ge
_x Crystal layer and Si_1-xy Ge_x C _y Crystal layer as base layer
To the grounded emitter of a bipolar transistor
V_CE -I_C It is a figure showing a characteristic.

FIG. 22 shows a Si content of 26.8%._1-x Ge
_x Crystal layer and Si_1-xy Ge_x C _y Crystal layer as base layer
To the grounded emitter of a bipolar transistor
V_CE -I_C It is a figure showing a characteristic.

[Explanation of symbols]

 Reference Signs List 1 Si substrate 2 LOCOS film 3a Sub-collector layer 3b Collector layer 3c Collector wall layer 4 SiGeC layer (second semiconductor layer) 5 Si layer (third semiconductor layer) 6 BSG film 7 Protective oxide film 8a Intrinsic base layer 8b External Base layer 9 Emitter layer 9a High concentration emitter layer 10 Side wall 11 Emitter electrode 12 Collector electrode 13 Interlayer insulating film 14 Collector contact layer 20 Si single crystal film (first semiconductor layer) 21 Al wiring 22 Al wiring 23 Al wiring

Continuing from the front page (72) Inventor Kenji Toyoda 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Reference) 5F003 BA97 BB04 BB06 BB07 BB08 BC07 BC08 BE07 BE08 BF06 BM01 BP06 BP07 BP34 BS06 BS08

Claims (31)

[Claims] 1. A semiconductor device comprising: a first semiconductor layer formed of a semiconductor material having Si as a component;
An upper layer made of a semiconductor material having C and C as components and having a smaller band gap than the first semiconductor layer;
A second semiconductor layer including a central layer and a lower layer, and a third semiconductor layer including a semiconductor material containing Si as a component and having a larger band gap than the second semiconductor layer are sequentially stacked. , The first semiconductor layer and the second semiconductor layer
And a collector layer formed in the first semiconductor layer and containing a first conductivity type impurity, and a second conductive layer formed in the second semiconductor layer. A base layer containing an impurity of a first conductivity type, and an emitter layer formed on the third semiconductor layer and containing an impurity of a first conductivity type, wherein the average lattice strain of the second semiconductor layer is 1.0% or less. Hetero bipolar transistor characterized by the above-mentioned. 2. The hetero bipolar transistor according to claim 1, wherein said second semiconductor layer is subjected to compressive strain. 3. The hetero bipolar transistor according to claim 1, wherein a band gap of the second semiconductor layer is 1.04 eV.
A heterobipolar transistor characterized by the following. 4. The hetero-bipolar transistor according to claim 1, wherein said first semiconductor layer is made of a single crystal of Si, and said second semiconductor layer is made of said second semiconductor. The composition of the layer is S
i _1-xy Ge _x C _y (When the content of Ge is represented by x and the content of C is represented by y), a two-dimensional orthogonal coordinate system in which the horizontal axis represents the Ge content and the vertical axis represents the C content. On the coordinates, straight line: y = 0.122x-0.032 straight line: y = 0.1245x + 0.028 straight line: y = 0.332x-0.0233 (C content is 22% or less) straight line: y = 0 A hetero bipolar transistor having a composition of a region surrounded by four straight lines of 0.0622x + 0.0127 (C content is 22% or less). 5. The hetero bipolar transistor according to claim 4, wherein the central layer of the second semiconductor layer has a uniform Ge and C content. 6. The hetero-bipolar transistor according to claim 5, wherein the C content in the upper layer of the second semiconductor layer is the third.
Characterized in that it increases in the direction from the semiconductor layer to the central layer. 7. The hetero bipolar transistor according to claim 5, wherein in the upper layer of the second semiconductor layer, the content of C and Ge increases in a direction from the third semiconductor layer toward the central layer. A hetero-bipolar transistor. 8. The hetero-bipolar transistor according to claim 5, 6 or 7, wherein, in a lower layer of the second semiconductor layer, a C content decreases in a direction from the central layer toward the first semiconductor layer. A hetero-bipolar transistor characterized in that: 9. The hetero-bipolar transistor according to claim 5, wherein in the lower layer of the second semiconductor layer, the content of C and Ge is in a direction from the central layer to the first semiconductor layer. A hetero-bipolar transistor characterized by being reduced. 10. The heterobipolar transistor according to claim 1, wherein a band gap of the central layer of the second semiconductor layer decreases in a direction from the third semiconductor layer toward the first semiconductor layer. A hetero-bipolar transistor characterized in that: 11. The hetero bipolar transistor according to claim 10, wherein the third semiconductor layer is made of only Si, and a composition of an upper layer of the second semiconductor layer changes continuously with the central layer. The portion in contact with the third semiconductor layer is made of only Si, and the central layer and the upper layer of the second semiconductor layer have a content of at least one of Ge and C from the third semiconductor layer. A hetero-bipolar transistor having a composition inclined to increase in a direction toward the first semiconductor layer. 12. The hetero-bipolar transistor according to claim 11, wherein the central layer and the upper layer of the second semiconductor layer include a G layer.
A hetero-bipolar transistor characterized in that the content ratios of e and C are both increased while keeping the content ratio thereof constant. 13. The heterobipolar transistor according to claim 10, wherein the C content in the lower layer of the second semiconductor layer decreases in a direction from the central layer toward the first semiconductor layer. A hetero bipolar transistor characterized by being small. 14. The heterobipolar transistor according to claim 10, wherein in the lower layer of the second semiconductor layer, the contents of Ge and C in the direction from the central layer toward the first semiconductor layer. A hetero-bipolar transistor characterized in that it has a reduced size. 15. The heterobipolar transistor according to claim 10, wherein an upper layer of the second semiconductor layer is made of Si containing at least one of Ge and C, and a content of Ge or C. From the third semiconductor layer to the first
A composition of the second semiconductor layer is inclined so as to change in a direction toward the semiconductor layer. 16. The hetero bipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that undergoes compressive strain, and has a constant C content and a Ge content. A hetero bipolar transistor having a gradient composition in which a rate increases in a direction from the third semiconductor layer to the first semiconductor layer. 17. The heterobipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that undergoes compressive strain, and has a constant Ge content and a C content. A hetero bipolar transistor having a gradient composition in which the rate decreases in a direction from the third semiconductor layer to the first semiconductor layer. 18. The hetero-bipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that receives a compressive strain, and the first semiconductor layer is formed of a third semiconductor layer. A hetero bipolar transistor having a gradient composition in which a Ge content increases and a C content decreases in a direction toward a layer. 19. The hetero-bipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that undergoes compressive strain, and further includes a first semiconductor layer from the third semiconductor layer. A hetero bipolar transistor having a gradient composition in which the contents of Ge and C increase in a direction toward a layer. 20. The hetero bipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that undergoes tensile strain, and has a constant C content and a Ge content. A hetero bipolar transistor having a gradient composition in which the rate decreases in a direction from the third semiconductor layer to the first semiconductor layer. 21. The heterobipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that undergoes tensile strain, and has a constant Ge content and a C content. A hetero bipolar transistor having a gradient composition in which a rate increases in a direction from the third semiconductor layer to the first semiconductor layer. 22. The hetero-bipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that undergoes tensile strain, and the first semiconductor layer is formed from the third semiconductor layer. A hetero bipolar transistor having a gradient composition in which a Ge content decreases and a C content increases in a direction toward a layer. 23. The hetero-bipolar transistor according to claim 15, wherein the central layer of the second semiconductor layer has a composition that undergoes tensile strain, and the first semiconductor layer is formed of a third semiconductor layer. A hetero bipolar transistor having a gradient composition in which the Ge content increases and the C content increases in the direction toward the layer. 24. The heterobipolar transistor according to claim 15, wherein a vertical direction interposed between the central layer and a third semiconductor layer of the second semiconductor layer. In the edge region, C
Characterized by the fact that the content of GaAs increases in the direction from the third semiconductor layer toward the central layer. 25. The heterobipolar transistor according to claim 15, wherein in the upper layer of the second semiconductor layer, the content of C and Ge is higher than that of the third semiconductor layer in the central layer. Characterized in that it increases in the direction toward. 26. The heterobipolar transistor according to claim 15, wherein a C content in the lower layer of the second semiconductor layer is from the central layer to the first semiconductor layer. A hetero-bipolar transistor characterized by being reduced in a direction. 27. The heterobipolar transistor according to claim 15, wherein in the lower layer of the second semiconductor layer, the content of C and Ge in the first semiconductor layer is lower than that of the central layer. Characterized in that it is reduced in the direction toward 28. A semiconductor device comprising a first semiconductor layer of the first conductivity type having Si as a component and functioning as a collector layer,
(a) forming a second semiconductor layer including an eC layer and having a band gap smaller than that of the first semiconductor layer and having an average lattice strain of 1.0% or less; Forming a third semiconductor layer containing at least Si and having a band gap larger than that of the second semiconductor layer, and including a first conductivity type impurity contacting a part of the third semiconductor layer. A step (c) of forming a conductor layer, a step (d) of introducing a second conductivity type impurity into at least a part of the second semiconductor layer, and a step (d) of forming a base layer. (E) forming an emitter diffusion layer by diffusing the first conductivity type impurity into the third semiconductor layer. 29. The method for manufacturing a hetero bipolar transistor according to claim 28, wherein the first semiconductor layer is a Si layer, and in the step (a), the second semiconductor layer is Si.
_{1-xy Ge x C y (} Ge x the content of the content of C y) layer is formed, in the step (b), and characterized by forming the Si layer as the third semiconductor layer Of manufacturing a hetero bipolar transistor. 30. The method for manufacturing a heterobipolar transistor according to claim 29, wherein in the step (a), the second semiconductor layer is formed such that the abscissa represents the Ge content and the ordinate represents the C content. On the two-dimensional orthogonal coordinates, straight line: y = 0.122x-0.032 straight line: y = 0.1245x + 0.028 straight line: y = 0.332x-0.0233 (C content is 22% or less) Straight line: A method for manufacturing a hetero-bipolar transistor, characterized in that it is formed so as to have a composition of a region surrounded by four straight lines: y = 0.0622x + 0.0127 (C content is 22% or less). 31. The method of manufacturing a hetero-bipolar transistor according to claim 28, wherein in the step (b), the first and second steps are performed simultaneously with the epitaxial growth.
A method of manufacturing a hetero-bipolar transistor, wherein a conductivity type impurity is doped in the third semiconductor layer.