JP2001068474A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To readily reduce increase of wiring capacitance caused by high density of a wiring layer and prevent generation of malfunction by forming a first wiring along an upper part of a surface step, and a second wiring along a lower part of a surface step adjacent mutually apart up and down in a vertical direction to a semiconductor substrate. SOLUTION: A field oxide film 2 is formed on the surface of a semiconductor substrate 1, and a diffusion layer 3 is formed in an element region. An irregular layer insulation film 4 is formed, a wiring layer 5 is formed in a recessed part thereof, a wiring layer 6 is formed in a projection part thereof, and a wiring layer 5a connected to the diffusion layer 3 is formed similarly. A layer insulation film 7 is formed all over. That is, the irregular layer insulation film 4 is formed on a field oxide film 2 and a height difference between a recessed part and a projection part of the irregular layer insulation film 4 is (t) and the wiring layer 5 is formed in a recessed part and the wiring layer 6 is formed on a projection part at the same time, and a separation distance between the wiring layer 5 and the wiring layer 6 is shown by (d).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a wiring structure.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, a fine wiring layer is indispensable for the configuration of a semiconductor device. At present, as an interlayer insulating film of a semiconductor device having such a wiring layer, a silicon oxide film based insulating film having a relatively small dielectric constant and a stable quality is mainly used.

Although the width of the wiring and the spacing between the wirings are reduced by miniaturization of the semiconductor element, it is necessary to secure a certain cross-sectional area of the wiring in order to avoid an increase in the wiring resistance. As a result, the aspect ratio (interconnect height / interconnect interval) between the interconnects as well as the aspect ratio of the interconnect layer (interconnect height / interconnect width) increases. For this reason, the parasitic capacitance between the wiring layers greatly increases, and the signal transmission speed decreases,
Crosstalk between wiring layers (a phenomenon in which signal noise occurs between adjacent wiring layers) frequently occurs.

Hereinafter, a conventional method for forming a wiring layer will be described with reference to FIG. FIG. 6 is a cross-sectional view of a semiconductor device on which a wiring layer is formed.

As shown in FIG. 6, a field oxide film 102 is formed on a surface of a semiconductor substrate 101 such as silicon.
COS (Local Oxidation of Si)
(silicon) method or trench element isolation method. In FIG. 6, this region is shown as an element isolation region. Further, a diffusion layer 103 that forms an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor) is formed in the element region. In addition,
Although not shown, a gate electrode and the like constituting a MOS transistor as a semiconductor element are formed by a known method, and a first interlayer insulating film 104 covering the entire surface is formed. here,
Usually, the surface of the first interlayer insulating film 104 is chemically mechanically polished (C
(MP) method.

Next, a wiring layer 105 is provided on the first interlayer insulating film 104 with a predetermined wiring width and a predetermined wiring interval. Further, a wiring layer 105a connected to the diffusion layer 103 is similarly formed. These wiring layers 105 and 105a are usually
The aluminum alloy film is formed by forming a single-layer aluminum alloy film and patterning the aluminum alloy film by fine processing using a photolithography technique and a dry etching technique.

Then, a second interlayer insulating film 106 is formed on the entire surface by a chemical vapor deposition (CVD) method of a silicon oxide film. Thus, a semiconductor device is completed. Alternatively, in the case of a multilayer wiring structure, another wiring layer is further laminated via an interlayer insulating film.

[0008]

In the prior art as described above, in a wiring structure of a semiconductor device, a wiring layer for connecting a semiconductor element is formed on the same plane of an insulating film. However, when the semiconductor element is miniaturized and the wiring density increases, the capacitance between wirings increases as described above.

[0009] For this reason, with the increase in the degree of integration or the density of the semiconductor device, a signal transmitted through the wiring layer is delayed or a signal is distorted. Alternatively, noise propagates to an adjacent wiring layer. Then, a malfunction of the semiconductor device occurs.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can easily reduce an increase in inter-wiring capacitance due to an increase in the density of wiring layers and can prevent occurrence of a malfunction.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a plurality of wirings are provided on a semiconductor substrate via an interlayer insulating film. Forming a convex portion of an insulating film on a predetermined region of the interlayer insulating film to provide a surface step on the interlayer insulating film, depositing a metal film so as to cover the interlayer insulating film having the surface step; By patterning a film, a first wiring and a second wiring along the lower part of the surface step are formed adjacent to each other on the insulating film convex part and the upper part of the surface step so that the first wiring is adjacent to each other and is perpendicular to the semiconductor substrate. And forming the substrate vertically apart.

Here, an interlayer insulating film and a silicon layer are laminated on a semiconductor substrate having a semiconductor element, and the silicon layer is selectively thermally oxidized by using an oxidation mask material provided on the silicon layer. An insulating film projection is formed. And
The silicon layer contains an N-type impurity. The metal film is formed of an aluminum-based metal film or a high-melting-point metal film.

Alternatively, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a plurality of wirings are provided on a semiconductor substrate via an interlayer insulating film, wherein a plurality of wirings are provided on a predetermined region of the interlayer insulating film. Forming a convex portion of an insulating film and providing a surface step in the interlayer insulating film; forming an insulating film for a wiring groove on the interlayer insulating film having the surface step and forming a wiring groove in the insulating film for a wiring groove A first metal film is filled in the wiring groove, and a first film is formed on the insulating film convex portion above the surface step.
Forming the groove wiring and the second groove wiring along the lower portion of the surface step adjacent to each other and vertically apart from the semiconductor substrate in the vertical direction.

Here, an etching stopper layer is formed between the interlayer insulating film having the insulating film protrusions and the wiring groove insulating film. The metal film is made of a metal containing copper.

As described above, according to the present invention, the wiring layers adjacent to each other are vertically separated by the insulating film having a height difference in the vertical direction with respect to the semiconductor substrate. For this reason, the effective separation distance between adjacent wiring layers increases, and the capacitance between the wiring layers decreases.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a semiconductor device having a wiring structure formed by the manufacturing method of the present invention. 2 and 3 are sectional views in the order of the manufacturing process of the present invention.

A field oxide film 2 is formed on the surface of a semiconductor substrate 1 in the same manner as described in the prior art. In FIG. 1A, this region is shown as an element isolation region. Further, a diffusion layer 3 that forms a MOS transistor is formed in the element region.

Next, an insulating film having a step having a height difference on its surface, that is, an interlayer insulating film 4 having unevenness is formed. This forming method will be described later in detail with reference to FIGS. Then, a wiring layer 5 is formed in a concave portion of the surface of the uneven interlayer insulating film 4, and a wiring layer 6 is formed in a convex portion of the surface of the uneven interlayer insulating film 4. Also,
The wiring layer 5a connected to the diffusion layer 3 is formed similarly.

Then, an interlayer insulating film 7 is formed on the entire surface by CVD of a silicon oxide film. Thus, a semiconductor device is completed. Here, FIG.
This will be described in (b).

As shown in FIG. 1B, an interlayer insulating film 4 having irregularities is formed on the field oxide film 2. Here, the height difference between the concave and convex portions of the uneven interlayer insulating film 4 is t
Indicated by Then, the wiring layer 5 is formed in the concave portion, and at the same time, the wiring layer 6 is formed in the convex portion. The distance between the wiring layer 5 and the wiring layer 6 is indicated by d.

As described above, according to the present invention, the wiring layers adjacent to each other are vertically separated by the insulating film having the difference in height. Here, the effective separation distance between adjacent wiring layers is substantially expressed by (t ² + d ² ) ^1/2 , and the value increases, and the capacitance between the wiring layers decreases.

Next, a specific method for manufacturing the above wiring structure will be described with reference to FIGS. As shown in FIG. 2A, a field oxide film 2 is selectively formed on a surface of a semiconductor substrate 1 such as a P-type silicon substrate.
Here, the field oxide film 2 is formed by forming a silicon oxide film by thermal oxidation by the LOCOS method and flattening the surface by the CMP method. Then, a diffusion layer 3 constituting a MOS transistor as a semiconductor element is formed with doping with an N-type impurity such as arsenic.

Next, a first interlayer insulating film 8 having a thickness of 400 nm is formed on the entire surface. Here, the first interlayer insulating film 8 is made of C
It is composed of a silicon oxide film deposited by the VD method. Next, a silicon layer 9 having a thickness of 200 nm is formed on the first interlayer insulating film 8. Here, the silicon layer 9 is formed of a polycrystalline silicon film or an amorphous silicon film. Such a silicon layer 9 may contain impurities such as arsenic or phosphorus at a high concentration. Further, an oxidation mask material 10 is formed on silicon layer 9. Such an oxidation mask material 10 is preferably made of a silicon nitride film having a thickness of about 100 nm.

Next, known thermal oxidation is performed. By this thermal oxidation, the silicon layer 9 in the opening of the oxidation mask material 10 is selectively thermally oxidized, and as shown in FIG. 2B, an oxide film protrusion 11 having a thickness of about 400 nm is formed in this region. .
Here, if the N-type impurity is contained in the silicon layer 9 at a high concentration, the selective thermal oxidation rate is increased, and the time required for forming the oxide film projections 11 is greatly reduced.

Next, the oxidation mask material 10 is removed, and the exposed silicon layer 9 is removed by anisotropic dry etching. In this way, as shown in FIG.
An oxide film protrusion 11 is formed on the interlayer insulating film, and a residual silicon layer 12 is formed at an end of the oxide film protrusion 11.

Then, the remaining silicon layer 12 is thermally oxidized. By this thermal oxidation again, as shown in FIG. 3A, the inclination of the end of the oxide film convex portion 11 becomes gentle,
Oxide film protrusions 11a having a reduced inclination are formed. Thus, the oxide film protrusion 11a and the first interlayer insulating film 8 are formed.
Thus, the interlayer insulating film 4 having the above-mentioned unevenness is formed.

Next, an opening is formed on the diffusion layer 3 of the uneven interlayer insulating film 4, and an aluminum / copper metal film having a thickness of about 500 nm is formed on the entire surface. Here, the metal film is deposited by a sputtering method.

Next, the metal film is finely processed by a known photolithography technique and a dry etching technique. Thus, the wiring layer 5 is formed in the concave portion on the uneven interlayer insulating film 4, and the wiring layer 6 is formed in the convex portion on the uneven interlayer insulating film 4 at the same time. In addition, a wiring layer 5a is formed on the diffusion layer 3.
Is formed. Here, if the end of the oxide film protrusion 11 is gentle, the problem such as the remaining etching of the wiring layer at the high / low step portion in the above-mentioned fine processing is eliminated.

Then, a film thickness of 6 is formed on the entire surface by a plasma CVD method.
A silicon oxide film of about 00 nm is deposited, and an interlayer insulating film 7 is formed as described with reference to FIG.

When the remaining silicon layer 12 is thermally oxidized, only a part of the remaining silicon layer 12 is selected and thermally oxidized so that the end of the oxide film convex portion 11 in that region is made gentle. It may be. In this case, the oxide film convex portion 1
A portion with a gentle slope and a steep portion at the end of 1 are formed. In this manner, the density of the wiring layer at the steep portion can be increased.

Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment is a case where the manufacturing method of the present invention is applied to a trench wiring structure. Here, FIG. 4 is a cross-sectional view of a semiconductor device having a wiring structure formed by the manufacturing method of the present invention. FIG. 5 is a sectional view of the present invention in the order of the manufacturing process. 4 and 5, the same components as those described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 4A, a field oxide film 2 is formed on the surface of a semiconductor substrate 1 in the same manner as described in the first embodiment. Then, a diffusion layer 3 constituting a MOS transistor is formed in a predetermined region of the semiconductor substrate 1.

Next, an insulating film having a step with a height difference on its surface, that is, an interlayer insulating film 4 having irregularities is formed. This forming method is as described in detail with reference to FIGS.

Next, an etching stopper layer 13 is formed. This etching stopper layer 13 is composed of a silicon oxynitride (SiON) film. Then, an opening is formed on the diffusion layer 3, and the opening is filled with a contact plug 14 to be formed.

Next, a wiring groove is formed in the groove wiring insulating film 15, and the wiring groove is filled with a metal film such as copper. Thus, the groove wiring 16 is formed in the region corresponding to the concave portion of the uneven interlayer insulating film 4, and the groove wiring 17 is formed in the region corresponding to the convex portion of the uneven interlayer insulating film 4. Also, a trench wiring 17a connected to the diffusion layer 3 through the contact plug 14 is formed in the same manner. Then, an interlayer insulating film 18 is formed on the entire surface by forming a SiON film by a CVD method.

Next, as in the first embodiment, the features of the present invention will be described with reference to FIG.

As shown in FIG. 4B, an interlayer insulating film 4 having irregularities is formed on the field oxide film 2. Then, the groove wiring 16 is formed in the concave portion via the etching stopper layer 13, and at the same time, the groove wiring 17 is formed in the convex portion.

As described above, in the present invention, the trench wirings adjacent to each other are vertically separated by the insulating film having the difference in height. For this reason, the effective separation distance between the adjacent groove wirings increases, and the capacitance between the groove wirings decreases.

Next, a specific method of manufacturing the above-described trench wiring structure will be described with reference to FIG. As shown in FIG. 5A, in the same manner as described with reference to FIG.
Field oxide film 2 is selectively formed on the surface of the substrate. Then, a diffusion layer 3 constituting a MOS transistor as a semiconductor element is formed with doping with an N-type impurity such as arsenic.

Next, the interlayer insulating film 4 having irregularities is formed so as to cover the entire surface by the method described in the first embodiment. Then, as shown in FIG. 5B, an etching stopper layer 13 having a thickness of about 100 nm is formed. This etching stopper layer 13 is a SiON film deposited by a plasma CVD method. Further, on the etching stopper layer 13, an insulating film 15 for trench wiring having a thickness of about 600 nm is formed. The insulating film 15 for trench wiring is a silicon oxide film deposited by the CVD method.

Next, as shown in FIG. 5C, an opening 19 reaching the diffusion layer 3 is formed in a predetermined region of the uneven interlayer insulating film 4 and the etching stopper layer 13.
Further, a wiring groove 20 is formed by dry etching of a predetermined region of the groove wiring insulating film 15. Here, the etching stopper layer 13 has a role of protecting the uneven interlayer insulating film 4 from dry etching.

As shown in FIG. 5D, a metal film such as copper is formed so as to fill the wiring groove, and groove wirings 16, 17, and 17a are formed in the groove wiring insulating film 15. You. Further, a film thickness of 600 n is formed on the entire surface by a plasma CVD method.
About m m of SiON film is deposited, and the interlayer insulating film 7 is formed as described with reference to FIG.

In the second embodiment, the unevenness in the level of the interlayer insulating film 4 having irregularities appears on the surface of the trench wiring insulating film 15 as it is. Alternatively, the surface of the trench wiring insulating film 15 may be planarized by a CMP method or the like, and the trench wiring 16 may be formed on the interlayer insulating film 4 in the concave portion. However, in this case, the trench wiring 16 is used, for example, as a power supply line or a GND line of a semiconductor device. Since the thickness of the trench wiring 16 is increased, the current supply capability is increased.

[0044]

As described above, according to the present invention, in a method of manufacturing a semiconductor device in which a plurality of wirings are provided on a semiconductor substrate via an interlayer insulating film, the insulating film is formed in a predetermined region of the interlayer insulating film. A convex portion is formed, and a surface step is provided on the interlayer insulating film. Then, a metal film is deposited so as to cover the interlayer insulating film having the surface step, the metal film is patterned, and the first wiring and the first wiring are formed on the insulating film convex portion on the surface step. The second wiring along the lower part of the surface step is formed adjacent to each other and vertically separated from the semiconductor substrate in the vertical direction.

Alternatively, according to the present invention, a first trench wiring and a second trench wiring are arranged adjacent to each other on the interlayer insulating film having a surface step formed by the above-mentioned insulating film projections, and are vertically arranged with respect to the semiconductor substrate. Formed apart from each other.

As a result, the effective distance between adjacent wirings increases, and the capacitance between wirings in the same layer decreases. Even if the wiring structure becomes finer and the spacing between the wirings becomes narrower, the parasitic capacitance between the wirings does not greatly increase, the signal transmission speed does not decrease, and crosstalk between the wirings does not occur frequently.

As described above, the present invention facilitates the enhancement of the performance and the reliability of the fine multilayer wiring accompanying the miniaturization or multifunctionalization of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a wiring portion of a semiconductor device for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of the above embodiment in the order of the manufacturing process.

FIG. 3 is a sectional view of the above embodiment in the order of the manufacturing process.

FIG. 4 is a sectional view of a wiring portion of a semiconductor device for explaining a second embodiment of the present invention;

FIG. 5 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a cross-sectional view of a wiring portion of a semiconductor device for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 Semiconductor substrate 2,102 Field oxide film 3,103 Diffusion layer 4 Interlayer insulating film with unevenness 5,5a, 6,105,105a, 106 Wiring layer 7,18 Interlayer insulating film 8,104 First interlayer insulating film Reference Signs List 9 silicon layer 10 oxidation mask material 11, 11a oxide film protrusion 12 residual silicon layer 13 etching stopper layer 14 contact plug 15 groove wiring insulating film 16, 17, 17a groove wiring 19 opening 20 wiring groove 106 second interlayer insulating film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB02 BB04 DD06 DD08 DD24 DD37 DD62 EE06 EE12 FF03 FF21 GG14 HH18 5F033 HH08 HH11 MM01 MM15 NN01 PP15 QQ11 QQ23 QQ37 QQ73 QQ77 RR04 RR08 SS11 SS25 SS11 SS25

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: arranging a plurality of wirings on a semiconductor substrate via an interlayer insulating film, wherein an insulating film convex portion is formed in a predetermined region of the interlayer insulating film. A step of providing a surface step on the film, a step of depositing a metal film so as to cover the interlayer insulating film having the surface step, and a step of patterning the metal film to form an upper portion of the surface step on the insulating film convex portion. Forming a first wiring along the second wiring and a second wiring along the lower part of the surface step so as to be adjacent to each other and vertically separated in a vertical direction with respect to the semiconductor substrate. Manufacturing method. 2. An insulating film is formed by laminating an interlayer insulating film and a silicon layer on a semiconductor substrate having a semiconductor element, and the insulating layer is selectively thermally oxidized using an oxidation mask material provided on the silicon layer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a film projection is formed. 3. The method according to claim 1, wherein the silicon layer contains an N-type impurity. 4. The method for manufacturing a semiconductor device according to claim 1, wherein said metal film is an aluminum-based metal film or a high melting point metal film. 5. A method for manufacturing a semiconductor device, comprising: arranging a plurality of wirings on a semiconductor substrate via an interlayer insulating film, wherein a convex portion of the insulating film is formed in a predetermined region of the interlayer insulating film. Providing a surface step on the film, forming a wiring groove insulating film on the interlayer insulating film having the surface step, forming a wiring groove in the wiring groove insulating film, and filling the wiring groove with a metal film A first trench wiring along the convex portion of the insulating film, which is located above the surface step, and a second trench wiring extending below the surface step.
Forming the trench wirings adjacent to each other and vertically apart from each other in the vertical direction with respect to the semiconductor substrate. 6. The method of manufacturing a semiconductor device according to claim 5, wherein an etching stopper layer is formed between the interlayer insulating film having the insulating film protrusion and the insulating film for a wiring groove. 7. The method according to claim 5, wherein the metal film is made of a metal containing copper.