JP2001067382A - Logic circuit synthesizing method and storage medium storing program of the synthesizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a logic circuit small in the scale and less in the power consumption by using the least number of transistors and a given logical expression. SOLUTION: A logical expression is shown in a BDD (S1). A part to which the multi-stage logical optimization is applied is extracted from the BDD expression and replaced with an intermediate variable to generate a new BDD (S2). In the same way, the part to be replaced with the intermediate variable is searched and the part to which the multi-stage logical optimization is applied is replaced with an intermediate variable to obtain the final BDD (S3). Then the BDD is converted into an MUX cell to generate a circuit (S4). The intermediate variable serving as the input of the circuit consisting of the MUX cell that is generated from the BDD is replaced with a circuit which is optimized by the multi-stage logical optimization (S5).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for synthesizing a logic circuit used for a design automation technique in circuit design of a semiconductor integrated circuit or the like, a circuit optimization technique, and a storage medium for storing a program thereof.

[0002]

2. Description of the Related Art In the design of large-scale integrated circuits such as LSIs, the use of a top-down design technique for describing a circuit to be designed in a hardware description language and synthesizing a logic circuit using a logic synthesis device has become widespread. ing. There are a plurality of logic synthesis methods, and the most general method is an algebraic multi-stage logic synthesis method (conventional method 1).
This method aims at optimizing a circuit by extracting common terms from a logical expression and increasing the number of stages, which is disclosed in, for example, JP-A-5-242193.

When the circuit system of the circuit to be designed is a pass transistor circuit or the like, a BDD (Binary
A method (conventional method 2) using a Decision Diagram (Binary Decision Diagram) is known. BDD is basically 0
This is a method of expressing a logical function by a binary tree of nodes having two branches called -branch and 1-branch. The detailed description is given in Information Processing Society of Japan, Information Processing, Vol. 34, No. 5, MAY 1993, pp. 593-599. There are various types of BDDs, and in many cases, the order relation of input variables that appear from the root node to the end throughout the BDD is fixed. Hereinafter, the BDD in the present invention is based on a type of BDD that fixes the order relation of input variables. As a logic synthesis method using BDD, for example, Japanese Patent Application Laid-Open No. 9-97281 reports a method of synthesizing a circuit from BDD.

[0004]

According to the conventional method 1, the following logical expressions are synthesized. s0 =! c0 *! c1 *! c2 *! (A00 + a01) + (c0 + c1 + c2) *! (B00 + b01) (1) s1 =! c0 *! c1 *! c2 *! (A10 + a11) + (c0 + c1 + c2) *! (B10 + b11) (2)

The following intermediate variable t is introduced to simplify the circuits of the above logical expressions (1) and (2). t =! (C0 + c1 + c2) s0 = t *! (A00 + a01) +! t *! (B00 +
b01) s1 = t *! (A10 + a11) +! t *! (B10 +
b11) As a result, a circuit as shown in FIG. 7 is generated. The number in each gate in FIG. 7 is the number of transistor pairs, and the total is 29 transistor pairs.

In the conventional method 2, the above-mentioned logical expression (1),
The circuit of (2) is synthesized. The BDD node can be replaced with a circuit using a pass transistor as shown in FIG. 8, and two transistors are required for each node. FIG. 9 shows the logical expressions (1) and (2) expressed in BDD. The number of nodes is 14 (a _{00 to} c
₂ to 14), and three of them (nodes a01, b01, and b11 in FIG. 9) become input only when replaced by a transistor circuit like node b of BDD in FIG. No conversion is required. That is, when the nodes a01, b01, and b11 are replaced by pass transistors, the branch a in FIG. 8 is always fixed to 1 and the branch b is fixed to 0, and is not affected by other inputs. . FIG. 10 shows a case where the zero branch of the node a is fixed. Therefore, (14-3) * 2 = 22, and the number of gates is 22 transistor pairs.

By combining the logical expressions (1) and (2) without using the conventional methods 1 and 2, it is possible to realize a circuit of 15 transistor pairs as shown in FIG. However, as described above, the circuit of FIG. 11 cannot be generated by the conventional methods 1 and 2. This is because Conventional Method 1 and Conventional Method 2 each have a circuit configuration that they are good at and a circuit configuration that they are not good at. For example, logical expressions (1) and (2)
Includes a selector logic (a circuit structure for selecting one input from a plurality of inputs), but does not use a MUX cell in the circuit generated by the conventional method 1. On the other hand, circuit synthesis by BDD
Since the BDD itself is expressed by the selector logic, the selector logic included in the logical expression can be easily detected. However, since parts other than the selector logic are realized by the selector logic, there is a disadvantage that the area is eventually increased.

[0008] The object of the present invention is to provide, from a given logical expression,
An object of the present invention is to provide a logical formula synthesis method for designing a circuit with a small circuit size and low power consumption by realizing a circuit with the minimum number of transistors, and a recording medium storing the program.

[0009]

According to the present invention, a circuit to be designed expressed by a logical expression, a hardware description language, or the like is used.
In a logic circuit synthesis method for generating a gate circuit or a transistor circuit, a first step of graphically expressing a logical expression in BDD, and extracting a portion to which multi-stage logic optimization is applied from the graphed BDD, and intermediate the portion A second step of newly constructing the BDD by substituting variables,
A third step of replacing the part to which the multi-stage logic optimization is applied with an intermediate variable, applying the multi-stage logic optimization and generating a circuit, and MUX the BDD newly constructed in the second step.
A fourth step of converting the cell into a cell to generate a circuit, and converting the intermediate variables of the portion extracted in the second step, which are input to the circuit obtained in the fourth step, by the circuit selected in the third step And a fifth step of replacement.

The present invention also provides a method for converting a logical expression into a BDD in a storage medium storing a logical circuit synthesis program for generating a gate circuit or a transistor circuit from a design target circuit expressed by a logical expression or a hardware description language.
The first step in which the graph is expressed by
A second step of extracting a portion to which the multi-stage logic optimization is applied from the DD and replacing the portion with an intermediate variable to newly construct a BDD; and replacing the portion to which the multi-stage logic optimization is applied with an intermediate variable Then, a third step of applying a multi-stage logic optimization to generate a circuit, a fourth step of converting a BDD newly formed in the second step into a MUX cell to generate a circuit, and a fourth step of And a fifth step of replacing an intermediate variable of a portion extracted in the second step, which is an input of the circuit, with a circuit selected in the third step.

[0011] The second step includes some further steps, but before that, some terms will be explained. Variable order: The order of the variable of the node from the top node of the BDD to the constant node. The order is lower near the constant node. -Lower-order node: A node adjacent to the target node and having a lower variable order than the target node. That is, the nodes connected to the 0-branch and the 1-branch of the target node. -Replacement target node set: A set of nodes that may be replaced by intermediate variables. -Replacement target node all candidate set: A set of lower-order nodes of the nodes belonging to the replacement node set. -Replacement target node candidate set: A set obtained by removing constant nodes and intermediate variable nodes from all replacement target node candidate sets. -Target upper node: A node having a higher variable order among the elements of the replacement target node candidate set. -Unsearched upper node: BDD excluding intermediate variable node
Is the node with the highest variable order among the nodes that have never been in the replacement candidate node all candidate set. -Intermediate variable node ... A node replaced by an intermediate variable.

The second step is a step of setting a node N as an unsearched upper node, a step of empty-setting a set of replacement target nodes, a step of adding a node N to the set of replacement target nodes, Determining whether or not the target upper node is to be added to the replacement target node set, and determining whether the number of elements of the replacement target node all candidate set of the replacement target node set after addition is 2 or less. , The number of elements in the replacement target node set is 2
It is desirable to have a step of determining whether the above is the case, a step of replacing the replacement target node set with an intermediate variable to generate a new BDD, and a step of determining that there is no unsearched upper node.

With the above arrangement, the present invention expresses a given logical expression in BDD, extracts a part to which multi-stage logic optimization is applied from the BDD structure, and extracts the other part from the BDD structure. Can be directly replaced with MUX cells, thereby reducing the number of transistors of a circuit to be realized.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a flowchart showing the flow of processing in the logic circuit synthesis method according to the present invention. This is a process for realizing the circuit synthesis of the logical expressions (1) and (2). First, the logical expressions (1) and (2) are expressed by BDD (step S1). When represented by this BDD, FIG.
become that way.

Next, a portion to which the multi-stage logic optimization is applied is extracted from the BDD expression of FIG. 9 and the portion is replaced with an intermediate variable to newly generate a BDD (step S2). FIG.
Is a flowchart showing the flow of the process in step S2. The processing in step S2 will be described in detail.
(Hereinafter, the logical expression (2) will be described, but the same applies to the logical expression (1).)

In step S21, the node N is set as an unsearched upper node c0. By step S22, the replacement target node set is set to an empty set. The element of the replacement target node set is added to the node N to be {c0}.

In step S24, it is confirmed whether or not there is a target higher-order node. Since there is a target higher-order node c1, step S25 is executed. In step S25, the target higher-level node is c1, and attempts to add c1 to the replacement target node set (G), and confirms whether the number of elements of the replacement target node all candidate set after addition is 2 or less. Since the total number of replacement target node candidate sets of the replacement target node set {c0, c1} after addition is two, {c2, b10},
Step S24 is executed with the replacement target node set as {c0, c1}.

In step S24, the target upper node c2
Exists, so step S25 is executed. In step S25, the target upper node is c2, and attempts to add c2 to the replacement target node set (G). Since the number of replacement target node candidate sets in the replacement target node set {c0, c1, c2} after addition is two {a10, b10}, step S24 is executed next.

The dotted lines 11 and 12 of the ellipse in FIG. 3 do not form a set of nodes to be replaced. Therefore, it is necessary to replace the replacement node set {c0, c1, c2} of the solid line portion 13 of the ellipse with an intermediate variable, and introduce a new intermediate variable t as shown in FIG. That is, the solid line part 1 of the ellipse in FIG.
3 is set to the intermediate variable t in {c0, c1, c2}.
0 (FIG. 4 (b)). Assuming that the logical expression of this t0 is t0 = c0 * c1 * c2, the BD using the intermediate variable t as shown in FIG.
D is newly generated.

Similarly, a portion to be replaced with an intermediate variable is searched, and portions 14, 15, 16, and 15 enclosed by solid lines in FIG.
17 and 18 are parts to which the multi-stage logic optimization is applied, and are replaced by intermediate variables t1, t2, t3, t4 and t5, and finally the BDD as shown in FIG. 6 (step S2). In the BDD of FIG. 6, nodes t0 and t4 are allocated to MUX cells, and a circuit is generated. Also, nodes t1, t2,
t3 and t5 do not require a transistor as in the case of the node b in FIG. 10, that is, they do not become MUX cells (step S4). The intermediate variable input to the circuit composed of the MUX cells generated from the BDD is replaced by a circuit optimized by multi-stage logic optimization (step S3). Therefore, the circuit finally becomes as shown in FIG. 11 (step S5).

When BDD is simply used, the logical expression (1)
When the circuit shown in (2) is combined, the number of pairs becomes 22. However, by using the present invention, the number of pairs can be reduced to a minimum of 15 pairs. In this way, a circuit can be realized with 20% to 30% fewer transistors than the conventional method.

[0023]

According to the present invention, a given logical expression is represented by B
Expressed in DD, the part to which the multi-stage logic optimization is applied is extracted from the BDD structure, and the other part is
By directly replacing the DD structure with a MUX cell,
The number of transistors of a circuit to be realized can be reduced. Since the number of transistors can be reduced, the chip area can be reduced, and the gate capacity of the entire chip can be reduced, so that power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow in a logic circuit synthesis method according to the present invention.

FIG. 2 is a flowchart showing the flow of the process of step S2.

FIG. 3 is a diagram for explaining extraction of a portion to which multi-stage logic optimization is applied from nodes of the BDD;

FIG. 4 is a diagram for explaining generation of a new BDD by extracting a portion to which multi-stage logic optimization is applied from nodes of the BDD and introducing intermediate variables;

FIG. 5 is a diagram showing a portion in which a given logical expression is expressed in a BDD, and of which a multi-stage logical optimization is applied;

6 is a diagram showing a BDD finally obtained by extracting a part to which multi-stage logic optimization is applied from the nodes of the BDD of FIG. 10 and replacing the part with an intermediate variable node;

FIG. 7 is a logic circuit diagram generated by a conventional method 1.

FIG. 8 shows a case where the node of BDD is M using a pass transistor.
It is a figure explaining being replaced with a UX cell.

FIG. 9 is a diagram showing a BDD generated from a given logical expression.

FIG. 10 is a diagram illustrating a case where the 0 branch of a BDD node is a constant node 0;
FIG. 9 is a diagram illustrating that a node whose one branch is connected to a constant node 1 becomes a path input;

FIG. 11 is a circuit diagram in which the number of transistors generated from a given logical expression is optimal.

[Explanation of symbols]

 S1 to S5 Steps in the process of logic synthesis S21 to S28 Steps 11 and 12 in the process of step S2 Node set not to be replaced 13 to 18 Node set to be replaced

Claims (4)

[Claims] 1. A logic circuit synthesis method for generating a gate circuit or a transistor circuit from a circuit to be designed expressed by a logical expression, a hardware description language, or the like, a first step of graphically expressing the logical expression in BDD; From the expressed BDD, a part to which multi-stage logic optimization is applied is extracted, and the part is replaced with an intermediate variable,
A second step of newly constructing D; a third step of replacing the portion to which the multi-stage logic optimization is applied with an intermediate variable, applying a multi-stage logic optimization to generate a circuit; A fourth step of converting the configured BDD into a MUX cell to generate a circuit, and a second step of inputting the circuit obtained in the fourth step.
A fifth step of replacing the intermediate variable of the portion extracted in the step with the circuit selected in the third step. 2. The method according to claim 1, wherein the second step is a step of setting a node N as an unsearched upper node, a step of empty-setting a set of replacement target nodes, a step of adding the node N to the set of replacement target nodes, A step of determining whether or not there is, and attempting to add the target upper node to the replacement target node set, and determining whether the number of elements of the replacement target node all candidate set of the replacement target node set after addition is 2 or less. A step of determining whether the number of elements of the replacement target node set is 2 or more; replacing the replacement target node set with an intermediate variable;
A logic circuit synthesis method, comprising: generating a DD; and determining that there is no unsearched upper node. 3. A logical expression is represented by BDD in a storage medium storing a logic circuit synthesis program for generating a gate circuit or a transistor circuit from a design target circuit expressed by a logical expression, a hardware description language, or the like. A first step, extracting a part to which the multi-stage logic optimization is applied from the graphed BDD, replacing the part with an intermediate variable,
A second step of newly constructing D; a third step of replacing the portion to which the multi-stage logic optimization is applied with an intermediate variable, applying a multi-stage logic optimization to generate a circuit; A fourth step of converting the configured BDD into a MUX cell to generate a circuit, and a second step of inputting the circuit obtained in the fourth step.
A fifth step of replacing an intermediate variable of a portion extracted in the step with a circuit selected in the third step; and a recording medium recording a logic circuit synthesis program. 4. The second step comprises: setting a node N as an unsearched upper node; empty-setting a replacement target node set; adding a node N to the replacement target node set; A step of determining whether or not there is, and attempting to add the target upper node to the replacement target node set, and determining whether the number of elements of the replacement target node all candidate set of the replacement target node set after addition is 2 or less. A step of determining whether the number of elements of the replacement target node set is 2 or more; replacing the replacement target node set with an intermediate variable;
The recording medium according to claim 3, further comprising: generating a DD; and determining that there is no unsearched upper node.