JP2001061067A - Image processing unit, its method, data processing unit and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image processing unit that realizes effective coding and to obtain its method, a data processing unit and its control method. SOLUTION: An image processing circuit 50 converts image data of a CCD- RAW form into RGB image data depending on a setting of a recording mode switch 34, a JPEG circuit 80 applies JPEG compression to the image data or a data conversion circuit 100 and a Huffman coding/decoding circuit 86 apply reversible compression to the image data. A recording medium 70 stores the compressed image data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method, and a data processing apparatus and control method thereof. For example, the present invention relates to an image processing apparatus for processing image data obtained by an image sensor and a method thereof. .

[0002]

2. Description of the Related Art When compressing and recording an image or arbitrary input data, a discrete cosine transform (DC
T) or DPCM (Differential Pulse Ci
After reducing the entropy of the input data sequence by performing ode modulation) conversion or the like, the input data is compressed by performing entropy encoding represented by Huffman code or arithmetic code.

[0003] Huffman coding allocates a short codeword to data having a high frequency of appearance and a long codeword to data having a low frequency of appearance from a histogram of an input data sequence, and reduces the data size on average to reduce data compression. To achieve.

[0004] JPEG using DCT and Huffman coding
In the baseline method, encoding processing is performed according to the set Huffman table. All information necessary for encoding is described in the Huffman table, and the description is generated from a histogram of a data sequence to be encoded.

[0005]

In order to realize the most effective coding in Huffman coding, it is necessary to calculate a histogram of a data sequence to be coded and generate a unique Huffman table corresponding to each data sequence. There is.

However, in image compression / expansion of a digital camera (electronic camera) or the like, a single Huffman table provided as a standard is used due to problems such as processing speed. Therefore, effective encoding (compression) is not always realized.

An object of the present invention is to solve the above-mentioned problems and to provide an image processing apparatus and method for realizing effective encoding, and a data processing apparatus and control method therefor. I do.

[0008]

The present invention has the following configuration as one means for achieving the above object.

A data processing apparatus according to the present invention comprises: a memory in which a plurality of different Huffman tables are stored; an encoding means for Huffman encoding input data; and the plurality of different Huffman tables sequentially set in the encoding means. And
Control means for selecting a code having the smallest data size from the coding results corresponding to the respective Huffman tables.

A method for controlling a data processing apparatus according to the present invention is a method for controlling a data processing apparatus having a memory in which a plurality of different Huffman tables are stored, and an encoding means for Huffman encoding input data. The plurality of different Huffman tables are sequentially set in the encoding unit, and a code having the smallest data size is selected from the encoding results corresponding to the respective Huffman tables.

An image processing apparatus according to the present invention is an image processing apparatus having compression means for compressing image data, and memory control means for storing compressed image data on a recording medium, wherein the compression means is at least A memory in which a plurality of different Huffman tables are stored, encoding means for Huffman encoding the imaging data, and setting the plurality of different Huffman tables in the encoding means in order,
Encoding control means for selecting a code having the smallest data size from encoding results corresponding to the respective Huffman tables and supplying the selected code to the memory control means.

An image processing method according to the present invention is a method for compressing image data and storing the compressed image data on a recording medium, wherein the compression processing includes at least:
Using a plurality of different Huffman tables in order, the imaging data is Huffman-encoded, a code having the smallest data size is selected from the encoding results corresponding to the respective Huffman tables, and stored in the recording medium. I do.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

[Configuration] FIG. 1 is a block diagram showing a configuration example of an image processing apparatus 1000 according to an embodiment of the present invention.

An image of an object to be photographed is optically formed by a photographing lens 10 on an image sensor 12 such as a CCD for converting a photographed image into an electric signal. An analog output signal of the image sensor 12 is converted into a digital signal by the A / D converter 14. In the following, the image data output from the A / D converter 14 is referred to as C to distinguish it from the signal-processed image data.
Called CD-RAW data.

The memory control circuit 40 includes an A / D converter 14, a D / A converter 20, an image processing circuit 50, and a memory 6, which will be described later.
0, the data flow in the recording medium 70, the JPEG circuit 80, and the data conversion circuit 100 is controlled. The memory control circuit 40 includes a plurality of memory control circuits dedicated to writing data to the memory 60 and a plurality of memory control circuits dedicated to reading data from the memory 60.

The image processing circuit 50 performs a pixel interpolation process and a color conversion process on CCD-RAW data having an element arrangement (for example, a Bayer arrangement) as shown in FIG. Form RGB image data.

The memory 60 is a memory for storing photographed still images and moving images, and has a sufficient storage capacity for storing a predetermined number of still images and moving images for a predetermined time. The CCD-RAW data output from the A / D converter 14 is written to the memory 60 via the memory control circuit 40 and the image processing circuit 50 or directly from the memory control circuit 40. The display image data formed by the image processing circuit 50 from the CCD-RAW data and written to the memory 60 is transmitted to an image display unit such as a TFT LCD via the memory control circuit 40 and the D / A converter 20. Appears on 22.

The recording medium 70 is preferably a removable medium such as a semiconductor memory card, a magnetic recording medium floppy disk or hard disk, or a magneto-optical disk.

The JPEFG circuit 80 includes a DCT / quantization circuit 82, a data selector 84, a Huffman encoding / decoding circuit 86,
Image data is compressed / expanded by the baseline JPEG method. The data selector 84 switches the flow of data between a case where JPEG encoding / decoding of image data and a case where CCD-RAW data is reversibly compressed / expanded, that is, according to a recording mode described later.

The data conversion circuit 100 performs data conversion for reversibly compressing and expanding CCD-RAW data using the Huffman encoding / decoding circuit 86 of the JPEG circuit 80. The data conversion core 104 includes a synthesis circuit 106 and a DPCM conversion circuit 108. In addition,
The data conversion core circuit 104 is a part that actually performs the data conversion processing in the present embodiment.

The interface circuit 102 is constructed such that the data conversion circuit 100 is connected to another circuit block (for example, the memory control circuit 40).
And a JPEG circuit 80) to perform data handshaking with the data conversion core.
Simultaneously with the design of the 104, software development for controlling data transfer of the entire system is facilitated. The detailed configuration and operation will be described later.

The Huffman encoding / decoding circuit 86 is a circuit designed for the baseline JPEG. The data bus between the data selector 84 and the Huffman encoding / decoding circuit 86 has 11 bits. Therefore, the CCD-RAW data subjected to the DPCM conversion needs to be 10 bits or less.

The dividing / synthesizing circuit 106 performs
-If the RAW data is 12 bits, divide it into upper 10 bits and lower 2 bits and pack the lower 2 bits every 8 data
(Pack) to process. If the CCD-RAW data is 12 bits at the time of decompression, the lower 2 bits of the PACKed data are UNPACK-processed, and the DPCM conversion circuit 108
And synthesizes with the inverse DPCM converted 10-bit data.
FIG. 2 shows the data format in the division and PACK processing, and the UNPACK and synthesis processing.

The DPCM conversion circuit 108 performs DPCM conversion (prediction coding) of CCD-RAW data in order to reduce the entropy of information and increase the coding efficiency in Huffman coding. The DPCM conversion circuit 108 performs DPC conversion on 10-bit data.
Performs M conversion (prediction coding) and performs inverse DPCM conversion on the 11-bit DPCM data. The DPCM transform is to reduce the entropy of information by utilizing the fact that there is a strong correlation between the image information of the target pixel to be encoded and the image information of the peripheral pixels. Specifically, the coding efficiency in Huffman coding is increased by converting the image data of the pixel of interest into a difference value from the image data of the adjacent pixel (the pixel on the left).

This embodiment corresponds to the image sensor 12 having the color filter array of the element array as shown in FIG. 3, and it is necessary to always calculate the difference value with the CCD-RAW data adjacent to the left of two pixels. . That is, the DPCM conversion circuit 108 is configured to calculate the difference between the input CCD-RAW data and the CCD-RAW data input two pixels earlier. In addition, since the prediction in the DPCM conversion is easier for the lower frequency components of the image, the CCD-
If the RAW data is 12 bits, only the upper 10 bits are subjected to DPCM conversion, and high-frequency components that are difficult to predict are recorded without compression. More detailed configuration and operation will be described later.

The data selector 90 switches the data flow between when performing JPEG encoding / decoding and when performing lossless compression / expansion of CCD-RAW data, that is, according to a recording mode described later.

The system control circuit 30 includes a CPU, a RAM, a ROM, and the like, and stores programs stored in the ROM,
Setting of the mode dial 32 and the recording mode switch 34,
In addition, according to the recorded contents of the read-only memory (ROM) 36,
The operation of the entire image processing apparatus 1000 and each circuit block is controlled.

The mode dial 32 is for the user to switch the function mode of the image processing apparatus 1000, such as power on / off, photographing mode and reproduction mode. The recording mode switch 34 is for the user to select one of a lossless compression / expansion mode for CCD-RAW data and a JPEG recording mode. When the user selects the JPEG recording mode, the compression ratio and the like are also set in the recording mode switch 34.
Can be set by The read-only memory 36 stores a program executed by the system control circuit 30, a quantization table and a Huffman table set in the JPEG circuit 80, and the like.

[Data Conversion Core] FIG. 4 shows a data conversion core 1.
FIG. 4 is a block diagram showing a detailed configuration example of 04. FIG. 4
In FIG. 7, the parts other than the DPCM conversion circuit 108 correspond to the dividing / combining circuit 106.

A pair of VALID signal and STOP signal exist in every data series input / output to the data conversion core 104. When the VALID signal is “1”, the input / output data is valid, and when the STOP signal is “1”, the data input / output is invalid. When the VALID signal accompanying the input / output data is “1” and the STOP signal is “0”, the data conversion core 104 performs processing assuming that valid data is input / output. The following six types of data series are input / output to / from the data conversion core 104. CCD_IN_DATA: CCD-RAW data to be compressed (from memory control circuit 40) DPCM_OUT_DATA: DPCM-converted data (JPEG circuit 80
To) PACK_DATA: PACKED lower 2 bits data (to memory control circuit 40) CCD_OUT_DATA: Expanded CCD-RAW data (to memory control circuit 40) DPCM_IN_DATA: Data to be inverse DPCM converted (from JPEG circuit 80) UNPACK_DATA : Data to UNPACK

A VALID signal (input) and a STOP signal (output) are attached to each input data sequence, and a VALID signal (output) and a STOP signal (input) for each output data sequence.
Is included.

The STOP signal input to the data conversion core 104 accompanying the output data of the data conversion core 104 is DPCM_OU
T_STOP, PACK_STOP and CCD_OUT_STOP.

Blocks in which these STOP signals are set to "1" means that data output from the data conversion core 104 cannot be received, and the output data of the data conversion core 104 becomes invalid. Therefore, when any of these STOP signals is “1” and the corresponding VALID signal is “1”, all flip-flops (buffers) in the data conversion core 104 are in the holding state, and all the STOP signals are “1”. No data is updated until it reaches 0 '.

On the other hand, the STOP signal output from the data conversion core 104 accompanying the input data of the data conversion core 104 is of three types: CCD_IN_STOP, DPCM_IN_STOP, and UNPACK_STOP.

When these STOP signals are “1”, it means that the data conversion core 104 cannot receive the input data, and the input data from the block to which the STOP signal is connected is
It is not updated until the STOP signal becomes '0'. Therefore, the control signal generator 180 or 182 of the data conversion core 104 is used to delay the next data input according to the operation state inside the data conversion core 104, or to receive data from a plurality of blocks and wait for the data. In this case, the update of the data input to the data conversion core 104 can be temporarily interrupted by setting the STOP signal to be sent to the corresponding block to “1”.

Reversible compression of CCD-RAW data Data conversion core 104 for reversibly compressing CCD-RAW data
Is as follows.

CCD-RAW data to be compressed (CCD_IN_DATA)
Is buffered when the VALID signal (CCD_IN_VALID) is '1'.
When the VALID signal (CCD_IN_VALID) is “0”, the CCD-RAW data read into the buffer 184 is held. FIG. 5 shows an example of the data format of the CCD-RAW data held in the buffer 184. Regardless of the data width of the CCD-RAW data, the 10-bit data from the 11th bit to the 2nd bit of the data held in the buffer 184 is D
The data is transferred to the PCM conversion circuit 108 and DPCM conversion is performed. DPCM
The converted data is temporarily stored in the buffer 190 and then output from the data conversion core 104. The control signal generator 180 outputs a DP signal from the input VALID signal (CCD_IN_VALID).
VALID signal (DPCM_OUT_VAL) corresponding to the CM-converted data
ID) and output it according to the DPCM-converted data.

When the data width of the CCD-RAW data is 12 bits, the lower 2 bits are separated and the PACK processing is performed according to the format shown in FIG. The lower two bits of the data held in the buffer 184 are held in any of the eight buffers 200 to 214. Control signal generator
180 counts the input VALID signal (CCD_IN_VALID) to determine the order in which the data held in the buffer 184 is the input data, and based on the determination result, the buffers 200 to 214 An 8-bit control signal for selecting one of them is generated. The buffer whose corresponding bit of the 8-bit control signal is “1” updates the data by reading 2-bit data from the buffer 184. on the other hand,
The buffer in which the corresponding bit of the 8-bit control signal is '0' holds data.

The output of the buffers 200 to 214 is
Connected to. The data of the buffer 192 is updated every eight input data by the control signal of the control signal generator 180,
The updated data is output as PACKed data. At this time, the control signal generator 180 outputs a VALID signal (PACK_VALID) of '1' corresponding to the PACK data.

The operation of the data conversion core 104 when expanding CCD-RAW data is as follows.

The DPCM data to be subjected to inverse DPCM conversion (DPCM_IN
_DATA) is read into the buffer 188 when the VALID signal (DPCM_IN_VALID) is “1”, and the DPCM data read into the buffer 188 is held when the VALID signal (DPCM_IN_VALID) is “0”. The DPCM data held in buffer 188 is D
Inverse DPCM conversion and inverse conversion by PCM conversion circuit 108
The 10-bit data is input from the eleventh bit to the second bit of the buffer 194. When the original data width of the compressed and recorded CCD-RAW data is 10 bits, '00' corresponding to the lower 2 bits of the buffer 194 is input to the buffer 194 via the multiplexer 198 as dummy data. Buffer 1
The output of 94 is expanded CCD-RAW data (CCD_OUT_DATA)
Is output as The control signal generator 182 receives the input V
A VALID signal (CCD_OUT_VALID) for the decompressed data is created from the ALID signal (DPCM_IN_VALID) and output according to the CCD-RAW data.

When the original data width of the compressed and recorded CCD-RAW data is 12 bits, UNPACK and synthesis processing of the lower 2 bits are performed according to the format shown in FIG. U
The data to be NPACK (UNPACK_DATA) is the VALID signal (UNPACK
When (_VALID) is '1', it is read into buffer 186 and VALID
When the signal (UNPACK_VALID) is “0”, the data read into the buffer 186 is held. The data held in the buffer 186 is read out two bits at a time by the multiplexer 196 and connected to the lower two bits of the buffer 194 via the multiplexer 198.

Which two bits are selected by the multiplexer 196 is determined by a 4-bit control signal of the control signal generator 182. The control signal generator 182 counts the input VALID signal (DPCM_IN_VALID), determines the order of the 10-bit data input to the buffer 194, and generates a 4-bit control signal. Further, the control of causing the multiplexer 198 to select the output of the multiplexer 196 or the dummy data '00' is also performed by the 4-bit control signal.

The 12-bit data synthesized in the buffer 194 is expanded CCD-RAW data (CCD_OUT_DATA).
Is output as The control signal generator 182 receives the input V
A VALID signal (CCD_OUT_VALID) corresponding to the data expanded from the ALID signal (DPCM_IN_VALID) is created and output in accordance with the CCD-RAW data.

The data in the buffer 186 is updated only once for every eight data subjected to the inverse DPCM conversion. Therefore, the control signal generator 182 receives the input VALID signal (DPCM_
STOP signal (UNPACK_STOP) while counting IN_VALID)
By creating and outputting the upper 10 bits of data and the lower 10 bits.
The process of waiting for data with 2 bits is easily performed.

FIG. 6 is a timing chart showing a specific example of the waiting process.

In the following, for simplicity of explanation, the DPCM
The data sent from the conversion circuit 108 to the buffer 254 is
The VALID signal and STOP signal associated with DATA and 10bit_DATA will be described as 10bit_VALID and 10bit_STOP, respectively.
Actually, the control signal generator 182 performs control in consideration of the data delay of the DPCM conversion circuit 108.

At timing t1, the UNPACK_VALID signal is “1” and the UNPACK_STOP signal is “0”.
P1, which is DATA, is read into the buffer 186. UNPACK_DA
Since the TA is updated only twice for eight 10-bit_DATAs, the control signal generator 182 sets the UNPACK_STOP signal to “1” so as not to be updated to P2 of the UNPACK_DATA at the next timing t2.

At timing t2, since the 10-bit VALID signal is "1", the selected data D1 and P1 are combined in the buffer 194 and output as CCD_OUT_DATA. The control signal generator 182 sets the CCD_OUT_VALID signal to “1”.

At timing t8, the selected data
D7 and P1 are combined in buffer 194 to form CCD_OUT_DATA
Is output as Since the processing of synthesizing the seven data ends by the processing at timing t8, it is necessary to update the data in the buffer 186 after the processing of synthesizing the eighth data ends at the next timing t9. for that reason,
At timing t8, the control signal generator 182 changes the UNPACK_STOP signal from “1” to “0”.

At timing t9, the selected data
D8 and P1 are combined in buffer 194 to form CCD_OUT_DATA
Is output as On the other hand, P2 of UNPACK_DATA is read into the buffer 186. Then, similarly to the timing t1, the control signal generator 182 sets the UNPACK_STOP signal to “1”.

At a timing t10, the selected data D9 and P2 are combined in the buffer 194 to obtain CCD_OUT_DAT
Output as A. Further, since the UNPACK_VALID signal is “0”, there is no need to issue a STOP signal, so the control signal generator 182 sets the UNPACK_STOP signal to “0”.

At a timing t17, the selected data D16 and P2 are combined in the buffer 194 and the CCD_OUT_DA
Output as TA. Since the processing of synthesizing the eight data D9 to D16 is completed by the processing at timing t17, the data in the buffer 186 needs to be updated. But UNPAC
The K_VALID signal is '0' and UNPACK_DATA is undefined. Therefore, the synthesizing process cannot be performed at the next timing t18, and the control signal generator 182 sets the 10-bit_STOP signal to “1” so that 10-bit_DATA is not updated.

At timing t18, the 10-bit_STOP signal is "1", so that 10-bit_DATA is not updated with D17. Also, since the UNPACK_VALID signal is '1',
P3 of K_DATA is read into the buffer 186. Timing t
Similarly to 1, the control signal generator 182 sets the UNPACK_STOP signal to “1”.

At the timing t19, the selected data D17 and P3 are combined in the buffer 194 and the CCD_OUT_DA
Output as TA.

As described above, the data conversion core 104 performs the STOP
By outputting the signal as needed, the queuing process can be easily realized. In addition, since the data conversion core 104 implements the queuing process in hardware, the system control circuit 30 hardly needs to control data transfer between the circuit blocks.

[Interface Circuit] As described above, the data conversion core 104 uses the VALID signal and the STOP signal to
A waiting process when data is received from two blocks is easily realized. However, in order to actually perform data handshake with another block, an interface circuit 102 for controlling the VALID signal and the STOP signal is required around the data conversion core 104.

FIG. 7 is a block diagram showing an example of the most basic configuration of the interface circuit 102.

An arithmetic unit 302 corresponding to the data conversion circuit 100 includes an interface circuit 102 for performing handshaking of data with the arithmetic units 300 and 304, and an arithmetic circuit 308 corresponding to a data conversion core 104 for processing input data. Composed of The plurality of operation units configuring the system are based on the configuration of the operation unit 302,
All blocks are designed with a similar configuration.

All data sequences propagating between units have a pair of VALID signals and a STOP signal for each data sequence.
Accompanied by a signal. All data transfer between each processing unit in the device is controlled by these signals.

The VALID signal indicates that the data sequence transferred between the operation units is valid data at a certain timing, and is propagated in the same direction as the data sequence. In the present embodiment, the VALID signal is '1'
The cycle of means that the data series is valid, and only one cycle of the valid data series is output.

The STOP signal is used to stop updating the data of the input data sequence when the data to be input at the next timing cannot be processed because the arithmetic unit that should receive the data is processing the data. Is propagated in a direction opposite to the propagation direction of the data sequence. In this embodiment, a cycle in which the STOP signal is “1” means that the arithmetic unit cannot perform data processing.

As described above, the purpose of the interface circuit 102 is to facilitate the design of the arithmetic circuit 308 for performing data processing and to facilitate the control of the entire system.

At a certain timing, the arithmetic circuit 308 receives data only when the input VALID_IN signal is “1” and performs necessary data processing. When valid data transfer is performed to the operation unit 304 connected to the subsequent stage, the VALID_OUT signal is set to “1”. However, VALI
Even in the cycle in which the D_OUT signal is '1', OUT_STO which is a STOP signal from the arithmetic unit 304 connected to the subsequent stage
When the P signal is “1”, the STOP_OUT signal which is a STOP signal to the arithmetic circuit 308 becomes “1”. That is, since the arithmetic unit 302 cannot update data, all internal states in the arithmetic circuit 308 are held. Also, the arithmetic unit 3 connected before the arithmetic unit 302
If you want to stop data transfer from 00, set the STOP_IN signal to '1'. That is, the VALID_IN signal is '1',
The arithmetic circuit 308 fetches valid data only when the STOP_IN signal and the STOP_OUT signal are “0”.

In actual data processing, the arithmetic circuit 30
Most control can be performed only by counting the VALID signal input to 8.

The interface circuit 102 is located around the operation circuit 308 that actually performs data processing, and performs data handshaking with an adjacent operation unit. The basic configuration of the interface circuit 102 includes a buffer 110 composed of n D flip-flops corresponding to the bus width (n bits) of the input data IN_DATA, one D flip-flop, and n + 1 bit output. And a plurality of logic gates.

[Functions of Interface Circuit]
FIG. 8B is a timing chart showing the relationship between the data, the VALID signal and the STOP signal in detail, and explains the function of the interface circuit 102. The arithmetic circuit 308, the arithmetic unit 300, and the arithmetic unit 304 in the present embodiment
Are merely assuming operations for explanation. 8A and 8B are a series of timing charts.

At the timing t0, the output of the D-FF 112 is reset to “0” by the reset signal RESET. As a result, the IN_STOP signal output from the arithmetic unit 302 becomes “0”. The selector 114 is connected to the data input side (non-buffer
110), the IN_DATA and IN_VALID signals are directly connected to the DATA_IN and VALID_IN signals of the arithmetic circuit 308.

At timing t 1, the input data DATA_IN is undefined and the VALID_IN signal input to the arithmetic circuit 308 is “0”, so that the arithmetic unit 302 does not perform any processing. Immediately after t1, the arithmetic unit 30 connected to the previous stage
Since the input data IN_DATA from 0 is determined and the IN_VALID signal changes to '1', the VA input to the arithmetic circuit 308
The LID_IN signal changes to '1'.

At timings t 2 and t 3, since the VALID_IN signal and the STOP_IN signal and the STOP_OUT signal input to the arithmetic circuit 308 are “0”, D 1 and D 2 of IN_DATA are valid via the selector 114 The data is read into the arithmetic circuit 308 and processed.

At timing t4, the VALID_IN signal input to the arithmetic circuit 308 is "1", but the arithmetic circuit 308
Indicates '1'. In other words, it means that the arithmetic circuit 308 is currently processing data and cannot receive the next data. In this case, the output of the logic gate 118, which is the logical product of the VALID_IN signal and the STOP_IN signal, sets the D-FF 112 to '1', outputs the IN_STOP signal of '1' to the arithmetic unit 300, and simultaneously buffers the selector 114. Set to 110 side. IN_STO
The P signal is generated by the same operation as the above-described logic gate 124.
Change the IN_VALID signal from '1' to '0'. The outputs of the logic gate 118 and the D-FF 112 become the LOAD signal (LD) of the buffer 110 via the logic gate 116. Accordingly, at timing t4, D3 of IN_DATA is read into the buffer 110, and the read data D3 * is transferred to the arithmetic circuit 308 by DATA.
Output as _IN.

At timing t5, the operation unit 30
Since the IN_STOP signal output from 2 is “1”, the IN_DATA output from the arithmetic unit 300 is not updated. Further, since the VALID_IN signal input to the arithmetic circuit 308 and the STOP_IN signal output from the arithmetic circuit 308 remain “1”, the D-FF 112 is continuously set to “1”. Also, the buffer 110 is not updated.

At timing t6, the operation unit 30
Since the IN_STOP signal output from 2 is “1”, the IN_DATA output from the arithmetic unit 300 is not updated. However, since the VALID_IN signal input to the arithmetic circuit 308 remains '1' and the STOP_IN signal output from the arithmetic circuit 308 becomes '0', the buffer 11 connected to DATA_IN
The data D3 * of 0 is read into the arithmetic circuit 308 and processed.
Further, the STOP_IN signal is output to the D-FF 112 via the logic gate 118.
Is reset to '0' and output from the arithmetic unit 302
Set the IN_STOP signal to '0'. Then, since the selector 114 selects the data input side, DATA_IN of the arithmetic circuit 308 is directly connected to IN_DATA of the arithmetic unit 302 again. Furthermore, IN
The _STOP signal changes the IN_VALID signal from '0' to '1' by the same operation as the gate circuit 124 described above.

At timing t7, the VALID_IN signal input to the arithmetic circuit 308 is “1”, and the STOP_IN signal output from the arithmetic circuit 308 and the STOP_OUT signal input to the arithmetic circuit 308 are “0”. , IN_DATA are read into the arithmetic circuit 308 via the selector 114 as valid data and processed. Further, since the IN_STOP signal output from the arithmetic unit 302 is “0”, the arithmetic unit 300
The data output from is updated.

At timing t8, similarly to timing t7, D5 of IN_DATA is processed by the arithmetic circuit 308,
IN_DATA is updated.

At timing t9, the operation unit 30
Since the IN_VALID signal input to 4 is '0', IN_DAT
A means invalid (undefined). IN_DATA is D of the arithmetic circuit 308
Although connected to ATA_IN, the arithmetic circuit 308 does not perform any processing because the data is invalid. Note that, in the present embodiment, IN_DATA is undefined, but as described above, the IN_VALID signal is designed to be '0' when the IN_DATA from the arithmetic unit 300 is not updated with D5. .

At timing t10, the arithmetic unit 302
IN_DATA input to is ignored as in the case of the timing t9. On the other hand, the VALID_OUT signal output from the arithmetic circuit 308 is “1”, and the OUT_STOP signal input to the arithmetic unit 304 is
Since the signal is '0', '1' is output to the OUT_VALID signal. DATA_OUT d1 is an arithmetic unit via OUT_DATA
The data is transferred to 304 and processed as valid data in the arithmetic unit 304.

At timings t11 and t12, similarly to timing t7, IN_
The data D6 and D7 are processed by the arithmetic circuit 308, and the data is updated. Similarly to the timing t10, the arithmetic circuit 3
D2 and d3 of OUT_DATA output from 08 are arithmetic units
Processed at 304, the data is updated. Further, the arithmetic unit 304 cannot receive new data at the timing t13 immediately after receiving d3 of OUT_DATA, and therefore outputs the OUT_STOP signal to the arithmetic unit 302 as '1'.
To This is because at timing t4, the arithmetic unit
This is the same as the process in which the 302 changes the IN_STOP signal output to the arithmetic unit 300 from '0' to '1'. Arithmetic unit 3
The OUT_STOP signal output from 04 changes the OUT_VALID signal from '1' to '0' via the logic gate 124. Further, since the VALID_OUT signal of the arithmetic circuit 308 is “1”, the STOP_OUT signal is changed from “0” to “1” via the logic gate 122 at the next timing t13 so as not to update d4 of DATA_OUT. .

At timing t13, the operation unit 3
The OUT_STOP signal output from 04 is “1”, the VALID_OUT signal output from the arithmetic circuit 308 is “1”, and the IN_VALID signal input from the arithmetic unit 300 is also “1”. This is because at the timing when the subsequent operation unit 304 cannot receive data, the previous operation unit 30
0 and the operation unit 302 is trying to transfer valid data.

Valid DATA_OU output from arithmetic circuit 308
D4 of T is STOP_O as described at timing t12.
Since the UT signal is set to '1', it is not updated at timing t13. Further, similarly to the timing t4, the VALID_IN signal and the STOP_
The OUT signal sets the D-FF 112 to “1” via the logic gate 118, sets the IN_STOP signal output to the arithmetic unit 300 to “1”, and sets the buffer 114
Select 0 side. The IN_STOP signal is
By the same operation as 124, the IN_VALID signal is changed from '1' to '0'. D8 of IN_DATA is buffer 11
0 and the read data D8 * is
To DATA_IN.

At timing t14, the operation unit 3
Since the IN_STOP signal input to 00 is '1', IN_DAT
A is not updated. OUT_ST input to arithmetic unit 304
Since the OP signal remains “1”, the DATA_OUT signal output from the arithmetic circuit 308 is not updated. Similarly to the processing of the IN_STOP signal output to the arithmetic unit 300 at the timing t6, as a result of the processing of the arithmetic unit 304 at the timing t14, the OUT_STOP signal changes from “1” to “0”. Output from the arithmetic unit 100 via the logic gate 124
The OUT_VALID signal is changed to “1”, and the STOP_OUT signal input to the arithmetic circuit 308 via the logic gate 122 is changed to “0”.

At timing t15, the operation unit 3
OUT_VALID signal input to 04 is '1', arithmetic unit 30
Since the OUT_STOP signal output from 4 is “0”, d4 of DATA_OUT output from the arithmetic circuit 308 is processed as valid data in the arithmetic unit 304, and DATA_OUT is updated. Also, IN_STOP input to the arithmetic unit 300
Since the signal is “1”, IN_DATA output from the arithmetic unit 300 is not updated. However, the VALID_IN signal input to the arithmetic circuit 308 is “1”, the STOP_IN signal output from the arithmetic circuit 308, and the STOP_OUT signal input to the arithmetic circuit 308.
Since the signal is “0”, the data D8 * of the buffer 110 connected to DATA_IN is input to the arithmetic circuit 308 and processed. Further, the output of the logic gate 122 resets the D-FF 112 to “0” via the logic gate 118, and outputs
Set the IN_STOP signal output to to '0'. Almost at the same time, the selector 114 is made to select the data input side. Further, the IN_STOP signal changes the IN_VALID signal from '0' to '1'.

At timing t16, at timing t7
Similarly to D9 of IN_DATA output from the arithmetic unit 300
Is processed by the arithmetic circuit 308, and IN_DATA is updated.

At timing t17, the operation unit 3
Although the OUT_STOP signal output from 04 is “1”, there is no problem because neither the arithmetic unit 300 nor the arithmetic unit 302 attempts to transfer valid data.

As described above, the function of the interface circuit 102 is that the operation unit 302 corresponding to the data conversion circuit 100 cannot receive the data, or the operation unit 304 of the subsequent stage cannot receive the data and In the case where the operation unit 300 stops, the data transferred from the preceding operation unit 300 is temporarily stored in a buffer, and the function of stopping the data update of the previous operation unit 300 is performed. Further, as described below, the interface circuit 102 can be used as a template for all arithmetic units (circuit blocks) only by partially changing its configuration.

FIGS. 9 and 10 are block diagrams showing the operations of the interface circuit 102 during compression and expansion, respectively.
The basic configuration is the same as FIG.

At the time of compression, there are two types of data output from the data conversion core 104, and the subsequent block is a JPEG circuit.
80 and the memory control circuit 40b. Therefore, O
The R gate 120 is changed to three inputs to correspond to two types of output data.

At the time of decompression, there are two types of data input to the data conversion core 104, and the preceding block is a JPEG circuit 80.
And the memory control circuit 40d. Therefore, the STOP signal output from the memory control circuit 40c corresponding to the subsequent block is supplied to the OR gates 120a and 120b to correspond to two types of input data.

[Image Recording Processing] The image processing apparatus 1000
When the shooting mode is set on the mode dial 32,
CCD-RAW data of a captured image obtained by the imaging lens 10, the imaging device 12, and the A / D converter 14 is stored in the recording medium 70 after image processing or directly. FIG. 11 is a flowchart illustrating an operation example of the image processing apparatus 1000 regarding the recording processing of a captured image, which is executed by the system control circuit 30.

In FIG. 11, one of the Huffman tables stored in the read-only memory 36 is set in the JPEG circuit 80 (S100). The Huffman table used differs between when the recording mode is JPEG mode and when the CCD-RAW lossless compression mode is used.The Huffman table suitable for the DCT-converted data series or the DPH-converted data series Huffman tables are used.

A plurality of Huffman tables are stored in the read-only memory 36 for each of the two types of data series. These Huffman tables are generated from average histograms obtained from a plurality of pieces of image data each having highly similar features. Therefore, efficient encoding is provided for image data similar to the original image data.

Next, the setting of the recording mode switch 34 is determined (S101). If the recording mode is JPEG mode,
The CCD-RAW data held in 60 is sent to the image processing circuit 50 via the memory control circuit 40 (S102). Image processing circuit 50
Performs image processing on the CCD-RAW data (S103). The image-processed data is sent to the JPEG circuit 80 via the memory control circuit 40.
Are subjected to DCT and quantization (S104).

On the other hand, the setting of the recording mode switch 34 is
In the RAW mode, the CCD-RAW data held in the memory 60 is transferred to the memory control circuit 40 and the interface circuit 102.
Is sent to the data conversion core 104 via the (S110). And C
The data width of the CD-RAW data is determined (S111), and in the case of 12 bits, the dividing / combining circuit 106 performs the dividing / PACK processing (S11).
3) The PACKed data is sent to the memory 60 via the memory control circuit 40 (S114). 10-bit wide CCD-RAW data,
Alternatively, the upper 10 bits of data separated from the 12-bit wide CCD-RAW data are subjected to DPCM conversion by the DPCM conversion circuit 108 (S112).

The data subjected to DCT and quantization or DPCM conversion is Huffman-coded according to a Huffman table set in the Huffman coding / decoding circuit 86 of the JPEG circuit 80 (S105). The Huffman-coded data is sent to the memory 60 via the memory control circuit 40 (S106).

For example, when a code for one image is stored in the memory 60, a Huffman code newly stored in the memory 60 and
The data size with the Huffman code stored in the memory 60 by the previous encoding is compared (S107), and the Huffman code with a small data size is held in the memory 60. Subsequently, it is determined whether or not encoding by all Huffman tables has been completed (S108), and if not completed, the process returns to step 100,
A new Huffman table is set in the JPEG circuit 80, and the encoding is repeated. By repeating this encoding, the one with the smallest data size is selected from among a plurality of Huffman codes obtained by different Huffman tables.

After that, the code stored in the memory 60 is stored as a data file on the recording medium 70 via the memory control circuit 40 (S109). At this time, the Huffman-encoded data and the PACK-packed data are stored as CCD-RAW reversible compressed data together with header data including recording (photographing) conditions. For header data,
This will be described later with reference to FIG.

As described above, in the present embodiment, a plurality of Huffman tables are prepared in advance, and encoding is performed a plurality of times on one data, so that a single Huffman table provided as a standard is provided. Compared to compression using
Effective compression can be performed in terms of the compression ratio.

[Reproduction Mode] When the reproduction mode is set on the mode dial 32, the image processing apparatus 1000 displays the image recorded in the image data file stored in the recording medium 70 on the image display unit 22. FIG. 12 is a flowchart illustrating an operation example of the image processing apparatus 1000 regarding the image reproduction processing, which is executed by the system control circuit 30.

The image data file stored in the recording medium 70 is read into the memory 60 via the memory control circuit 40 (S201), and the header data is analyzed by the system control circuit 30 (S202). The result of analyzing the header data is determined (S203), and if the recording mode is the JPEG mode, the JPEG data held in the memory 60 is sent to the JPEG circuit 80 via the memory control circuit 40 to decode the JPEG data. (S204).
That is, the JPEG data is Huffman-decoded by the Huffman code decoding circuit 86, and is inversely quantized and inverse DCT-processed by the DCT / quantization circuit 82. Thereafter, the decoded image data is stored in the memory 60 via the memory control circuit 40 (S
205). The image data held in the memory 60 is sent to the image display unit 22 via the memory control circuit 40 and the D / A converter 20, and the image is displayed (S206).

If the result of analyzing the header data is a CCD-RAW mode, the Huffman-encoded data held in the memory 60 is sent to the JPEG circuit 80 via the memory control circuit 40, and the Huffman encoding / decoding circuit is 86 Huffman decoding (S
207), the Huffman-decoded data is subjected to inverse DPCM conversion by the DPCM conversion circuit 108 (S208).

Then, the analysis result of the header data is determined (S209). If the CCD-RAW data is 10 bits, the inverse DPCM
The 10-bit CCD-RAW data obtained by the conversion is passed through the interface circuit 102 and the memory control circuit 40,
It is stored in the memory 60 (S211). Also, CCD-RAW data is 1
In the case of 2 bits, the PACK data held in the memory 60 is sent to the data conversion core 104 via the memory control circuit 40 and the interface circuit 102, and the division / combination circuit 106
To UNPACK processing and the lower order obtained by UNPACK processing
2-bit data and top 10 obtained by inverse DPCM conversion
A combining process with bit data is performed (S210). The restored 12-bit CCD-RAW data is transferred to the interface circuit 1
02 and stored in the memory 60 via the memory control circuit 40 (S211).

The CCD-RAW data stored in the memory 60 is
The image is sent to the image processing circuit 50 via the memory control circuit 40 and subjected to image processing (S212). RG obtained by image processing
The B image data is stored in the memory 60 via the image processing circuit 40 (S205). The image data held in the memory 60 is
The image is sent to the image display unit 22 via the memory control circuit 40 and the D / A converter 20, and the image is displayed (S206).

Data Format FIG. 13 is a diagram showing a basic format example of CCD-RAW reversible compressed data recorded on the recording medium 70.

At the beginning of the basic format shown in FIG. 13, header data is recorded. The first bit of the header data indicates the recording mode MODE, and if it is '0', the 10-bit C
CD-RAW data, "1" indicates 12-bit CCD-RAW data. In the subsequent 15 bits, a 12-bit numerical value SIZE_H representing the number of pixels of the image sensor 12 in the horizontal direction is recorded in a bottom-justified manner. In the subsequent 16 bits, a 12-bit numerical value SIZE_V indicating the number of pixels in the vertical direction of the image sensor 12 is recorded in a bottom-justified manner. Subsequently, PACK data having a data size calculated from the following equation is recorded, and Huffman codes are recorded following the PACK data. Data size = MODE × SIZE_H × SIZE_V / (8 × 8) [b
ytes]

Whether the data file is a CCD-RAW reversible compressed data file or a JPEG file is determined by the first 4
It can be determined by bits. "FFD8" for JPEG files
The first 4 bits are '111
1 '. On the other hand, '00 for CCD-RAW lossless compressed data
00 'or' 1000 '.

As described above, according to the present embodiment, a CCD-RAW reversible compression / decompression circuit for 10- or 12-bit CCD-RAW data is formed using an existing baseline JPEG encoding / decoding circuit. Can be realized. In other words, the JPEG recording mode or the
CCD-RAW reversible compression recording mode can be selected.
Therefore, when it is desired to prevent data loss (image quality deterioration) due to quantization when performing JPEG encoding, CCD-RAW data can be losslessly compressed and stored on a recording medium. In addition, compressed CCD-RAW data (especially 12-bit CCD-R
AW data) can have a sufficiently small data size as compared to the case where data is stored in the CCD-RAW format.

Also, in other words, the existing baseline
Part of the JPEG encoding / decoding circuit can be used for CCD-RAW reversible compression / decompression processing, reducing the load on the development of equipment that requires such a circuit and reducing the circuit size. Such a device can be realized.

Furthermore, in the present embodiment, a plurality of Huffman tables are prepared in advance, and encoding is performed on one piece of data a plurality of times, so that compression by a single standard Huffman table is provided. More effective compression can be performed in terms of compression ratio.

Since the selection and supply of the Huffman table is selectively performed by the system control unit 30, the Huffman table can be easily realized without changing the image compression / decompression unit. Furthermore, since it is not necessary to generate a Huffman table for each data to be compressed, the load of software development for generating the Huffman table can be reduced.

In the above-described embodiment, an image processing apparatus including an image sensor such as an electronic camera (digital camera) has been described. However, similar processing can be performed by a computer or an image output apparatus. .

[0112]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

Further, an object of the present invention is to supply a storage medium (or a recording medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus, and a computer (a computer) of the system or the apparatus. It is needless to say that the present invention can also be achieved by a CPU or an MPU) reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. Also,
When the computer executes the readout program code, not only the functions of the above-described embodiments are realized, but also the operating system (OS) running on the computer based on the instructions of the program code.
It goes without saying that a case where the functions of the above-described embodiments are implemented by performing some or all of the actual processing, and the processing performs the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. Needless to say, the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium described above, the storage medium may include the storage medium described above (FIG. 11 and / or FIG. 1).
2) (shown in FIG. 2).

Further, the application of the present invention is not limited to an image processing apparatus such as a digital camera and its recording medium. For example, image data of an image captured by an image processing device such as a digital camera
Image data used for normal use such as display, print, search, etc.
EG encoding and recording on a CD-ROM, etc., and image data that requires arbitrary image processing such as color separation for printing and CG creation are recorded on a CD-ROM or the like in CCD-RAW format. The method for compressing and expanding image data according to the invention can be used. Further, a medium on which image data is recorded (stored) in such a form is also included in the present invention.

[0117]

As described above, according to the present invention,
It is possible to provide an image processing device and method for realizing effective encoding, and a data processing device and control method therefor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an image processing apparatus according to an embodiment of the present invention;

FIG. 2 is a diagram showing a data format in division and PACK processing, and UNPACK and synthesis processing;

FIG. 3 is a diagram illustrating an example of a color filter array.

FIG. 4 is a block diagram showing a detailed configuration example of a data conversion core shown in FIG. 1;

FIG. 5 is a diagram showing an example of a data format of CCD-RAW data.

FIG. 6 is a timing chart showing a specific example of a waiting process;

FIG. 7 is a block diagram showing a most basic configuration example of the interface circuit shown in FIG. 1;

FIG. 8A is a timing chart showing a relationship between data, a VALID signal, and a STOP signal in detail;

FIG. 8B is a timing chart showing the relationship between data, a VALID signal, and a STOP signal in detail;

FIG. 9 is a block diagram showing a compression operation of the interface circuit;

FIG. 10 is a block diagram showing a decompression operation of the interface circuit;

FIG. 11 is a flowchart illustrating an operation example of the image processing apparatus regarding recording processing of a captured image;

FIG. 12 is a flowchart illustrating an operation example of an image processing apparatus regarding image reproduction processing;

FIG. 13 is a diagram illustrating an example of a basic format of CCD-RAW reversible compressed data recorded on a recording medium.

Claims (13)

[Claims] 1. A memory in which a plurality of different Huffman tables are stored; an encoding unit for Huffman encoding input data; and the plurality of different Huffman tables are sequentially set in the encoding unit. A control unit for selecting a code having the smallest data size from the corresponding coding results. 2. A method for controlling a data processing device, comprising: a memory storing a plurality of different Huffman tables; and an encoding unit for Huffman encoding input data, wherein the encoding unit includes the plurality of different Huffman tables. A control method comprising: setting a table in order; and selecting a code having the smallest data size from encoding results corresponding to the respective Huffman tables. 3. An image processing apparatus comprising: compression means for compressing image data; and memory control means for storing the compressed image data on a recording medium, wherein the compression means includes at least a plurality of different Huffman tables. A stored memory, an encoding unit that performs Huffman encoding of the imaging data, and the plurality of different Huffman tables are sequentially set in the encoding unit, and the largest data size among encoding results corresponding to each of the Huffman tables is set. An encoding control unit for selecting a code having a small size and supplying the selected code to the memory control unit. 4. The image processing apparatus according to claim 3, wherein the encoding unit performs Huffman encoding after predictive encoding or orthogonal transformation and quantization of the image data. 5. When predictive encoding of the image data is performed,
The encoding unit separates the imaging data into upper bits and lower bits, predictively encodes the separated upper bits of imaging data, and packs the separated lower bits of imaging data into predetermined imaging data units. 5. The image processing device according to claim 4, wherein: 6. The image processing apparatus according to claim 4, wherein, when orthogonally transforming and quantizing the image data, the encoding unit performs image processing on the image data in advance. 7. The image processing apparatus according to claim 5, wherein the imaging data is multi-valued data according to an element array of an imaging element. 8. The image processing apparatus according to claim 7, wherein the image sensor is a CCD having a predetermined element array. 9. The image processing device according to claim 3, further comprising the image pickup device. 10. An image processing method for compressing image data and storing the compressed image data on a recording medium, wherein the compression process includes at least using a plurality of different Huffman tables in order to convert the image data into Huffman data. An image processing method, comprising: encoding, selecting a code having the smallest data size from encoding results corresponding to respective Huffman tables, and storing the selected code in the recording medium. 11. The image processing method according to claim 10, wherein the imaging data is subjected to Huffman coding after being subjected to predictive coding or orthogonal transform and quantization. 12. A storage medium storing a memory storing a plurality of different Huffman tables and a program code for controlling a data processing apparatus having an encoding unit for performing Huffman encoding of input data, wherein the program code comprises: The code includes at least a code of a step of sequentially setting the plurality of different Huffman tables in the encoding unit, and a code of a step of selecting a code having the smallest data size among encoding results corresponding to the respective Huffman tables. A recording medium comprising: 13. A recording medium on which a program code for image processing for compressing image data and storing the compressed image data on a recording medium is recorded, wherein the program code includes at least a plurality of different Huffman tables in order. A code of a step of performing Huffman encoding of the imaging data using a code of a step of selecting a code having the smallest data size among encoding results corresponding to the respective Huffman tables; and a step of storing the code in the recording medium. A recording medium characterized by having a code.