JP2001060985A - Transmitter, receiver and communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the reduction of power consumption and the suppression of unnecessary radiation in communication equipment by controlling the frequency of a clock in accordance of a communication speed. SOLUTION: A clock selection and signal generation circuit 20 outputs a clock selection signal clksel and a clock stopping signal clkstp in accordance with the data accumulation quantity of a transmission/reception buffer 40, and a clock generation circuit 10 controls the frequency of a clock signal clk in accordance with clksel and stops the supply of the clock signal in accordance with clkstp. A signal processing circuit 30 successively writes transmission data corresponding to transmission information from a host to a transmission buffer at the time of answering and reads received data from a reception buffer at the time of reception to reproduce received information. A front end 50 successively reads transmission data from the transmission buffer at the time of transmission to output the data to a transmission line and receives data from a communication line at the time of reception to successively write them in the reception buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus including a transmission / reception apparatus, and more particularly to a communication apparatus including a transmission / reception apparatus, which controls the frequency of a clock signal used for signal processing at the time of transmission / reception according to the status of transmission / reception data, thereby reducing power consumption and unnecessary radiation. The present invention relates to a communication device capable of suppressing the communication.

[0002]

2. Description of the Related Art In a communication apparatus, the actual communication speed changes according to the quality of a communication path, the communication processing capacity of a communication partner, and the like. For example, when the quality of a communication channel is high, the frequency of a clock signal used for data transmission / reception can be set high, and high-speed communication can be realized. In addition, when the communication partner has a high communication processing capability, the transmission side can set the data transmission speed accordingly, and high-speed communication can be realized within the allowable range of the communication path.

[0003]

By the way, the conventional communication device always operates at a constant clock frequency irrespective of the quality of the communication path and the communication processing capability of the communication partner. That is, even if the communication speed changes according to the quality of the communication path or the capability of the communication partner, the frequency of the clock signal used in the communication device is substantially constant. For this reason, when performing slow communication, an unnecessarily high-speed clock signal is supplied to the communication device, and as a result, unnecessarily large power is consumed and unnecessary electromagnetic radiation is generated.

The present invention has been made in view of the above circumstances, and an object of the present invention is to control the frequency of a clock signal used in accordance with an actual communication speed so that a transmitting / receiving circuit can optimize an optimum clock frequency. It is an object of the present invention to provide a communication device which can be operated with a communication device and can realize reduction of power consumption and suppression of unnecessary electromagnetic radiation.

[0005]

In order to achieve the above object, a transmitting apparatus of the present invention is a transmitting apparatus for transmitting data at a predetermined communication speed, comprising: a transmitting buffer for storing transmitting data; Received clock signal,
A signal processing circuit that operates at a speed corresponding to the frequency of the clock signal and sequentially writes information data to be transmitted as a transmission data sequence into the transmission buffer; And an interface circuit for sequentially reading and transmitting the transmission data from the transmission buffer, and controlling a frequency of a clock signal to be generated in accordance with an amount of data stored in the transmission buffer, and transmitting the clock signal to the signal processing circuit. And a clock supply circuit that supplies the clock signal to the interface circuit and stops the supply of the clock signal when there is no transmission data for a predetermined time.

A receiving apparatus according to the present invention is a receiving apparatus for receiving data transmitted at a predetermined communication speed, and receives a reception buffer for storing received data, and receives a frequency-controlled clock signal to receive the data. A signal processing circuit that operates at a speed corresponding to the frequency of the clock signal, sequentially reads the received data from the reception buffer, and reproduces information data corresponding to the received data; An interface circuit that operates at a speed according to and receives received data and sequentially writes the received data into the reception buffer, and controls the frequency of a clock signal to be generated in accordance with the amount of data stored in the reception buffer, and controls the clock signal to The signal is supplied to the signal processing circuit and the interface circuit. And a clock supply circuit for stopping the supply of the clock signal.

A communication device according to the present invention is a communication device for transmitting and receiving data at a predetermined communication speed. The communication device has a transmission buffer for storing transmission data, a reception buffer for storing reception data, and a frequency-controlled transmission buffer. Receiving a clock signal, operating at a speed corresponding to the frequency of the clock signal,
A signal processing circuit for sequentially writing information data to be transmitted as a transmission data sequence to the transmission buffer, sequentially reading reception data from the reception buffer, and reproducing information data corresponding to the reception data, and a frequency-controlled clock signal. Receiving, operating at a speed according to the frequency of the clock signal, sequentially transmitting and transmitting the transmission data from the transmission buffer at the time of transmission, receiving the reception data at the time of reception, and sequentially writing to the reception buffer, The frequency of the generated clock signal is controlled and supplied to the signal processing circuit and the interface circuit according to the amount of data stored in the transmission buffer and the reception buffer, and the transmission data and the reception data do not exist in a predetermined time. Clock supply to stop the supply of the clock signal And a circuit.

In the present invention, preferably, the transmission buffer and the reception buffer are constituted by FIFO. The clock supply circuit includes: a clock selection signal generation circuit that generates a clock selection signal according to the amount of data stored in the transmission buffer or the reception buffer; and a clock that generates a clock signal having a frequency corresponding to the clock selection signal. And a generation circuit.

In the present invention, preferably, a first write counter for counting the amount of data written to the transmission buffer, and a first read counter for counting the amount of data read from the transmission buffer are provided. And the clock selection signal generation circuit generates the clock selection signal according to the count value of the first write counter and the count value of the first read counter. More specifically, for example, the clock selection signal generation circuit calculates the data accumulation amount of the transmission buffer according to the difference between the count value of the first write counter and the count value of the first read counter. The clock selection signal is generated according to the data storage amount.

In the present invention, preferably, a second write counter for counting the amount of data written to the reception buffer, and a second read counter for counting the amount of data read from the reception buffer are provided. And the clock selection signal generation circuit generates the clock selection signal according to the count value of the second write counter and the count value of the second read counter. More specifically, for example, the clock selection signal generation circuit calculates the data accumulation amount of the reception buffer according to the difference between the count value of the second write counter and the count value of the second read counter. The clock selection signal is generated according to the data storage amount.

Further, in the present invention, preferably, the clock selection signal generation circuit outputs a clock stop signal to the clock generation circuit when there is no transmission data and no reception data in a predetermined time. The clock generation circuit stops supplying the clock signal when receiving the clock stop signal from the clock selection signal generation circuit.

According to the present invention, the operation speed of each of the signal processing circuit and the interface circuit is controlled in accordance with the clock signal supplied from the clock supply circuit.
In the signal processing circuit, transmission data according to the transmission information is generated at the time of transmission, is sequentially written to the transmission buffer, and at the time of reception, the reception data is sequentially read from the reception buffer,
The received information is reproduced accordingly. The transmission circuit sequentially reads out the transmission data from the transmission buffer at the time of transmission and outputs the data to the communication path, and receives the reception data from the communication path at the time of reception and writes the data in the reception buffer. The frequency of the clock signal supplied by the clock signal supply circuit is controlled according to the amount of transmission data or reception data stored in the transmission buffer or the reception buffer. It is controlled to operate at the optimum operating speed, and furthermore, it is controlled so that the supply of the clock signal is stopped when data is not transmitted or received, so that power consumption is reduced and unnecessary electromagnetic radiation is prevented. It is feasible.

[0013]

FIG. 1 is a diagram showing an embodiment of a communication device according to the present invention, and is a block diagram showing an entire configuration of the communication device. As illustrated, the communication device of the present invention includes a clock generation circuit 10, a clock selection signal generation circuit 20, a signal processing circuit 30, a transmission / reception buffer 40, and a front end 50.

The clock generation circuit 10 generates a clock signal clk having a frequency corresponding to the clock selection signal clksel from the clock selection signal generation circuit 20, and supplies the clock signal clk to the signal processing circuit 30 and the front end 50, respectively. The clock generation circuit 10 generates, for example, a basic clock having a predetermined frequency, divides the basic clock by a predetermined frequency division ratio, and generates a plurality of clock signals whose frequency is reduced by a power of 2; One of the plurality of clock signals is appropriately selected according to the clock selection signal clksel, and the selected one is output to the signal processing circuit 30 and the front end 50 as the clock signal clk. in this case,
The clock generation circuit 10 can be configured by an oscillation circuit, a frequency division circuit, and a selection circuit.

Further, the clock generation circuit 10 includes, for example,
By using an oscillation circuit whose frequency is continuously variable according to the frequency control signal and generating the frequency control signal in accordance with the clock selection signal clksel from the clock selection signal generation circuit 20, the oscillation frequency of the oscillation circuit Can be controlled to a predetermined value. In this case, the clock generation circuit 10 can be configured by, for example, a PLL circuit. In addition, the clock generation circuit 1 thus configured
With 0, the frequency of the clock signal clk can be continuously controlled, and the processing speed of the signal processing circuit 30 and the front end 50 can be finely controlled.

The clock selection signal generation circuit 20 obtains the amount of transmission or reception data stored in the transmission / reception buffer 40 according to the read address rp and the write address wp from the transmission / reception buffer 40, and determines the amount of data stored in the transmission / reception buffer 40 according to the data storage amount. Generates a clock selection signal clksel for controlling the frequency of the clock signal clk,
Output to 0. In addition, when it is determined that data transmission / reception is not performed during a predetermined determination time, the clock generation circuit 10 outputs a clock stop signal clkstp to stop the supply of the clock signal. Clock generation circuit 1
0 receives the clock stop signal clkstp,
The output of the clock signal clk is stopped.

The signal processing circuit 30 includes a clock generation circuit 1
It operates according to the clock signal clk from 0. That is,
The signal processing speed of the signal processing circuit 30 is controlled by the frequency of the supplied clock signal clk. The processing speed of the signal processing circuit 30 increases as the frequency of the clock signal clk increases, and conversely, the processing speed of the signal processing circuit 30 decreases as the frequency of the clock signal clk decreases. At the time of transmission, for example, the signal processing circuit 30 receives transmission information from the host system, generates a transmission data sequence by predetermined signal processing according to the transmission information, and sequentially writes the transmission data sequence to the transmission buffer. In addition, as signal processing performed at the time of transmission,
For example, quantization and coding of transmission information are included.

At the time of reception, the signal processing circuit 30 reads out reception data from the reception buffer, performs predetermined signal processing on the reception data, and generates reception information.
Output to host system. Note that the signal processing performed at the time of reception includes, for example, decoding processing, error correction processing, and the like. When there are a plurality of host systems and these host systems simultaneously communicate, the signal processing circuit 30 performs multiplexing processing of transmission data at the time of transmission and separates multiplexed reception data at the time of reception. Separation processing is performed. The multiplexing process and the demultiplexing process can be performed by the front end 50, for example. In FIG. 1, transmission data and reception data are generally referred to as communication data for convenience. Also, the host system is simply abbreviated as host.

The transmission / reception buffer 40 includes, for example, a FIFO
(First-in, first-out) buffer memory, and the FIFO is characterized in that data is written and read out sequentially, and data is read out in the order of writing. The transmission / reception buffer 40 includes a transmission buffer and a reception buffer. At the time of transmission, transmission data from the signal processing circuit 30 is sequentially written into the transmission buffer and accumulated in the transmission buffer. On the other hand, the data stored in the transmission buffer is sequentially read out to the front end 50. Since the reading speed of the front end 50 is determined by the communication speed, if the processing speed of the signal processing circuit 30 is reduced with respect to a certain communication speed, the amount of data stored in the transmission buffer is reduced. When the processing speed is increased, the amount of data stored in the transmission buffer increases. The write address wp is updated according to the write by the signal processing circuit 30, and
The read address rp is updated in accordance with the read by the front end 50. Therefore, the data storage amount of the transmission buffer can be calculated according to the write address wp and the read address rp.

At the time of reception, the transmission data of the other party is sequentially received from the communication path by the front end 50 and stored in the reception buffer. On the other hand, the data stored in the reception buffer is sequentially read by the signal processing circuit 30. Since the writing speed of the received data by the front end 50 is determined by the communication speed, for a certain communication speed,
Decreasing the processing speed of the signal processing circuit 30 increases the amount of data stored in the reception buffer. Conversely, increasing the processing speed of the signal processing circuit 30 can reduce the amount of data stored in the reception buffer. The write address wp is updated according to the writing by the front end 50, and the read address rp is updated according to the reading by the signal processing circuit 30. Therefore, the amount of data stored in the reception buffer can be calculated according to the write address wp and the read address rp.

The front end 50 includes a transmission / reception buffer 4
This is an interface circuit provided between the communication channel 0 and the communication path. The front end 50, as described above, receives the clock signal cl supplied by the clock generation circuit 10.
k. That is, the processing speed of the front end 50 is controlled by the frequency of the clock signal clk. When the frequency of the clock signal clk is high, the processing speed of the front end 50 increases, and conversely, when the frequency of the clock signal clk is low, the processing speed of the front end 50 decreases. At the time of transmission, the front end 50 reads out the transmission data stored in the transmission buffer in the transmission / reception buffer 40 and outputs it to the communication path. At the time of reception, the front end 50 receives the transmission data of the other party from the communication path, Write to buffer.

In a communication device using a transmission / reception buffer, the communication speed of the communication device can be known from the amount of untransmitted data stored in the transmission buffer during transmission. Also, the communication speed of the communication device can be similarly determined from the amount of unprocessed data stored in the reception buffer at the time of reception. By utilizing this principle, the frequency of the clock signal clk supplied to the signal processing circuit 30 and the front end 50 in the communication device can be appropriately controlled.

In the communication device according to the present embodiment, the clock selection signal generation circuit 20 calculates the amount of data stored in the transmission / reception buffer according to the write address wp and the read address rp from the transmission / reception buffer 40, and in response to this, Clock selection signal clk for controlling frequency
sel is generated and supplied to the clock generation circuit 10. The clock generation circuit 10 outputs the clock selection signal clksel
, The frequency of the generated clock signal clk is controlled. With this control, when the amount of data accumulated in the transmission / reception buffer increases, the frequency of the clock signal clk supplied by the clock generation circuit 10 is controlled to be high,
Accordingly, the signal processing circuit 30 and the front end 50
Processing speed is improved. Conversely, when the amount of data stored in the transmission / reception buffer decreases, the frequency of the clock signal clk supplied by the clock generation circuit 10 is controlled to be low, and the processing speed of the signal processing circuit 30 and the front end 50 decreases accordingly. . That is, when the amount of transmitted / received data is reduced, the signal processing circuit 30 and the front end 5
By reducing the processing speed of 0, power consumption is reduced and unnecessary radiation from these circuits is reduced.

Further, when data transmission / reception is not actually performed or when the transmission speed is extremely low, the amount of data stored in the transmission / reception buffer is reduced. Under the control of the clock selection signal generation circuit 20, the supply of the clock signal clk is stopped when the amount of data accumulated in the transmission / reception buffer does not satisfy a certain reference value during a certain determination time. Accordingly, the signal processing circuit 30 and the front end 50 are both held in a stopped state, whereby the power consumption of these circuits is suppressed to a low level, and the effect of suppressing unnecessary electromagnetic radiation by stopping the operation is obtained.

After the supply of the clock signal clk is stopped, the clock selection signal generation circuit 20 continuously monitors the amount of data stored in the transmission / reception buffer 40, and when the amount of data stored exceeds a predetermined reference value, Is output to the clock generation circuit 10 to restart the supply of the clock signal clk.

Hereinafter, the operations at the time of transmission and at the time of reception in the communication apparatus of the present embodiment will be described in detail with reference to FIGS. FIG. 2 is a block diagram showing the configuration of a partial circuit including a transmission buffer 41, a read (read) address counter 43, a write (write) address counter 44, a clock selection signal generation circuit 20, and a timer circuit 42 in the transmission / reception buffer 40. is there. This partial circuit shown in FIG. 2 relates to the transmission operation in the communication device of the present embodiment.

The transmission data sd0 from the signal processing circuit 30 shown in FIG.
On the other hand, the data stored in the transmission buffer 41 is sequentially read to the front end 50, and the read transmission data sd1 is output to the communication path via the front end 50.

The timer circuit 42 is provided for setting a predetermined time. As shown in FIG. 2, the timer circuit 42 sets a predetermined time according to the instruction signal from the clock selection signal generation circuit 20, and starts counting the time. Then, when the set time has elapsed, a signal indicating the lapse of time is output to the clock selection signal generation circuit 20. The clock selection signal generation circuit 20 includes a timer circuit 4
2, a predetermined time is set, and during that time, the state of the transmission buffer is monitored, whereby the clock selection signal clk
sel or the clock stop signal clkstp is generated as appropriate.

The read address counter 43 stores the transmission data s stored in the transmission buffer 41 by the front end 50.
A read address rp for reading d1 is generated. Here, assuming that reading of the transmission data sd1 is performed in any of a bit unit, a byte unit, and a wide unit, the read address rp increases by one each time one unit of transmission data is read out to the front end 50. The write address counter 44 includes the signal processing circuit 30
Generates a write address wp for writing the transmission data sd0 to the transmission buffer 41. For example, when data is written in byte units, the write address wp increases by one each time one byte of transmission data is written to the transmission buffer 41.

The clock selection signal generation circuit 20 transmits a transmission request signal send_req from the host system, a read address rp from the read address counter 43, and a write address w from the write address counter 44.
A clock selection signal clksel and a clock stop signal clkstp for controlling the frequency of the clock are generated in accordance with p, and output to the clock generation circuit 10 shown in FIG.

The clock selection signal generation circuit 20 starts generating the clock selection signal clksel in response to the transmission request signal send_req from the host system. In this case, the clock selection signal generation circuit 20 calculates the amount of untransmitted data stored in the transmission buffer 41 according to the write address wp and the read address rp. For example, assuming that both the write address wp and the read address rp are reset to 0 by the reset operation at the start of transmission, the write address wp and the read address rp are set every time writing to the transmission buffer 41 and reading from the transmission buffer 41 are started. Since the read address is incremented by one, the amount ΔD _{s of} untransmitted data in the transmission buffer 41 at an arbitrary time is obtained by the following equation.

[0032]

ΔD _s = wp−rp (1)

The clock selection signal generation circuit 20, depending on the amount [Delta] D _s unsent data calculated in accordance with equation (1), and generates a clock selection signal CLKSEL. Also,
When the amount of untransmitted data ΔD _s is maintained at or below a predetermined reference value D _{ref at} a predetermined time T _S , a clock stop signal clkstp for stopping the supply of the clock signal is generated, and the clock generation circuit 10 Output to Note that the reference value _Dref can be set to 0, for example.

FIG. 3 is a state transition diagram showing an operation state of the clock selection signal generation circuit 20 at the time of transmission. As shown in the figure, there are three operation states at the time of transmission, that is, a transmission standby state SST1, a transmission start state SST2, and a transmission stop state (suspend state) SST0. The clock selection signal generation circuit 20 is held in any one of these states according to the amount ΔD _{s of} untransmitted data accumulated in the transmission buffer 41. As an initial state, the clock selection signal generation circuit 20 is held in the transmission standby state SST1. In this state, the clock selection signal generation circuit 20 generates the clock selection signal clksel so as to output the lowest frequency clock to the clock generation circuit 10,
Output to the clock generation circuit 10. Then, the write address wp and the read address rp are (wp = rp)
Is satisfied, that is, the amount of untransmitted data ΔD _s is 0
, The clock selection signal is continuously output.

In the transmission standby state SST1, when the clock selection signal generation circuit 20 detects (wp> rp), that is, when untransmitted data is detected in the transmission buffer 41, the state transits to the transmission start state SST2. In the transmission start state SST2, the clock selection signal generation circuit 20 generates the clock selection signal c according to the write address wp and the read rp.
It controls generation of lksel and state transition. For example,
When (wp> rp), the clock selection signal generation circuit 20
Calculates the untransmitted data amount ΔD _s according to equation (1),
In response to this, the clock selection signal clksel is appropriately generated. On the other hand, when the (wp = rp) state of the lasted time T _s2 or more, state transition to transmit standby state SST1.

In the transmission start state SST2, the clock selection signal generation circuit 20 calculates the untransmitted data amount ΔD _s according to the equation (1), and accordingly, the clock selection signal c.
lksel is generated appropriately. For example, if the write address, read address, and clock frequency at time t are wp (t), rp (t), and fck (t), respectively, the unprocessed data amount ΔD of the reception buffer 45 at two different times t1 and t2. _s (t1), ΔD
_s (t2) is calculated according to the following equations.

[0037]

(Equation 2)

The clock selection signal generation circuit 20 generates ΔD _s
If (t1)> ΔD _s (t2), fck (t1) <f
clock selection signal clkse so as to satisfy ck (t2)
Generate l.

The clock selection signal generation circuit 20, when the transmission standby state SST1 lasted time T _s1 above, a transition to the suspend state SST0. After transitioning to the suspend state SST0, first, the clock selection signal generation circuit 20 outputs the clock stop signal clkstp to the clock generation circuit 10. In response, the clock generation circuit 10 stops supplying the clock signal clk.
And the operation of the front end 50 is stopped.

In the suspend state SST0, the clock selection signal generation circuit 20 keeps monitoring the state of the transmission buffer 41, and when there is no untransmitted data in the transmission buffer 41, that is, when (wp = rp), the suspend state SS
It is held at T0. When untransmitted data is detected in the transmission buffer 41, that is, when (wp> rp), the state transits to the transmission standby state SST1.

[0041] As described above, the clock selection signal generation circuit 20, the state of the transmission buffer 41, corresponding to the amount [Delta] D _s unsent data stored in the transmission buffer 41 specifically, transmission standby state SST1, start transmission It is held in either the state SST2 or the suspend state SST0. In each state, the clock selection signal generation circuit 20 appropriately generates the clock selection signal clksel or the clock stop signal clkstp according to the data amount ΔD _s of the transmission buffer and supplies the clock selection signal clkstp to the clock generation circuit 10 to optimize the transmission data. When the signal can be output to the communication path at a high speed and there is no transmission data, the operation of the signal processing circuit 30 and the front end 50 is stopped, so that unnecessary power consumption and unnecessary radiation can be prevented.

FIG. 4 is a flowchart showing a flow of an operation at the time of transmission in the communication apparatus of the present invention. Hereinafter, FIG.
The transmission operation will be described with reference to FIG. The transmission operation includes, for example, a transmission request signal sen from the host system.
Starts receiving d_req. First, the clock selection signal clks for selecting the default clock signal clk0 having a predetermined frequency by the clock selection signal generation circuit 20.
The clock signal clk0 is supplied to the signal processing circuit 30 and the front end 50, respectively. The front end 50 establishes a connection with the receiving side via the communication path at the clock (step SS1).

Next, the clock selection signal generation circuit 20
The transmission is kept in a standby state (step SS2). In this state, the presence or absence of untransmitted data is detected in the transmission buffer 41, and transmission is started according to the detection result (step SS3).

After starting transmission, the clock selection signal generation circuit 2
0 detects the status (state) of the transmission buffer 41 (step SS4), and generates a clock selection signal clksel for selecting an optimal clock signal according to the amount ΔD _{s of} untransmitted data accumulated in the transmission buffer 41 (step SS4). Step SS5).

Then, the clock generation circuit 10 generates an optimum clock signal clk by selecting it with the clock selection signal clksel, and supplies it to the signal processing circuit 30 and the front end 50, respectively. The front end 50
A connection with the receiving side is established with the supplied clock signal clk, transmission data is read from the transmission buffer 41, and transmitted to the receiving side via a communication path (step SS).
6).

Then, the clock selection signal generation circuit 20
Is, for example, a transmission request signal sen from the host system.
d_req and amount Δ of untransmitted data in the transmission buffer 41
Depending on the D _s, it is determined whether the transmission is completed (step S
S7). If transmission is to be continued, the process returns to step SS4.
As described above, in the communication device of the present embodiment, until the transmission data stored in the transmission buffer 41 becomes 0, the optimum clock signal is selected in accordance with the amount ΔD _s of the stored transmission data, and the selected clock signal is A series of operations for establishing a connection with the reception side, reading transmission data from the transmission buffer 41 and transmitting the data to the reception side are repeatedly performed.

Next, the operation at the time of reception in the communication apparatus of the present embodiment will be described with reference to FIGS.

FIG. 5 shows a reception buffer 45, a write address counter 46, a read address counter 47, and a clock selection signal generation circuit 20 in the transmission / reception buffer 40.
FIG. 3 is a block diagram showing a configuration of a partial circuit including a timer circuit 42. This partial circuit shown in FIG. 5 relates to the receiving operation of the communication device of the present embodiment.

The reception data rd1 from the front end 50 shown in FIG. On the other hand, the data accumulated in the reception buffer 45 is sequentially read out to the signal processing circuit 30, the read reception data rd0 is processed by the signal processing circuit 30, and the information data transmitted by the transmission partner is reproduced. Output to the host system.

The timer circuit 42 sets a predetermined time according to the instruction signal from the clock selection signal generation circuit 20, and starts counting the time. Then, when the set time has elapsed, a signal indicating the lapse of time is output to the clock selection signal generation circuit 20. Clock selection signal generation circuit 20
Sets a predetermined time using a timer circuit 42, and monitors the state of the transmission buffer during that time, whereby the clock selection signal clksel or the clock stop signal cl
kstp is generated appropriately.

The write address counter 46 generates a write address wp when the front end 50 writes the reception data sd1 in the reception buffer 45. For example, when writing data is performed in byte units,
Each time one byte of received data is written to the reception buffer 45, the write address wp increases by one. The read address counter 47 generates a read address rp when the signal processing circuit 30 reads the received data rd0 accumulated from the reception buffer 45. For example, when reading of received data is performed in byte units, the read address rp increases by one each time one byte of received data is read by the signal processing circuit 30.

The clock selection signal generation circuit 20 calculates the write address wp from the write address counter 46 and the read address r from the read address counter 47.
A clock selection signal clksel and a clock stop signal clkstp for controlling the frequency of the clock are generated in accordance with p, and output to the clock generation circuit 10 shown in FIG.

The clock selection signal generation circuit 20 calculates the amount of unprocessed data stored in the reception buffer 45 according to the write address wp and the read address rp. For example, if the write address wp and the read address rp are both reset to 0 by the reset operation at the start of reception, the reception buffer 4
Since the write address wp and the read address are incremented by one each time data is written to the read buffer 5 and read from the receive buffer 45, the amount ΔD _{r of} unprocessed data in the receive buffer 45 at an arbitrary time can be obtained by the following equation.

[0054]

ΔD _r = wp−rp (3)

The clock selection signal generation circuit 20 generates the clock selection signal clksel according to the unprocessed data amount ΔD _r calculated according to the equation (2). Also,
If the amount of unprocessed data ΔD _r is held at or below a predetermined reference value D _{ref at} a predetermined time _Tr , a clock stop signal clkstp for stopping the supply of the clock signal is generated, and the clock generation circuit 10 Output to Note that the reference value _Dref can be set to 0, for example.

FIG. 6 is a state transition diagram showing an operation state of clock selection signal generation circuit 20 at the time of reception. As shown, there are three operating states at the time of reception, that is, a reception standby state RST1, a reception start state RST2, and a reception stop state (suspend state) RST0. The clock selection signal generation circuit 20 is held in one of these states according to the amount ΔD _{r of the} unprocessed data accumulated in the reception buffer 45. As an initial state, the clock selection signal generation circuit 20 is held in the reception standby state RST1. In this state, the clock selection signal generation circuit 20 generates the clock selection signal clksel so as to output the lowest frequency clock to the clock generation circuit 10,
Output to the clock generation circuit 10. Then, the write address wp and the read address rp are (wp = rp)
While the amount of unprocessed data ΔD _r is zero.
, The clock selection signal is continuously output.

In the reception standby state RST1, when the clock selection signal generation circuit 20 detects (wp> rp), that is, when unprocessed data is detected in the reception buffer 45, the state transitions to the reception start state RST2. In the reception start state RST2, the clock selection signal generation circuit 20 generates the clock selection signal c according to the write address wp and the read rp.
It controls generation of lksel and state transition. For example,
When (wp> rp), the clock selection signal clksel is appropriately generated according to the state of the reception buffer.
When the state of (p = rp) continues for the time _Tr2 or more, the state transits to the reception standby state RST1.

[0058] In reception start condition RST2, clock selection signal generation circuit 20 calculates the raw data amount [Delta] D _r depending on equation (3), the clock selection signal c in response thereto
lksel is generated appropriately. For example, if the write address, read address, and clock frequency at time t are wp (t), rp (t), and fck (t), respectively, the unprocessed data amount ΔD of the reception buffer 45 at two different times t1 and t2. _r (t1), ΔD
_r (t2) is calculated according to the following equations.

[0059]

(Equation 4)

The clock selection signal generation circuit 20 calculates ΔD _r
If (t1)> ΔD _r (t2), fck (t1)> f
clock selection signal clkse so as to satisfy ck (t2)
Generate l.

When the reception standby state RST1 has continued for the time _Tr1 or more, the clock selection signal generation circuit 20 transitions to the suspend state RST0. After transition to the suspend state RST0, the clock selection signal generation circuit 20 first outputs the clock stop signal clkstp to the clock generation circuit 10. In response, the clock generation circuit 10 stops supplying the clock signal clk.
And the operation of the front end 50 is stopped.

In the suspend state RST0, the clock selection signal generation circuit 20 keeps monitoring the state of the receiving buffer 45, and when there is no unprocessed data in the receiving buffer 45, that is, when (wp = rp), the suspend state RS
It is held at T0. When unprocessed data is detected in the reception buffer 45, that is, when (wp> rp), the state transits to the reception standby state RST1.

As described above, the clock selection signal generation circuit 20 responds to the state of the reception buffer 45, specifically, the reception standby state RST1 and the reception start state according to the amount of unprocessed data ΔD _r accumulated in the reception buffer 45. It is held in either the state RST2 or the suspend state RST0. In each state, the clock selection signal clock selection signal generation circuit 20 in response to the raw data amount [Delta] D _r of receive buffer clksel or clock stop signal clkst
By appropriately generating p and supplying it to the clock generation circuit 10, the operation speeds of the signal processing circuit 30 and the front end 50 can be set optimally. By stopping the operation of 50, useless power consumption and generation of unnecessary radiation can be prevented.

FIG. 7 is a flowchart showing a flow of an operation at the time of reception in the communication apparatus of the present invention. Hereinafter, FIG.
The receiving operation will be described with reference to FIG. After the start of the receiving operation, first, the clock selection signal generation circuit 20 outputs a clock selection signal clksel for selecting the default clock signal clk0 having a predetermined frequency, and in response to this, outputs the clock signal to the signal processing circuit 30 and the front end 50. clk0 is supplied. The front end 50 establishes a connection with the transmission side via the communication path at the clock (step SR1).

Next, the clock selection signal generation circuit 20
The reception standby state is maintained (step SR2). In this state, the presence or absence of unprocessed data in the reception buffer 45 is detected, and reception is started according to the result of the detection (step SR3).

After the start of reception, the clock selection signal generation circuit 2
0 detects the status of the receive buffer 45 (step SR4), generates a clock selection signal clksel selecting an optimum clock signal in accordance with the amount [Delta] D _r of raw data stored in the reception buffer 45 (step SR
5).

Then, the clock generation circuit 10 generates an optimum clock signal clk by selecting it with the clock selection signal clksel and supplies it to the signal processing circuit 30 and the front end 50, respectively. The front end 50
The connection with the communication destination is established by the supplied clock signal clk, the reception data is received from the communication path, and the reception data is written into the reception buffer 45 (step SR6).

Then, the clock selection signal generation circuit 20
Is, for example, the amount ΔD of the unprocessed data in the reception buffer 45.
_It is determined whether the reception is terminated according to _r (step SR
7). If reception is to be continued, the process returns to step SR4. As described above, in the communication device of the present embodiment, until the received data stored in the reception buffer 45 becomes 0, the optimum clock signal is selected in accordance with the amount ΔD _r of the stored unprocessed data, and the selected clock signal is selected. , A series of operations for establishing a connection with the transmitting side, receiving the received data from the communication path, and writing the received data to the reception buffer 45 are repeatedly performed.

As described above, in the transmission and reception operations, the transmission buffer 41 or the reception buffer 45
, The frequency of the clock signal clk supplied to the signal processing circuit 30 and the front end 50 is optimally controlled. When transmission and reception are performed independently, for example, clock selection is performed with priority given to the one requesting the fastest clock signal. In a communication device having a transmitting device and a receiving device separately,
It is also possible to select an optimal clock signal in each of the transmitting device and the receiving device.

In the above-described transmission operation, the clock selection signal generation circuit 20 shifts from the transmission start state SST2 to the transmission standby state SST1 when no transmission data is detected for a certain period of time in the transmission start state SST2, and shifts to the transmission standby state SST1. After being held for a certain period of time or more, the state transition is controlled so as to transit to the suspend state SST0, but it is also possible to transit directly to the suspend state SST0 without passing through the transmission standby state SST1. Also,
Similarly, in the reception operation, when the reception data is not detected for a predetermined time or more in the reception start state RST2, the state transition is controlled such that the state transition directly from the transmission start state RST2 to the suspend state RST0 without passing through the reception standby state RST1. it can.

[0071]

As described above, according to the communication apparatus of the present invention, a clock signal having a minimum required clock frequency is supplied according to the communication speed, and the transmission / reception operation is performed accordingly. Power consumption can be reduced, and at the same time, generation of unnecessary radiation can be suppressed. Further, the communication device can control the communication device to be in the suspend state by controlling the hardware.
The burden on U can be reduced. Furthermore, in a communication device having separate transmitting and receiving devices, optimal clock frequency control can be realized for each of the transmitting and receiving devices, so that even in an asymmetric communication system, the power consumption of the communication device can be reduced and unnecessary electromagnetic radiation can be reduced. There is an advantage that suppression can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a communication device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a partial circuit related to a transmission operation.

FIG. 3 is a state transition diagram of a clock selection signal generation circuit during transmission.

FIG. 4 is a flowchart showing an operation at the time of transmission.

FIG. 5 is a block diagram showing a configuration of a partial circuit related to a receiving operation.

FIG. 6 is a state transition diagram of the clock selection signal generation circuit at the time of reception.

FIG. 7 is a flowchart showing an operation at the time of reception.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Clock generation circuit, 20 ... Clock selection signal generation circuit, 30 ... Signal processing circuit, 40 ... Transmission / reception buffer, 4
1 ... Transmission buffer, 42 ... Timer circuit, 43 ... Read address counter, 44 ... Write address counter, 4
5 reception buffer, 46 write address counter, 4
7: Read address counter, 50: Front end.

Claims (13)

[Claims] 1. A transmission apparatus for transmitting data at a predetermined communication speed, comprising: a transmission buffer for storing transmission data; a frequency-controlled clock signal, receiving a frequency-controlled clock signal at a speed corresponding to the frequency of the clock signal. A signal processing circuit for operating and sequentially writing information data to be transmitted as a transmission data sequence to the transmission buffer; receiving the clock signal, operating at a speed corresponding to the frequency of the clock signal; An interface circuit for sequentially reading and transmitting data; and controlling the frequency of a generated clock signal according to the amount of data stored in the transmission buffer to supply the clock signal to the signal processing circuit and the interface circuit, and transmitting the data at a predetermined time. A clock supply circuit for stopping the supply of the clock signal when there is no data. Communication device. 2. A receiving apparatus for receiving data transmitted at a predetermined communication speed, comprising: a receiving buffer for storing received data; A signal processing circuit that operates at a speed, sequentially reads received data from the reception buffer, and reproduces information data corresponding to the received data; and receives the clock signal, and operates at a speed corresponding to the frequency of the clock signal. An interface circuit that receives received data and sequentially writes the received data into the reception buffer, and controls the frequency of the generated clock signal according to the amount of data stored in the reception buffer to supply the clock signal to the signal processing circuit and the interface circuit; Clock supply for stopping supply of the clock signal when there is no received data for a predetermined time A receiving device having a circuit. 3. A communication device for transmitting and receiving data at a predetermined communication speed, comprising: a transmission buffer for storing transmission data; a reception buffer for storing reception data; It operates at a speed corresponding to the frequency of the clock signal, sequentially writes information data to be transmitted to the transmission buffer as a transmission data sequence, sequentially reads reception data from the reception buffer, and reproduces information data according to the reception data. A signal processing circuit, receiving the frequency-controlled clock signal, operating at a speed corresponding to the frequency of the clock signal, sequentially reading and transmitting the transmission data from the transmission buffer during transmission,
An interface circuit that receives received data at the time of reception and sequentially writes the received data into the reception buffer; and a signal processing circuit and the interface that control a frequency of a clock signal to be generated according to an amount of data stored in the transmission buffer and the reception buffer. A communication device comprising: a clock supply circuit that supplies a clock signal to a circuit when the transmission data and the reception data do not exist for a predetermined time. 4. The transmission buffer and the reception buffer,
The communication device according to claim 3, wherein the communication device is configured by an IFO. 5. The clock supply circuit according to claim 1, wherein the clock supply circuit generates a clock selection signal in accordance with the amount of data stored in the transmission buffer or the reception buffer, and has a frequency corresponding to the clock selection signal. The communication device according to claim 3, further comprising a clock generation circuit that generates a clock signal. 6. A clock selection signal, comprising: a first write counter for counting an amount of data written to the transmission buffer; and a first read counter for counting an amount of data read from the transmission buffer. 6. The communication device according to claim 5, wherein the generation circuit generates the clock selection signal according to a count value of the first write counter and a count value of the first read counter. 7. The clock selection signal generation circuit calculates a data accumulation amount of the transmission buffer according to a difference between a count value of the first write counter and a count value of the first read counter. 7. The communication device according to claim 6, wherein the clock selection signal is generated according to a data storage amount. 8. The communication device according to claim 7, wherein said clock selection signal generation circuit outputs a clock stop signal to said clock generation circuit when there is no transmission data in a predetermined time. 9. The communication device according to claim 8, wherein said clock generation circuit stops supplying said clock signal when receiving said clock stop signal from said clock selection signal generation circuit. 10. A clock selection signal, comprising: a second write counter for counting an amount of data written to the reception buffer; and a second read counter for counting an amount of data read from the reception buffer. The communication device according to claim 5, wherein the generation circuit generates the clock selection signal according to a count value of the second write counter and a count value of the second read counter. 11. The clock selection signal generation circuit calculates a data accumulation amount of the reception buffer according to a difference between a count value of the second write counter and a count value of the second read counter. The communication device according to claim 10, wherein the clock selection signal is generated according to a data storage amount. 12. The clock selection signal generation circuit outputs a clock stop signal to the clock generation circuit when there is no received data in a predetermined time.
The communication device as described. 13. The communication device according to claim 12, wherein said clock generation circuit stops supplying said clock signal when receiving said clock stop signal from said clock selection signal generation circuit.