JP2001060865A - Clock generation circuit and frequency correction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a clock generation circuit in a queuing mode. SOLUTION: A crystal vibrator (Xtal) 101 generates an original oscillation, a voltage controlled oscillator(VCO) 102 generates an operation clock of a clock reproduction part 103 from the original oscillation and the part 103 generates a reproduction clock. A learning circuit 104 learns the frequency deviation of the Xtal 101 of every frame from the change of a dividing cycle of the part 103. An arithmetic part 106 counts a prescribed number of frames corresponding to a non-receiving section via a counter 107, calculates a frequency deviation that is equivalent to the number of frames corresponding to the non-receiving section from the learning result of the circuit 104 and outputs the frequency deviation to a frequency correction part B 108. Then the part B 108 corrects en bloc and continuously the frequency deviations of the non-receiving section where the clock reproduction is so far stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit and a frequency correction method, and more particularly to a TDMA (Time D).
In a wireless communication system employing an ivision Multiple Access (time division multiplex) system, the present invention relates to a clock generation circuit and a frequency correction method for periodically correcting a reproduced clock in order to maintain synchronization with a base station.

[0002]

2. Description of the Related Art Conventionally, in a mobile communication system of the PDC (Personal Digital Cellular) system, a mobile station intermittently receives a control signal transmitted from a base station every plural frames during a standby time. Receiving. At this time, the mobile station corrects the frequency error of the reproduced clock generated between the mobile station and the base station as needed in order to maintain synchronization with the base station.

FIG. 8 is a main block diagram showing a schematic configuration of a conventional clock generation circuit. In FIG. 8, a crystal oscillator (Xtal) 11 is an element that performs original oscillation. The voltage controlled oscillator (VCO) 12 generates an operation clock of the clock reproducing unit 13 from the original oscillation. Clock regeneration unit 13
Generates a reproduction clock. The learning circuit 14 learns the frequency deviation of Xtal 11 per frame from the change of the frequency division cycle in the clock recovery unit 13. The frequency correction unit 15 periodically corrects the frequency deviation of Xtal11.

Next, the operation of the conventional clock generation circuit having the above configuration will be described with reference to FIG. FIG. 9 is a schematic diagram for explaining the operation of the conventional clock generation circuit during standby. During standby, the mobile station receives a control signal periodically transmitted from the base station. Here, it is assumed that a control signal is transmitted from the base station every eight frames. Therefore, for example, as shown in FIG. 9, each mobile station receives a control signal in each frame 3 during standby. One frame is composed of three slots, and each of the slots 0 to 2 is allocated to each of the mobile stations 1 to 3 and used. Therefore, the slot in which the mobile station 2 receives the control signal is the slot 1.

[0005] While receiving the control signal, the clock reproducing section 13 divides the clock supplied by the Xtal 11 and the VCO 12 while changing the dividing cycle, and generates a reproduced clock. That is, in the reception slot shown in FIG. 9, the clock recovery unit 13 keeps synchronization with the base station side by changing the frequency division period according to the phase change of the reception control signal. At this time, the learning circuit 14 learns the frequency deviation of Xtal11 per frame from the change of the frequency division period in the clock recovery unit 13.

[0006] Since the learning circuit 14 learns the frequency deviation per frame, the frequency correction unit 15 performs the frequency correction periodically for each frame according to the learning result except for the reception slot. Control. Therefore, the clock reproducing unit 13 can generate a reproduced clock synchronized with the base station, even in a slot other than the reception slot. This makes it possible for the mobile station to prevent loss of synchronization with the base station when the control signal is received next time.

[0007]

However, the conventional clock generating circuit has the following problems. That is, during standby, the devices provided in the mobile station do not need to operate in other than the reception slot, so that it is not necessary to generate a reproduced clock in other than the reception slot. However, in the above-described conventional clock generation circuit, it is necessary to maintain synchronization with the base station when the next control signal is received (next reception slot). And the frequency correction unit 15 must always be operated. Therefore, there is a problem that the power consumption of the clock generation circuit increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a clock generation circuit and a frequency correction method capable of reducing power consumption during standby.

[0009]

A clock generating circuit according to the present invention comprises an oscillating means for generating an original oscillation, a clock generating means for generating a clock from the original oscillation, and a learning means for learning a frequency deviation of the original oscillation. And control means for controlling an operation stop section of the clock generation means, and correction means for correcting a frequency deviation of the original oscillation in the operation stop section in accordance with a learning result of the learning means.

In the clock generation circuit according to the present invention, the control means controls the operation stop section of the clock generation means in accordance with the number of transmission units in the non-reception section of the reception signal, and the correction means performs the operation before the clock generation means starts operating. A configuration is adopted in which frequency deviations corresponding to the number of transmission units are collectively corrected.

According to these configurations, the frequency deviation in the non-reception section is collectively and continuously corrected immediately before the start of the reception section, so that the generation of the reproduced clock is stopped in the sections other than the reception section. Power consumption can be reduced.

[0012] The clock generation circuit of the present invention includes a reception quality measuring means for measuring the reception quality, and the control means adopts a configuration for changing the number of transmission units according to the reception quality.

According to this configuration, when it becomes necessary to perform predetermined processing due to deterioration of reception quality, the communication terminal apparatus can perform the necessary processing before the start of a reception section.

[0014] The clock generation circuit of the present invention includes comparison and detection means for detecting deterioration of reception quality by comparing a past reception quality measurement value and a current reception quality measurement value,
The correction means is configured to correct the frequency deviation of the original oscillation in the operation stop interval according to the past learning result when the reception quality is deteriorated.

According to this configuration, when the reception quality is temporarily deteriorated, the frequency correction is performed using the frequency deviation learned before that. Therefore, even if the reception quality is temporarily degraded, the frequency is corrected. Since the correction can be performed with high accuracy, stable clock reproduction can be performed.

The clock generation circuit according to the present invention employs a configuration in which the comparison and detection means compares the average value of the past reception quality measurement values with the current reception quality measurement value.

According to this configuration, since a plurality of measured values measured in the past are averaged and used, the reliability of the past measured values can be improved.

The clock generation circuit according to the present invention comprises a temperature measuring means for measuring the temperature around the device, a past temperature measurement value and a current temperature measurement value measured by the temperature measurement means, and a past learning result by the learning means. And comparison detection means for detecting the deterioration of the reception quality by comparing the current learning result with the current learning result. When the reception quality deteriorates, the correction means detects the frequency of the original oscillation in the operation stop section according to the past learning result. A configuration for correcting the deviation is employed.

According to this configuration, the learning value of the frequency deviation used for the frequency correction is switched according to the relationship between the change in the ambient temperature of the communication terminal device equipped with the clock generation circuit and the change in the learning value of the frequency deviation. Therefore, even if the reception quality is temporarily deteriorated, the frequency can be accurately corrected, so that stable clock reproduction can be performed.

The clock generation circuit according to the present invention employs a configuration in which the comparison and detection means compares the average value of past temperature measurement values with the current temperature measurement value.

According to this configuration, since a plurality of measured values measured in the past are averaged and used, the reliability of the past measured values can be improved.

The clock generation circuit of the present invention employs a configuration in which the comparison detection means compares the average value of the past learning results with the current learning result.

According to this configuration, since the past learning results are averaged and used, the reliability of the past learning results can be improved.

The communication terminal device according to the present invention employs a configuration in which any one of the above clock generation circuits is mounted. According to this configuration, battery saving can be achieved in the communication terminal device.

According to the frequency correction method of the present invention, the frequency deviation of the original oscillation is learned, and the frequency deviation of the original oscillation in the section where the clock generation is stopped according to the learning result is corrected collectively before the start of the clock generation. did.

According to this method, the frequency deviation in the non-reception section is collectively and continuously corrected immediately before the start of the reception section, so that the generation of the reproduction clock is stopped in other than the reception section. The power can be reduced.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present inventor has realized that if the frequency deviation per frame is constant, it is not necessary to sequentially perform frequency correction in a non-receiving section, and has arrived at the present invention. That is, the gist of the present invention is to correct the frequency deviation corresponding to the number of frames corresponding to the non-reception section existing between the reception frames in a batch immediately before the reception slot in a lump, so that the frequency deviation other than the reception frame is excluded. This is to stop the generation of the reproduction clock.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Embodiment 1) A clock generation circuit and a frequency correction method according to Embodiment 1 of the present invention provide a clock generation circuit and a frequency correction for a number of frames corresponding to a non-reception section existing between reception frames, by using , The generation of the reproduction clock is stopped except for the reception frame.

FIG. 1 is a main block diagram showing a schematic configuration of the clock generation circuit according to the first embodiment of the present invention.
In FIG. 1, a crystal oscillator (Xtal) 101 is an element that performs original oscillation. Voltage controlled oscillator (VCO) 102
Generates an operation clock of the clock recovery unit 103 from the original oscillation. The clock reproducing unit 103 generates a reproduced clock. The learning circuit 104 calculates Xtal 101 per frame based on the change of the frequency division period in the clock recovery unit 103.
Learn the frequency deviation of. The frequency correction unit A105 periodically corrects the frequency deviation of the Xtal 101 when it is necessary to generate a reproduced clock in the non-receiving section.
Here, the case where the reproduction clock needs to be generated in the non-reception section refers to a case where it is necessary to perform a process other than communication, such as voice memo reproduction, by the operation of the mobile station user at the time of standby.

The arithmetic section 106 counts a predetermined number of frames corresponding to the non-reception section by the counter 107, and calculates a frequency deviation corresponding to the number of frames corresponding to the non-reception section from the learning result of the learning circuit 104. Then, the signal is output to the frequency correction unit B108. The frequency correction unit B108 corrects the frequency deviation in the non-reception section in which the clock recovery operation has been stopped for a plurality of frames continuously and continuously.

Next, the operation of the clock generation circuit having the above configuration will be described with reference to FIG. FIG. 2 is a schematic diagram for explaining the operation of the clock generation circuit according to the first embodiment of the present invention during standby. During standby,
The mobile station periodically receives a control signal transmitted from the base station. Here, it is assumed that a control signal is transmitted from the base station every eight frames. Thus, for example, each mobile station:
As shown in FIG. 2, at the time of standby, a control signal is received in each frame 3. Also, one frame is composed of three slots, and since it is a TDMA system, each of the slots 0 to 2 is allocated to each of the mobile stations 1 to 3 and used. Therefore, for example, if the mobile station equipped with the clock generation circuit according to the present embodiment is the mobile station 2, the slot in which the control signal is received is the slot 1.

In the receiving slot, the clock reproducing section 103 divides the clock supplied by the Xtal 101 and the VCO 102 while changing the dividing cycle, and generates a reproduced clock. That is, in the reception slot shown in FIG. 2, the clock recovery unit 103 keeps synchronization with the base station side by changing the frequency division period according to the phase change of the reception control signal. At this time, the learning circuit 104
Is 1 from the change of the frequency division period in the clock recovery unit 103.
The frequency deviation of Xtal 101 per frame is learned.

On the other hand, except for the reception slot, the clock reproducing unit 103 stops the clock reproduction. Arithmetic unit 106
Is the frame corresponding to the non-receiving section (frames 4 and 2)
The number is counted by incrementing the counter 107 one by one. In the counter 107, a predetermined number of frames corresponding to a non-receiving section is set in advance. Then, when the counter value reaches the predetermined number, that is, when the next received frame is reached, the frequency deviation corresponding to the number of frames corresponding to the non-reception section is continuously and continuously performed as follows. Is corrected.

That is, in slot 0 assigned to another mobile station user, which is located immediately before reception slot 1 assigned to the own station, arithmetic unit 106
The frequency deviation per frame is read from the learning circuit 104, and the frequency deviation is multiplied by the counter value to calculate the frequency deviation for the number of frames corresponding to the non-receiving section. Specifically, the frequency deviation for seven frames of frames 4 and 2 is calculated.

Next, the calculating section 106 outputs the calculated frequency deviation to the frequency correcting section B108. Based on the calculated value, the frequency correction unit B108
3 and outputs the correction pulses collectively and continuously. As a result, the number of frames corresponding to the non-reception section (here, 7
The frequency deviation corresponding to (frame) is corrected collectively and continuously in slot 0 immediately before reception slot 1.

Therefore, even if a reproduced clock is not generated in order to sequentially correct the frequency deviation in a slot other than the receiving slot, the synchronization with the base station occurs in the slot 1 where the next control signal is received. Can be prevented. In the non-reception period, the clock recovery unit 103 does not need to generate a recovered clock, so that the operations of the VCO 102 and the clock recovery unit 103 that consume a large amount of power can be completely stopped.
Power consumption of the clock generation circuit can be suppressed.

In the clock generation circuit according to the present embodiment, the section in which the clock reproduction is stopped can be appropriately changed by appropriately changing the predetermined number of frames previously set in the counter 107.

As a result, a reproduced clock can be generated several frames before the received frame. Therefore, when a predetermined process needs to be performed in the mobile station before the reception frame, the process can be performed. When it is necessary to generate a reproduced clock in the non-receiving section, the frequency correction unit A105 periodically corrects the frequency deviation during the clock reproduction.

Further, by configuring the clock generation circuit according to the present embodiment as shown in FIG. 3, it is possible to adaptively change the predetermined number of frames set in the counter 107 according to the reception quality. Can be. Thereby, the section in which the clock reproduction is stopped can be adaptively changed according to the reception quality.

FIG. 3 is a main block diagram showing another schematic configuration of the clock generation circuit according to the first embodiment of the present invention. In FIG. 3, reception quality measuring section 301 measures the reception quality of a control signal. As the value indicating the reception quality, for example, RSSI (Received Signal Strength Indicato
r: desired signal reception power), ISSI (Interference Signal)
Strength Indicator: interference wave received power, SIR (Sig
nal to Interference Ratio)
Is used, but the present invention is not limited to these, and any value may be used as long as the value can indicate the reception quality. When the reception quality has deteriorated below a predetermined threshold value, control section 302 decreases the predetermined number of frames set in counter 107.

Thus, when the reception quality is degraded, a reproduced clock can be generated several frames before the next reception frame. Therefore, when it is necessary to perform predetermined processing (for example, cell search and handover processing) due to deterioration of reception quality, for example,
Before the reception frame, the mobile station can perform the necessary processing. When it is necessary to generate a reproduced clock in the non-receiving section, the frequency correction unit A105 periodically corrects the frequency deviation during the clock reproduction.

As described above, according to the clock generation circuit and the frequency correction method according to the present embodiment, the frequency deviation for the number of frames corresponding to the non-reception section existing between the reception frames is determined by using the slot deviation immediately before the reception slot. , The generation of the reproduction clock is stopped except for the reception frame, so that the power consumption during standby can be reduced.

(Embodiment 2) The clock generation circuit according to the present embodiment has substantially the same configuration as that of Embodiment 1, and if the reception quality is temporarily deteriorated, it is learned before that. The difference is that the frequency correction is performed using the frequency deviation.

When the reception control signal becomes unstable due to the burst-like deterioration of the reception quality in the reception slot,
An error may occur in the frequency deviation learned by the learning circuit. In this case, since the frequency correction is performed based on the erroneous learning value, the mobile station may lose the synchronization of the reproduced clock with the base station. Therefore, in the clock generation circuit and the frequency correction method according to the second embodiment of the present invention, when the reception quality is temporarily deteriorated, the frequency correction is performed using the frequency deviation learned before that. Things.

FIG. 4 is a main block diagram showing a schematic configuration of a clock generation circuit according to the second embodiment of the present invention.
In FIG. 4, the learning circuit 401 includes a clock recovery unit 10
Xtal per frame from the change of the dividing cycle at 3
The frequency deviation of 101 is learned, and the learned frequency deviation is stored in the learning result storage unit 402.

Receiving quality measuring section 403 measures the receiving quality of the control signal received in the receiving slot, and holds a value indicating the receiving quality in measurement result holding section 404.

The comparing section 405 includes a value indicating the reception quality measured this time and a value indicating the reception quality measured in the immediately preceding reception slot (the value indicating the reception quality held in the measurement result holding section 404). ) Is calculated, and if the difference is equal to or greater than a predetermined threshold, the calculation unit 406 is notified of the difference. That is, when the amount of deterioration of the reception quality is equal to or more than the predetermined threshold, comparison section 405 notifies arithmetic section 406 of the fact.

The arithmetic unit 406 sends the notification to the comparing unit 405
, The frequency correction amount is calculated using the frequency deviation held in the learning result holding unit 402. That is, when the deterioration amount of the reception quality of the control signal received this time is equal to or more than the predetermined threshold, the arithmetic unit 406 determines the frequency learned based on the control signal received in the previous reception slot. Using the deviation, a frequency correction amount is calculated.

Next, the operation of the clock generation circuit having the above configuration will be described with reference to FIG. FIG. 5 is a schematic diagram for explaining the operation of the clock generation circuit according to the second embodiment of the present invention during standby.

The learning circuit 401 includes reception slots A and B
, The frequency deviation is learned, and the learning result is held in the learning result holding unit 402. Also, reception quality measuring section 403
Measures the reception quality of the control signal in the reception slots A and B, and holds the measurement result in the measurement result holding unit 404.

In reception slot B, comparison section 405
Are the value indicating the reception quality in the reception slot B measured this time and the value indicating the reception quality measured in the immediately preceding reception slot A (the value indicating the reception quality held in the measurement result holding unit 404). ) Is calculated. Then, when the difference is equal to or larger than the predetermined threshold value and the reception quality is significantly deteriorated, comparison section 405 notifies arithmetic section 406 of the fact.

In this case, the calculation unit 406 does not use the frequency deviation learned in the reception slot B,
The frequency correction amount is calculated using the frequency deviation learned in the reception slot A held in the learning result holding unit 402.

In the clock generation circuit according to the present embodiment, reception quality measurement section 403 averages values indicating reception quality measured in a plurality of past slots, and measures an average value of values indicating reception quality. Held in the result holding unit 404,
The comparing unit 405 may calculate the deterioration amount of the reception quality using the average value and the value indicating the reception quality measured this time. Since a plurality of measured values measured in the past are averaged and used, the reliability of past measured values can be improved.

As described above, according to the clock generation circuit and the frequency correction method according to the present embodiment, when the reception quality is temporarily deteriorated, the frequency correction is performed using the frequency deviation learned before that. Therefore, even if the reception quality temporarily deteriorates, the frequency correction can be performed with high accuracy, and thus stable clock reproduction can be performed.

(Embodiment 3) The clock generation circuit and the frequency correction method according to the present embodiment have substantially the same configuration as that of the first embodiment, and measure the ambient temperature of the communication terminal device equipped with the clock generation circuit. The difference is that the learning value of the frequency deviation used for frequency correction is switched according to the relationship between the change and the change of the learning value of the frequency deviation.

FIG. 6 is a main block diagram showing a schematic configuration of a clock generation circuit according to the third embodiment of the present invention.
In FIG. 6, the learning circuit 601 includes a clock recovery unit 10.
Xtal per frame from the change of the dividing cycle at 3
The frequency deviation of 101 is learned, and the learned frequency deviation is stored in the learning result storage unit 602.

The temperature measuring section 603 measures the peripheral temperature of the communication terminal device equipped with the clock generating circuit, and stores the measured temperature in the measurement result storing section 604.

The comparing section 605 calculates the difference between the frequency deviation learned this time and the frequency deviation learned in the immediately preceding reception slot (frequency deviation held in the learning result holding section 602), and calculates the difference. The difference is compared with a predetermined threshold. Further, the comparison unit 605 calculates the temperature measured this time,
The difference between the temperature measured in the immediately preceding reception slot (the temperature held in the measurement result holding unit 604) is calculated, and the difference is compared with a predetermined threshold.

When the variation of the learning value of the frequency deviation is greater than or equal to a predetermined threshold value and the variation of the temperature is smaller than the predetermined threshold value, the comparing unit 605 calculates that fact. Notify unit 606. That is, the comparison unit 605
Notifies the calculation unit 606 of a large change in the learning value of the frequency deviation despite the small temperature change.

The calculating unit 606 sends the notification to the comparing unit 605.
, The frequency correction amount is calculated using the frequency deviation held in the learning result holding unit 602. That is, when the change amount of the learning value of the frequency deviation is large despite the small temperature change, the calculation unit 606 uses the frequency deviation learned based on the control signal received in the previous reception slot. Then, the frequency correction amount is calculated.

Here, when the amount of change in the learning value of the frequency deviation is large despite the small temperature change, the frequency deviation learned based on the control signal received in the previous reception slot is used. The reason for calculating the frequency correction amount is as follows. That is, the change in the frequency deviation depends on the change in the oscillation frequency of the Xtal 101 due to the temperature change and the change in the reception quality of the control signal, but when the change in the frequency deviation becomes large despite the small temperature change amount, This is because it is considered that the reception quality of the control signal is greatly deteriorated. Therefore, in this case, the calculation unit 606 calculates the frequency correction amount using the frequency deviation learned based on the control signal received in the previous reception slot.

Further, even if the amount of change in the frequency deviation is large, if the cause is a change in the oscillation frequency of Xtal 101 due to a change in temperature, the amount of change in the temperature is also large. Therefore, in this case, the arithmetic unit 606 calculates the frequency correction amount using the frequency deviation deviation learned this time in order to correct the error of the oscillation frequency of the Xtal 101.

Next, the operation of the clock generation circuit having the above configuration will be described with reference to FIG. FIG. 7 is a schematic diagram for explaining the operation of the clock generation circuit according to the third embodiment of the present invention during standby.

The learning circuit 601 includes reception slots A and B
, The frequency deviation is learned, and the learning result is stored in the learning result storage unit 602. In addition, the temperature measurement unit 603 measures the ambient temperature of the communication terminal device equipped with the clock generation circuit in the reception slots A and B, and stores the measurement result in the measurement result storage unit 604.

In the receiving slot B, the comparing unit 605
If the change amount of the learning value of the frequency deviation is equal to or more than a predetermined threshold value and the change amount of the temperature is smaller than the predetermined threshold value as a result of the comparison operation,
Notify 6.

In this case, the calculation unit 606 does not use the frequency deviation learned in the reception slot B,
The frequency correction amount is calculated using the frequency deviation learned in the reception slot A held in the learning result holding unit 602.

In the clock generation circuit according to the present embodiment, the temperature measurement section 603 averages the temperatures measured in a plurality of past slots, holds the average temperature in the measurement result holding section 604, and The unit 605 may calculate the amount of change in temperature by comparing the average value with the temperature measured this time. Since a plurality of temperatures measured in the past are averaged and used, the reliability of past measured values can be improved.

In the clock generation circuit according to the present embodiment, the learning circuit 601 averages the frequency deviations learned in a plurality of past slots, and stores the average value of the frequency deviations in the learning result holding unit 602. It may be.
Since a plurality of frequency deviations learned in the past are averaged and used, the reliability of the learned value of the past frequency deviation can be improved.

As described above, according to the clock generation circuit and the frequency correction method according to the present embodiment, the relationship between the change in the ambient temperature of the communication terminal device equipped with the clock generation circuit and the change in the learning value of the frequency deviation is determined. Accordingly, the learning value of the frequency deviation used for the frequency correction is switched, so that even if the reception quality temporarily deteriorates, the frequency correction can be performed with high accuracy, and thus stable clock reproduction can be performed.

The above first to third embodiments can be applied to a communication terminal device such as a mobile phone used in a mobile communication system. When applied, battery saving can be achieved in the communication terminal device.

Further, the first to third embodiments can be implemented in appropriate combinations.

[0072]

As described above, according to the present invention, power consumption during standby can be reduced.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing a schematic configuration of a clock generation circuit according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram for explaining the operation of the clock generation circuit according to the first embodiment of the present invention in a standby state;

FIG. 3 is a main part block diagram showing another schematic configuration of the clock generation circuit according to the first embodiment of the present invention;

FIG. 4 is a main block diagram illustrating a schematic configuration of a clock generation circuit according to a second embodiment of the present invention;

FIG. 5 is a schematic diagram for explaining the operation of the clock generation circuit according to the second embodiment of the present invention during standby;

FIG. 6 is a main block diagram showing a schematic configuration of a clock generation circuit according to a third embodiment of the present invention;

FIG. 7 is a schematic diagram for explaining the operation of the clock generation circuit according to the third embodiment of the present invention during standby;

FIG. 8 is a main block diagram showing a schematic configuration of a conventional clock generation circuit.

FIG. 9 is a schematic diagram for explaining the operation of the conventional clock generation circuit during standby.

[Explanation of symbols]

 101 Crystal Resonator (Xtal) 102 Voltage Controlled Oscillator (VCO) 103 Clock Recovery Unit 104, 401, 601 Learning Circuit 105 Frequency Correction Unit A 106, 406, 606 Operation Unit 107 Counter 108 Frequency Correction Unit B 301, 403 Reception Quality Measurement Unit 302 control unit 402, 602 learning result storage unit 404, 604 measurement result storage unit 405, 605 comparison unit 603 temperature measurement unit

Claims (10)

[Claims] An oscillation unit for generating an original oscillation, a clock generation unit for generating a clock from the original oscillation, a learning unit for learning a frequency deviation of the original oscillation, and controlling an operation stop section of the clock generation unit A clock generation circuit, comprising: a control unit that performs the operation and a correction unit that corrects a frequency deviation of the original oscillation in the operation stop period according to a learning result of the learning unit. 2. The control unit controls an operation stop period of the clock generation unit according to the number of transmission units in a non-reception period of a received signal, and the correction unit determines the number of transmission units before the operation of the clock generation unit starts. 2. The clock generation circuit according to claim 1, wherein the frequency deviation is corrected collectively. 3. The clock generation circuit according to claim 2, further comprising reception quality measurement means for measuring reception quality, wherein the control means changes the number of transmission units according to the reception quality. 4. A comparison detection means for detecting deterioration of reception quality by comparing a past reception quality measurement value and a current reception quality measurement value, and wherein the correction means is provided when the reception quality deteriorates. 4. The clock generation circuit according to claim 1, wherein a frequency deviation of the original oscillation in the operation stop section is corrected according to a past learning result. 5. The clock generation circuit according to claim 4, wherein the comparison and detection means compares the average value of the past reception quality measurement values with the current reception quality measurement value. 6. A temperature measuring means for measuring the temperature around the device, a past temperature measurement value and a current temperature measurement value measured by the temperature measuring means, and a past learning result and a current learning result by the learning means. And comparing means for detecting the deterioration of the reception quality by comparing
4. The clock generation circuit according to claim 1, wherein when the reception quality is deteriorated, the frequency deviation of the original oscillation in the operation stop section is corrected according to a past learning result. 7. The clock generation circuit according to claim 6, wherein the comparison detection means compares an average value of past temperature measurement values with a current temperature measurement value. 8. The clock generation circuit according to claim 6, wherein the comparison detection means compares an average value of past learning results with a current learning result. 9. A communication terminal device comprising the clock generation circuit according to claim 1. 10. A frequency correction method comprising: learning a frequency deviation of an original oscillation; and correcting the frequency deviation of the original oscillation in a section in which clock generation is stopped in accordance with the learning result before the start of clock generation. .