JP2001057341A - Manufacturing method of semiconductor and semiconductor device manufactured, therethrough - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor which is lessened in through dislocation density through a manufacturing process which is simplified by taking advantage of a mass transport phenomenon. SOLUTION: An AlN layer 7 serving as a buffer layer is laminated on a substrate 4, a III nitride layer such as a GaN layer 8 is formed on the GaN layer 8, a recessed structure 13 is provided to the GaN layer 8, the substrate 4 where the recessed structure 13 is formed is heated at a temperature of 600 to 1300 deg.C (e.g. 1000 deg.C), nitrogen gas as carrier gas is fed into a chamber, and ammonia gas is fed as a V group source. By this setup, a mass transport phenomenon where a part of material that forms the GaN layer is moved in the lateral direction in a recessed structure 13 is produced, by which a low- dislocation density region 16 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing method for manufacturing a group III nitride semiconductor utilizing a mass transport phenomenon, and a semiconductor device manufactured by the manufacturing method.

[0002]

2. Description of the Related Art A group III nitride semiconductor is 1.9 in InN.
Since it has a direct transition band gap in a wide range from eV to 6.2 eV of AlN, it is expected as a material for laser diodes corresponding to the visible region to the ultraviolet region, and a laser using a group III nitride semiconductor as a material. Diode lasing has been announced by many groups to date. Group III nitride semiconductors are also expected to be used as ultraviolet detectors that do not react to visible light and as materials for high-power microwave transistors.

When a conventional semiconductor manufacturing method is used, it is difficult to produce a bulk single crystal having a sufficient size, and there is no alternative substrate having a lattice constant and a coefficient of thermal expansion that match. It is not easy to obtain a good epitaxial growth layer. Therefore, sapphire substrates and SiC
AlN, Ga deposited at a relatively low temperature on a substrate such as a substrate
A technique for growing a group III nitride semiconductor using N or a mixed crystal thereof as a buffer layer between a substrate and a group III nitride semiconductor has been proposed. An epitaxial film having a sufficient crystal quality can be obtained, and a light emitting diode corresponding to a region from ultraviolet to green using the same material has been put to practical use.

[0004] The technique using the low-temperature deposited buffer layer is disclosed by Iwatani et al. In "Jpn. J. Appl. Phys. Vol. 37 (1998) L316". This technique can reduce the threading dislocation density. it can. In recent years, ELO (Epitaxial Lateral Overlay) for selectively growing crystals using a dielectric film has been developed.
growth) technology by Usui et al., "Jpn.J.Appl.Phys.Vol.
36 (1997) L899 ", and this technique can also reduce the threading dislocation density. Also, pnde
o-epitaxy technology by Ms.
J. Nitride Semicond.Res.4SI.G3.38 (1999) ”and embedded regrowth technology by Matsushita et al.
It has been announced at the 46th Applied Physics-related Lecture Meeting 30P-M-17 in the spring of 1999, and the threading dislocation density can be reduced by these techniques.

[0005]

SUMMARY OF THE INVENTION Using the above ELO technology,
In some cases, the process is considerably complicated and
The problem that impurities in the dielectric film remain in the crystal
Occurs. In addition, using the low-temperature deposition buffer layer described above,
When growing Group III nitride semiconductors, threading dislocation density
Degree can be greatly reduced, but still 1
0⁸ -10¹¹cm ^-2Degree of threading dislocations will remain.
You. When such high-density threading dislocations remain, laser
Diodes hinder life improvement and threshold reduction,
In UV detectors, the dark current increases, and electronic devices
In a chair, the mobility is reduced. That
Crystal growth technology to achieve even lower defect characteristics,
There is a demand for the development of a highly efficient quantum structure fabrication technology.

According to the present invention, it is possible to reduce the threading dislocation density and form a fine structure by forming a region having physical properties different from those of a base material by a simplified manufacturing process utilizing a mass transport phenomenon. It is a first object of the present invention to provide a method of manufacturing a semiconductor. A second object of the present invention is to provide various semiconductor elements having a reduced threading dislocation density or various semiconductor elements having a fine structure such as a quantum wire by the above-described method for manufacturing a semiconductor.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor manufacturing method for manufacturing a group III nitride semiconductor, comprising the steps of:
Stacking a group I nitride layer, forming a step structure in the group III nitride layer, heating the substrate having the step structure formed thereon at a temperature of 600 to 1300 ° C. Supplying a predetermined substance to cause a mass transport phenomenon in which a part of the substance forming the group III nitride layer is moved into the step structure.

[0008] In order to achieve the first object, a second aspect is provided.
The second invention described in the above is a semiconductor manufacturing method for manufacturing a group III nitride semiconductor, comprising the steps of: laminating a buffer layer made of a nitrogen compound on a substrate; and forming a group III nitride layer on the buffer layer. Laminating, forming a step structure on the group III nitride layer, and removing the substrate having the step structure formed thereon by 60
By heating at a temperature of 0 to 1300 ° C. and supplying a predetermined substance during the heating, a mass transport phenomenon occurs in which a part of the substance forming the group III nitride layer is moved into the step structure. And a process.

[0009] The third invention of claim 3, wherein the III-nitride layer has the general formula _{B x Al y In z Ga 1} -xyz N ( However, 0 ≦ x ≦
1,0 ≦ y ≦ 1,0 ≦ z ≦ 1) containing at least nitrogen and a group III element
It is made of a group III nitride semiconductor material.

According to a fourth aspect of the present invention, one or both of the carrier gas and the group V source are used as the predetermined substance from the start of the heating until the temperature is lowered to a predetermined temperature of less than 600 ° C. It is characterized in that it is supplied to the surface.

According to a fifth aspect of the present invention, the carrier gas is one or a mixture of two or more of hydrogen gas, nitrogen gas and other inert gas,
The Group V source is a compound containing nitrogen such as ammonia.

According to a sixth aspect of the present invention, there is provided a semiconductor device according to the sixth aspect, wherein the group III element constituting the group III nitride layer is heated when the substrate is heated.
It is characterized by supplying Group III sources.

A seventh aspect of the present invention is characterized in that a group III source of a group III element different from the group III element constituting the group III nitride layer is supplied when the substrate is heated. .

According to an eighth aspect of the present invention, in the case where the group III nitride layer is made of a mixed crystal, when the substrate is heated,
The method is characterized in that one or more Group III sources among the Group III elements constituting the Group III nitride layer are supplied.

According to a ninth aspect of the present invention, the growth rate and the growth state of the substance grown by the mass transport phenomenon, and the composition and crystal quality of the group III nitride layer after the substance growth are determined by adjusting the growth plane orientation, Control is performed by adjusting a substrate heating temperature, a substrate heating time, a pressure in a growth furnace, a step shape, and a supply amount of the predetermined substance.

In order to achieve the second object, a first aspect of the present invention is provided.
A tenth aspect of the present invention is a semiconductor device manufactured by the method of manufacturing a semiconductor according to the first to ninth aspects, wherein regions having different physical properties are formed in a direction parallel to a substrate surface. , Light emitting diode, photodiode, FET light receiving element, HBT light receiving element, FET,
It is characterized in that it is any one semiconductor element of HBT or two or more integrated elements.

[0017]

According to the first invention, a group III nitride layer is laminated on a substrate, a step structure is formed in the group III nitride layer, and then the substrate having the step structure is formed in a range of 600 to 130.
Heating is performed at a temperature of 0 ° C. and a predetermined substance is supplied during the heating, thereby causing a mass transport phenomenon in which a part of the substance forming the group III nitride layer is moved into the step structure. As described later, the group III nitride layer in which the substance moves (grows) into the step due to the mass transport phenomenon has a remarkably reduced threading dislocation density. Therefore, it is possible to provide a method of manufacturing a semiconductor which can reduce the threading dislocation density as desired.

In the second invention, a buffer layer made of a nitrogen compound is laminated on a substrate, a group III nitride layer is laminated on the buffer layer, and a step structure is formed in the group III nitride layer.
The substrate with the step structure formed is subjected to a temperature of 600 to 1300 ° C.
At the same time as heating at a temperature and supplying a predetermined substance during heating,
This causes a mass transport phenomenon in which a part of the substance forming the group III nitride layer is moved into the step structure. As described later, the group III nitride layer in which the substance moves (grows) into the step due to the mass transport phenomenon has a remarkably reduced threading dislocation density. Therefore, it is possible to provide a method of manufacturing a semiconductor which can reduce the threading dislocation density as desired.

[0019] In the third invention, the III-nitride layer has the general formula _{B x Al y In z Ga 1-} xyx N ( provided that
0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1)
Since the group III nitride layer is composed of a group III nitride semiconductor material containing at least nitrogen and a group III element, the group III nitride layer is suitable for use as the group III nitride layer of the first or second invention. .

In the fourth invention, one or both of a carrier gas and a group V source as the predetermined substance are supplied to the surface of the substrate during a period from the start of the heating of the substrate to a predetermined temperature lower than 600 ° C. Therefore, a group III nitride layer in which a substance moves (grows) in a step due to mass transport phenomenon can be manufactured without supplying a group III source during heating of the substrate. In addition, by appropriately adjusting the supply amount and the supply ratio of the predetermined substance, it is possible to control the growth rate, the growth position, and the composition of the substance grown in the step due to the mass transport phenomenon.

In the fifth invention, the carrier gas is a hydrogen gas, a nitrogen gas or another inert gas,
Any one or a mixture of two or more gases,
Since the group source is a compound containing nitrogen such as ammonia,
The carrier gas and the group V source are suitable for use as the carrier gas and the group V source of the fourth invention, respectively.

In the sixth invention, since the group III source of the group III element constituting the group III nitride layer is supplied when the substrate is heated, the supply amount and the supply ratio of the group III source are appropriately adjusted. This makes it possible to control the composition and crystal quality of the group III nitride layer in which the substance is grown in the step due to the mass transport phenomenon.

In the seventh invention, since the group III source of the group III element different from the group III element constituting the group III nitride layer is supplied at the time of heating the substrate, the supply amount of the group III source can be reduced. By appropriately adjusting the supply ratio, it is possible to control the composition and crystal quality of the group III nitride layer in which the substance is grown in the step due to the mass transport phenomenon.

In the eighth invention, when the group III nitride layer is made of a mixed crystal, one or two or more of the group III elements constituting the group III nitride layer are formed when the substrate is heated. Since the Group III source is supplied, the composition and composition of the mixed crystal, which is the Group III nitride layer in which the substance is grown in the step due to the mass transport phenomenon, are appropriately adjusted by adjusting the supply amount and the supply ratio of the Group III source. Crystal quality can be controlled.

In the ninth invention, the growth rate and the growth state of the substance grown by the mass transport phenomenon and the composition and crystal quality of the group III nitride layer after the substance growth are determined by the growth plane orientation, the substrate heating temperature, the substrate Heating time,
Since the pressure in the growth furnace, the step shape, and the supply amount of the predetermined substance are controlled to be controlled, it has a desired shape and composition and has a low threading dislocation density III.
A group nitride layer can be formed.

According to a tenth aspect of the present invention, there is provided a semiconductor device in which regions having different physical properties are formed in a direction parallel to a substrate surface by using the semiconductor manufacturing method according to the first to ninth aspects. , Light emitting diode, photodiode, FET type light receiving element, HBT type light receiving element,
It is possible to manufacture any one of a semiconductor device of FET, HBT or a semiconductor device which is an integrated device of two or more.
As will be described later, the manufactured semiconductor device has a reduced threading low dislocation density or a fine structure such as a quantum wire.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1 (a) and 1 (b) are diagrams illustrating the configuration of an atmospheric pressure organometallic compound vapor phase growth apparatus used for carrying out the semiconductor manufacturing method according to the first embodiment of the present invention, and a cross-sectional view taken along the line AA. It is. As shown in FIGS. 1A and 1B, the atmospheric pressure organometallic compound vapor deposition apparatus 1 transmits a source gas supply unit 2 and a source gas supplied from the source gas supply unit 2 to a susceptor 3. Reaction tube 5 leading to substrate 4
And an exhaust system 6 for discharging the raw material gas to the outside through the reaction tube 5
The substrate 4 is set on the slope of the susceptor 3. The source gas supply unit 2 includes a trimethyl gallium (TMGa) gas, a trimethyl aluminum (TMAl) gas, a trimethyl indium (TMI) gas.
n) Gas supply devices 2-1 to 2-4 for supplying gas and ammonia (NH ₃ ) gas and gas supply devices for supplying other source gases are provided, respectively.

Next, a manufacturing method for manufacturing a light emitting device using the atmospheric pressure organometallic compound vapor deposition apparatus 1 will be described.
In this case, the substrate 4 is a sapphire substrate (000
1) A surface shall be used. First, the substrate 4 is set on the slope of the susceptor 3 located at the end of the reaction tube 5, and the substrate surface is maintained for several minutes at a substrate temperature of about 1000 ° C. in a hydrogen gas flow to thereby clean the substrate surface. It was cleaned. Next, the temperature is lowered until the substrate temperature reaches a predetermined temperature (for example, 400 ° C.), and then a trimethyl aluminum (TMAl) gas and an ammonia (NH ₃ ) gas are supplied in a hydrogen atmosphere, so that A buffer layer 7 of about several tens of nm was deposited. Then, the substrate 4 is heated to 1000 ° C.
Then, a trimethylgallium (TMGa) gas and an ammonia (NH ₃ ) gas are supplied in a hydrogen atmosphere, and GaN, which is a group III nitride layer, is formed on the buffer layer 7.
When the layer 8 was grown by 6 μm, a cross-sectional structure as shown in FIG. 2A was obtained.

Next, the substrate 4 on which the GaN layer 8 has been grown is taken out of the reaction furnace of the atmospheric pressure organometallic compound vapor phase epitaxy apparatus 1, and [1] on the surface of the GaN layer 8 is subjected to photolithography.
In the 1-20] direction, stripe-shaped resist patterns 9 having a width of 4 μm were formed at 1 mm intervals as shown in FIG. 2B. After development, a Ti film 10 and a Ni film 11 were sequentially deposited on the GaN layer 8 on which the stripe-shaped resist pattern 9 was formed, as shown in FIG. Next, the stripe-shaped resist pattern 9 was removed by lift-off to produce a mask 12 as shown in FIG. Subsequently, Ga is applied by reactive etching.
The N layer 8 was processed into the shape shown in FIG. After that, the Ti film 10 and the Ni film 11 constituting the mask 12 were removed. As a result, as shown in FIG.
A step structure (in this case, a rectangular stripe groove) 13 having a width of 3.5 μm and a depth of 4 m was formed on the surface of. G of substrate 4
The step structure 13 processed into the aN layer 8 became as shown in the cross-sectional scanning electron microscope image of FIG.

Next, the substrate 4 after the step structure 13 has been formed on the GaN layer 8 is sufficiently washed, and then put again in the reaction furnace of the atmospheric pressure organometallic compound vapor phase epitaxy apparatus 1 so that the substrate temperature is reduced to 6.
Heating was performed to a predetermined temperature within the temperature range of 00 to 1300 ° C. (in this case, 1000 ° C.), and this state was maintained for 7 minutes. During this period (from the start of heating to the time point when the temperature was lowered to 400 ° C. after the heat treatment), nitrogen gas was supplied as a carrier gas, and ammonia was supplied as a group V source. As a result, despite the fact that TMGa gas as a group III source was not supplied at all, FIG.
As shown in (g), the inside of the step structure 13 is formed by the GaN layer 8.
Was almost completely buried by some of the substances 14 forming the.

The buried portion of the substance 14 in the above-described step structure 13 is formed by a process in which GaN on the crystal surface is once thermally decomposed and Ga atoms or GaN are diffused to the crystal surface or in the vicinity of the crystal surface. It is considered that this was caused by re-incorporation into the solid at a portion where the surface energy of the crystal surface was low and recombination. The crystal surface of the buried portion is formed by a lattice plane such as a (1-101) plane, and each plane is extremely flat. Such a phenomenon in which a substance moves has been reported for other III-V compound semiconductors (for example, ZL
40 (7) April 1, 1982) by Liau et al.) Is called the mass transport phenomenon. However, mass transport phenomena related to group III nitride semiconductors have not been reported to date.

Various conditions affecting the mass transport phenomenon include the following. The basic concept is
The crystal has a stable plane based on the crystal structure, and it is generally considered that the smaller the number of dangling bonds between atoms in the lattice plane, the more stable. Therefore, even during crystal growth due to the mass transport phenomenon, there is a high possibility that the crystal will grow in the direction in which the most stable plane is formed. For example, in the case of hexagonal GaN, a surface closer to the (0001) plane is more stable.

The growth rate of the substance varies depending on the temperature of the substrate heat treatment, the pressure in the growth furnace, the orientation of the growth surface, the supply amount and the supply ratio of the substance supplied during the heat treatment, and the like. For example, as the heating temperature of the substrate increases and the growth surface moves from the stable surface to the unstable surface, the supply ratio of the V source and the III source when the V source and the III source are supplied is V / III.
It is considered that the growth rate increases as the value increases. The growth state of the substance (growth position and degree of embedding) changes according to the pressure inside the growth furnace and the shape and position of the step structure, and the growth state of the substance (degree of progress of the growth of the substance)
Changes so that the growth progresses as the heat treatment time of the substrate becomes longer. Further, the composition and crystal quality of the group III nitride layer after the material growth varies depending on the heat treatment temperature of the substrate, the pressure in the growth furnace, the supply amount and the supply ratio of the material supplied during the heat treatment, and the like. In summary, by appropriately adjusting the above conditions, it is possible to produce a group III nitride layer in which the desired shape and composition are controlled and the threading low dislocation density is reduced as described later.

When the substrate 4 is heated at 1000 ° C. as described above, a large number of threading dislocations 15 are formed near the bottom surface of the step structure 13 in the GaN layer 8 due to a difference in lattice constant from the sapphire substrate 4. The substance 1 in the step structure 13 is
The number of threading dislocations 15 formed at a portion near the surface of the buried portion 4 is significantly smaller than the number of threading dislocations 15 formed at a portion around the step structure 13. Therefore, a low dislocation density region 16 is formed in a portion near the surface of the material buried portion in the step structure 13. The decrease in the threading dislocations is caused by the fact that the material grows in the lateral direction of the GaN layer 8 (the direction parallel to the substrate surface) due to the mass transport phenomenon, and the direction of the threading dislocations is bent by the rearrangement of surface atoms. I do.

Here, how threading dislocations are formed will be described by comparing the method of manufacturing a semiconductor of the present embodiment utilizing the mass transport phenomenon with a conventional technique. When a substance (crystal) is grown using the conventional ELO technique or the buried regrowth technique, the substance also grows in the vertical direction (the direction perpendicular to the substrate surface).
The dislocation proceeds obliquely along the growth direction as shown in FIG.

On the other hand, in the semiconductor manufacturing method of the present embodiment utilizing the mass transport phenomenon,
(A), as shown by the arrow B, it grows only in the horizontal direction, and in principle, the material does not grow in the vertical direction. Therefore, the dislocations 15 are directed in the horizontal or downward direction as shown. Therefore, the low dislocation density region 1 can be more efficiently
6 can be obtained. Further, in the semiconductor manufacturing technique of the present embodiment, since different materials such as a dielectric film are not embedded, crystallinity does not deteriorate due to impurities. The substrate 4 on which the step structure 13 is formed as described above is
When heat-treated at ° C, the threading dislocation density is 10 ⁶ c
m ^-2 or less.

According to the above method, the substance 1 is placed in the step structure 13.
4 is buried, a group III source is supplied, and normal vertical crystal regrowth as shown by arrow C is performed to obtain a GaN crystal 1.
As a result, a low dislocation density region similar to that described above grew in the upper region of the step structure 13. The phenomenon that such a low dislocation density region grows is caused by AlGaN, GaInN,
It was also confirmed in a group III nitride semiconductor mixed crystal such as AlInN and AlGaInN.

In the semiconductor manufacturing method of the present embodiment,
The effect of improving crystallinity by forming a low dislocation density region,
The effect of controlling the composition of the group III nitride layer to a desired one is as follows.
As described above, the same applies not only to the case where the cross-sectional shape of the step structure 13 is rectangular, but also to the case where the cross-sectional shape of the step structure is V-shaped, mesa-shaped, inverted mesa-shaped, round-shaped groove or stripe. I confirmed that In the semiconductor manufacturing method of the present embodiment, the effect of improving the crystallinity by forming the low dislocation density region and the effect of controlling the composition of the group III nitride layer to a desired one can be obtained by changing the orientation of the step structure. 5 °, 10 ° from [11-2] direction to [1-100] direction, respectively.
°, 15 °, 20 °, 25 °, and 30 ° were confirmed to be obtained similarly. In the semiconductor manufacturing method of the present embodiment, the effect of improving the crystallinity by forming the low dislocation density region and the effect of controlling the composition of the group III nitride layer to a desired one are obtained by the growth furnace during heating. Pressure within 0, 100, 250, 500, 760, 1000
(Torr), it was confirmed that the same could be obtained. Further, in the semiconductor manufacturing method of the present embodiment, the effect of improving the crystallinity by forming the low dislocation density region and the effect of controlling the composition of the group III nitride layer to a desired one are achieved by the width of the step structure and One of the depths is 0.1 μm, 0.
5 μm, 1 μm, 3 μm, 5 μm, 10 μm and the ratio of the width and depth of the step structure to 1/100, 1 /
10, 1/5, 1/2, 1/1, 2/1, 5/1, 10
/ 1, 100/1, it was confirmed that the same was obtained.

In the method of manufacturing a semiconductor according to the first embodiment, the substrate (in this case, a sapphire substrate) is used.
Although the buffer layer 7 is interposed on 4, the buffer layer 7 can be omitted. In that case, as shown in FIG.
A modification may be made so that the group III nitride layer 22 is directly laminated on the substrate (for example, a GaN substrate) 21, and the other portions may be manufactured in the same manner as described above.

By the way, the binary GaN for improving the crystallinity and producing a group III nitride layer controlled to a desired composition by the above-described semiconductor manufacturing method of the first embodiment is formed.
The following quantum wire structure can be manufactured by performing the following additional material supply during the heat treatment. That is, as described above, the GaN layer 8 is supplied while supplying nitrogen gas and ammonia as a group V source.
While the substrate 4 on which the step structure 13 has been processed is heated at 1000 ° C. for 7 minutes, TMIn is used as a group III source at predetermined time intervals (eg, 3 minutes) for a predetermined time (eg, 1 minute).
As a result, a ternary mixed crystal GaInN region as shown in FIG. 5A was formed, and this region showed good characteristics as a quantum wire. Such a quantum wire was uniformly formed in a size small enough for the quantum effect to appear. The formation of such quantum wires is realized by utilizing the mass transport phenomenon in the present embodiment. In the case of a general quantum wire, as shown in FIG. 5B, the size of the ternary mixed crystal GaInN is larger than that of the quantum wire of the present embodiment.

According to the semiconductor manufacturing method of the present embodiment,
Conventionally, a high-purity low-dislocation-density region, which has been difficult with a group III nitride semiconductor, can be manufactured by a relatively simple manufacturing process. Further, simultaneously with the formation of the high-purity low-dislocation-density region, it is also possible to produce a quantum wire small and uniform enough to exhibit a quantum effect.

Further, the semiconductor device structure actually manufactured by using the method of manufacturing a semiconductor utilizing the mass transport phenomenon of the present embodiment has a structure in which regions having different physical properties are formed in a direction parallel to the substrate surface. Since it has a low dislocation density layer and quantum wires, as described below, it has better characteristics than the conventional one. In the laser diode manufactured by the method for manufacturing a semiconductor according to the present embodiment, the life was greatly extended, and continuous oscillation became possible. Further, in the light emitting diode manufactured by the method for manufacturing a semiconductor according to the present embodiment, the light output of the blue light emitting diode and the green light emitting diode is several times as large as the conventional one. Also,
In the light receiving element manufactured by the semiconductor manufacturing method of the present embodiment, a photodiode, an FET type light receiving element,
In all of the BT type light receiving elements, the dark current decreased by three digits or more. Furthermore, the electronic device fabricated by the method of semiconductor manufacturing this embodiment, the amplification degree of the HBT will increase to several times that of the conventional, f _max of the FET exceeds 100 GHz.

The semiconductor manufacturing method of the present embodiment can be applied to a semiconductor light emitting device, a semiconductor ultraviolet light detector, a semiconductor voltage amplifier, a semiconductor current amplifier and the like.
Using a group I nitride semiconductor, a light-emitting element that emits light in the ultraviolet region and the visible short wavelength region to the infrared region, or an ultraviolet detector that detects only specific ultraviolet light,
A field-effect transistor or heterojunction bipolar transistor that amplifies high-power microwaves can be realized.

[0044] Incidentally, in the method of semiconductor manufacturing the first embodiment, GaN is used as the III-nitride layer, instead of the general _{formula; B x Al y In z Ga} 1-xyz N ( where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1) A group III nitride semiconductor material containing at least nitrogen and a group III element may be used. Further, in the method of manufacturing a semiconductor according to the first embodiment, 4 mm from the start of heating the substrate 4.
Until the temperature was lowered to 00 ° C., both the carrier gas and the group V source as the predetermined substances were supplied to the substrate surface.
Either one may be supplied. At that time,
Although the nitrogen gas is used as the carrier gas, a hydrogen gas, another inert gas such as helium, argon, or a mixed gas of two or more gases may be used instead. Further, although ammonia was used as the group V source, other compounds containing nitrogen may be used instead. Also,
In the method for manufacturing a semiconductor according to the first embodiment, the G
Step structure 1 having a width of 3.5 μm and a depth of 4 m on the surface of aN layer 8
3 was formed, but the depth of the step structure was changed to change the substrate 4
May be exposed.

In the method of manufacturing a semiconductor according to the first embodiment, when the substrate 4 is heated, a group III source of a group III element constituting the group III nitride layer, or a group III source constituting the group III nitride layer is formed. A group III source of a group III element different from the element may be supplied. When such a group III source is supplied, the group III nitride layer serving as the base material contains
By supplying a Group I source or a Group III source not included, the composition of the Group III nitride layer in the buried portion can be controlled.

In the method of manufacturing a semiconductor according to the first embodiment, when the group III nitride layer is made of ternary mixed crystal GaInN, when the substrate 4 is heated, one of the group III elements constituting GaInN is formed. Three Group III sources (In)
Two or more Group III sources among the Group III elements constituting nN may be supplied. When such a group III source is supplied, the ternary mixed crystal GaI
The composition of nN can be controlled. When the base material is a mixed crystal, the composition ratio (group III ratio) is determined by conditions such as the heat treatment temperature of the substrate 4 and the supply ratio between the group V source or the group III source and the group III source. However, the composition may be different from that of the base material even if the group III source is not supplied. For example, when the base material is Ga _0.80 In _0.20 N, the buried portion is Ga _0.90 In _0.10 N, or the base material is B _0.05 Al _0.05
In the case of In _0.10 Ga _0.80 N, the buried portion is Al _0.10 In.
_0.05 Ga _0.85 N.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) are diagrams illustrating the configuration of a normal pressure organometallic compound vapor phase growth apparatus used for carrying out a semiconductor manufacturing method according to a first embodiment of the present invention, and FIGS.
It is A sectional drawing.

FIGS. 2A to 2G are diagrams for explaining a semiconductor manufacturing method according to the first embodiment for each process;

FIG. 3 is a cross-sectional scanning electron microscope image of a stepped structure processed into a GaN layer on a substrate by the semiconductor manufacturing method according to the first embodiment.

FIGS. 4A and 4B are schematic cross-sectional views for explaining lateral growth of a substance in a buried portion using a mass transport phenomenon in the method of manufacturing a semiconductor according to the first embodiment; .

5A is a schematic cross-sectional view of a quantum wire manufactured by a semiconductor manufacturing method according to the first embodiment, and FIG. 5B is a schematic cross-sectional view of a quantum wire manufactured by a conventional semiconductor manufacturing method. .

FIG. 6 is a schematic cross-sectional view for explaining the growth of a substance in a buried portion in a conventional manufacturing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Atmospheric pressure organometallic compound vapor phase growth apparatus 2 Source gas supply unit 2-1 to 2-4 Gas supply unit 3 Susceptor 4,21 Substrate 5 Reaction tube 6 Exhaust system 7 Buffer layer (AlN layer) 8 Group III nitride layer (GaN layer) 9 Striped resist pattern 10 Ti film 11 Ni film 12 Mask 13 Step structure (square stripe groove) 14 Material 15 Threading dislocation 16 Low dislocation density region 17 GaN crystal 22 Group III nitride layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 31/10 H01L 31/10 A 5F102 33/00 E H01S 5/323 (72) Inventor Hiroshi Amano Aichi 2-104 Yamanote, Nato-ku, Nagoya-shi Takara Mansion Yamanote 508 (72) Inventor Red ▲ Saki ▼ Isa 1-1, 38-805, Nishi-ku, Nagoya-shi, Aichi F-term (reference) 5F003 AP00 AZ03 BF06 BM03 BP32 BP33 BZ03 5F041 AA40 CA34 CA40 CA64 CA67 CA99 5F045 AA04 AB09 AB14 AB17 AB18 AB19 AC08 AC12 AC15 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AE29 AE30 AF09 AF13 AF20 BB12 BB16 CA02 CA10 CA12 DA53 DA56 DP07 EB15 EE14 5F049 MA02 MA18 PA07 PA07 CB05 CB07 DA05 DA25 EA29 5F102 FA02 GB01 GC01 GD01 GJ04 GJ10 GK04 GL04 GR01 HC00 HC01 HC02

Claims (10)

[Claims] 1. A method of manufacturing a group III nitride semiconductor, comprising: stacking a group III nitride layer on a substrate; and forming a step structure in the group III nitride layer. The substrate with the step structure formed thereon is 600 to 1300
Heating at a temperature of ° C and supplying a predetermined substance during the heating, thereby causing a mass transport phenomenon in which a part of the substance forming the group III nitride layer is moved into the step structure. A method for manufacturing a semiconductor, comprising: 2. A semiconductor manufacturing method for manufacturing a group III nitride semiconductor, comprising: stacking a buffer layer made of a nitrogen compound on a substrate; and stacking a group III nitride layer on the buffer layer. Forming a step structure in the group III nitride layer;
Heating at a temperature of ° C and supplying a predetermined substance during the heating, thereby causing a mass transport phenomenon in which a part of the substance forming the group III nitride layer is moved into the step structure. A method for manufacturing a semiconductor, comprising: Wherein said III-nitride layer has the general formula _{B x Al y In z Ga 1} -xyz N ( However, 0 ≦ x ≦
1,0 ≦ y ≦ 1,0 ≦ z ≦ 1) containing at least nitrogen and a group III element
3. The method of manufacturing a semiconductor according to claim 1, wherein the semiconductor is made of a group III nitride semiconductor material. 4. A method of supplying one or both of a carrier gas and a group V source as the predetermined substance from the start of the heating to the time when the temperature is lowered to a predetermined temperature of less than 600 ° C. A method for manufacturing a semiconductor according to claim 1. 5. The carrier gas may be any one of hydrogen gas, nitrogen gas and another inert gas.
5. A gas mixture comprising at least one gas, wherein the group V source is a compound containing nitrogen such as ammonia.
The manufacturing method of the semiconductor of the description. 6. The semiconductor device according to claim 1, wherein a group III source of a group III element constituting said group III nitride layer is supplied when said substrate is heated. Production method. 7. The method according to claim 1, wherein a group III source of a group III element different from the group III element constituting the group III nitride layer is supplied when the substrate is heated. 2. The method for manufacturing a semiconductor according to claim 1. 8. When the group III nitride layer is a mixed crystal,
When the substrate is heated, the group III nitride layer
The method according to any one of claims 1 to 5, wherein one or two or more Group III sources of the Group I elements are supplied. 9. The growth rate and the growth state of a substance grown by the mass transport phenomenon, and the composition and crystal quality of the group III nitride layer after the substance growth, the growth plane orientation, substrate heating temperature, substrate heating time, growth The method according to claim 1, wherein the control is performed by adjusting a pressure in the furnace, a step shape, and a supply amount of the predetermined substance.
13. The method for producing a semiconductor according to the above item. 10. A semiconductor device manufactured by the method of manufacturing a semiconductor according to claim 1, wherein regions having different physical properties are formed in a direction parallel to a substrate surface. , Light emitting diode, photodiode, FET light receiving element, HBT light receiving element, FET,
A semiconductor device, which is any one semiconductor device of HBT or two or more integrated devices.