JP2001057086A - Non-volatile semiconductor memory device and storage medium stored with program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the rewriting of stored information by reducing the control circuit scale of a fuse cell and shortening the setting time of the fuse cell in a non-volatile semiconductor memory device having the fuse cells consisting of an electrically rewritable non-volatile semiconductor memory element. SOLUTION: This device is provided with a fuse cell 101, a sense circuit 12 detecting the threshold level of the fuse cell, a gate driver 103 driving the gate terminal of the fuse cell, a read-out voltage generating circuit 104 generating the read-out voltage of the fuse cell and transmitting it to the gate driver, and a fuse erasing circuit 105 reducing the threshold level of the fuse cell. When an erasing flag in a main memory area erasion and activation control circuit 106 is established, it is judged whether erasing operation of a main memory area 108 is performed in accordance with stored information of the fuse cell or not, a main memory region erasion and activation signal is outputted, and a main memory region erasing circuit 107 erases the main memory area 108 in accordance with this signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a fuse cell composed of an electrically rewritable nonvolatile semiconductor memory element and a storage medium storing a program used therein.

[0002]

2. Description of the Related Art In a conventional nonvolatile semiconductor memory device, a fuse cell using an electrically rewritable nonvolatile semiconductor memory element is provided. This fuse cell is provided for the purpose of storing redundancy switching information and product function switching information.

FIG. 6 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device having a fuse cell. Here, the configuration of the circuit for determining the storage information of the fuse cell,
The storage information of the fuse cell is used for switching the function between shipping the nonvolatile semiconductor memory device as an “electrically erasable and erasable product” or shipping as an “electrically writable and erasable product”. The configuration in the case is shown.

[0006] In FIG. 6, a fuse cell 601 is made of an electrically rewritable nonvolatile semiconductor memory element, and holds a difference as to whether its own threshold level is high or low as storage information. The sense circuit 602 is connected to the fuse cell 601, detects whether the threshold level of the fuse cell 601 is high (off cell) or low (on cell), and outputs information stored in the fuse cell 601. The gate driver 603 includes a fuse cell 601.
The gate terminal of the fuse cell 601 is driven by the power supply voltage VCC when reading the fuse cell 601.

The fuse writing circuit 604 is connected to the fuse cell 601 and has a function of increasing the threshold level of the fuse cell 601. Fuse erase circuit 605
Is connected to the fuse cell 601, and the fuse cell 60
It has a function of lowering the threshold level of 1.

Main memory area erase activation control circuit 606
Is connected to the sense circuit 602 and the main memory area 6
When the erase flag for erasing 08 is established, it is determined whether or not the erase operation is to be started according to the information stored in the fuse cell 601, and the main memory area erase activation signal is established. The main memory area erasing circuit 607 performs an erasing operation of the main memory area 608 in response to the main memory area erasing activation signal.

FIG. 7 is a diagram showing the relationship between the threshold level of the fuse cell 601 and the voltage level applied to the gate terminal of the fuse cell 601 at the time of reading. Fuse cell 601 has a threshold level of initial threshold level Vthinit (about 3 V) after diffusion.

Conventionally, when the power supply voltage VCC is 5 V, by applying the power supply voltage VCC to the gate terminal of the fuse cell 601, the fuse cell having the initial threshold level can be reliably turned on. However, since the power supply voltage VCC has been reduced to 2 to 4 V in recent years, even if the power supply voltage VCC is applied to the gate terminal of the fuse cell 601, the initial threshold level Vthinit
It is no longer possible to reliably turn on or off cells the fuse cell 601 having.

Therefore, first, an erase operation is performed on fuse cell 601 using fuse erase circuit 605 to lower the threshold level to about 1 V, and this threshold level is set to default threshold level Vthdef. When the threshold level of the fuse cell 601 is the default threshold level Vthdef, the gate driver 60
2 to 4 V to the gate terminal of the fuse cell 601
When the power supply voltage VCC is applied, the fuse cell 601 is turned on, and at this time, the sense circuit 602 outputs "High" information.

When the fuse storage information is changed, the fuse write circuit 604 is applied to the fuse cell 601.
, The threshold level is raised to about 5 V, and this threshold level is set to a threshold level Vthtrim after trimming. When the power supply voltage VCC is applied to the gate terminal of the fuse cell 601 when the threshold level of the fuse cell 601 is the above-trimmed threshold level Vthtrim, the fuse cell 601 is turned off. At this time, the sense circuit 602 becomes “Low”. Output information.

When an erasing operation is performed on main memory area 608, main memory area erasing activation control circuit 60
6 when the erase flag is established.
2 is confirmed, if the sense circuit 602 has output "High" information, the main memory area erasure activation signal is established, and if the "Low" information is output, it is not established.

In response to the establishment of the main memory area erasing activation signal, control is performed such that the main memory area erasing circuit 607 is activated and the erasing operation of the main memory area 608 is started.

As described above, the fuse cell 601 is first turned on using the fuse erase circuit 605 to turn on the fuse cell 601 having the initial threshold level (default threshold level Vthdef). This makes it possible to test the main memory area 608 as an electrically writable and erasable area in the process immediately before shipment.

Therefore, when this nonvolatile semiconductor memory device is shipped as a product that can be electrically written and erased, it is shipped as it is. Further, when the product is shipped as a product in which electrical writing can be performed only once, the fuse cell 601 is turned off using the writing circuit 604 (the threshold level Vthtrim after trimming), and the main memory area erasing circuit 607 is not activated. After the state, it was taking the procedure of shipping.

[0015]

However, the above-mentioned prior art has the following problems. The first problem is that the control circuit for setting the fuse cell becomes large-scale. The reason is that it is not possible to easily determine whether the fuse cell having the diffusion rise threshold Vthinit is an on cell or an off cell, so that the threshold level of the fuse cell must be completely turned on. This is because both an erase circuit and a write circuit for completely turning off cells are required.

The second problem is that it takes time to set a fuse cell. The reason is that it is not possible to easily determine whether the fuse cell having the diffusion rise threshold value Vthinit is an on-cell or an off-cell, so that the fuse cell reaches a default threshold level at which it can be completely determined to be an on-cell. This is because a step of once erasing the cell is required.

A third problem is that, when the storage information of the fuse cell is used as described above, the fuse data is written back after shipment by analyzing a test method for erasing the fuse cell. This is a problem in safety measures that information stored in the main memory area can be rewritten. The reason is that the semiconductor device has both a write circuit and an erase circuit for controlling a threshold level of a fuse cell as a test function in a factory.

Accordingly, the present invention provides a nonvolatile semiconductor memory device which can solve the above problems.

[0019]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises a fuse cell comprising an electrically erasable nonvolatile semiconductor memory element, and a fuse cell threshold. Sensing means for detecting a value level to determine whether a fuse cell is an on cell or an off cell; a gate driver means for driving a gate terminal of the fuse cell; and a gate driver means for applying a voltage to the gate terminal when reading the fuse cell. Read voltage generating means for generating a read voltage to be read, and fuse cell erasing means for erasing a fuse cell and lowering the threshold level of the fuse cell. When the cell has an initial threshold level indicating immediately after diffusion, the fuse cell is Scan means is characterized in that a voltage can be determined as an OFF cell.

Further, in another nonvolatile semiconductor memory device according to the present invention, a fuse cell using an electrically erasable nonvolatile semiconductor memory element and a fuse cell detecting a threshold level of the fuse cell are used. Sensing means for determining whether the cell is an on-cell or off-cell, gate driver means for driving a gate terminal of the fuse cell, and read-out which is connected to a digit line of the fuse cell and supplies current from a power supply voltage when reading the fuse cell Current source means; and fuse cell erasing means for erasing the fuse cell and lowering the threshold level of the fuse cell. The amount of current output from the current source means at the time of reading has an initial threshold level. The fuse cell is set to a current amount by which the sensing means can be determined as an off cell. That.

Further, in the storage medium according to the present invention, it is determined whether the fuse cell is an ON cell or an OFF cell by detecting a threshold level of a fuse cell composed of an electrically erasable nonvolatile semiconductor memory element. And a driving process for driving the gate terminal of the fuse cell;
A read voltage generation process for generating a read voltage to be applied to the gate terminal by a driving process when reading the fuse cell, and a fuse cell erasing process for erasing the fuse cell and lowering the threshold level of the fuse cell. A read voltage generated by storing a program and generating a read voltage is a voltage that can determine that the fuse cell is an off-cell when the fuse cell has an initial threshold level immediately after diffusion. And

Further, another storage medium according to the present invention detects the threshold level of a fuse cell using an electrically erasable nonvolatile semiconductor memory element and determines whether the fuse cell is an on cell or an off cell. A determination process of determining whether the fuse cell is driven, a drive process of driving the gate terminal of the fuse cell, a current supply process connected to the digit line of the fuse cell and supplying a current from the power supply voltage when reading the fuse cell, and erasing the fuse cell. A program for executing a fuse cell erasing process having a function of lowering the threshold level of the fuse cell is stored, and the amount of current supplied by the current supply process has an initial threshold level indicating immediately after diffusion. The fuse cell is set to an amount of current that can be determined to be an off cell in the determination process.

Further, in the nonvolatile semiconductor memory device and the storage medium, erasing of the main memory area may be controlled according to the judgment.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device having a fuse cell according to a first embodiment of the present invention. Here, the configuration of the circuit for determining the storage information of the fuse cell and the non-volatile semiconductor memory device are shipped as "products that can be written and erased electrically" or as "products that can be written only once". The configuration in the case of using the storage information of the fuse cell for the function switching of whether to perform the function is shown.

Referring to FIG. 1, a nonvolatile semiconductor memory device according to the present embodiment includes a fuse cell 101 composed of an electrically rewritable nonvolatile semiconductor memory element and a threshold voltage of fuse cell 101 connected to fuse cell 101. A sense circuit 102 for detecting an on-cell or an off-cell by detecting a level, and a gate driver 10 connected to the fuse cell 101 and driving a gate terminal of the fuse cell 101
3 and a read voltage generating circuit 104 which is connected to the gate driver 103 and generates a read voltage VFUSEREAD when reading a fuse cell and transmits the read voltage VFUSEREAD to the gate driver 103.
And the fuse cell 101 connected to the fuse cell 101.
And a fuse erase circuit 105 for electrically erasing (reducing the threshold level).

When the erase flag for erasing the main memory area 108 connected to the sense circuit 102 is established, the main memory area erase activation control circuit 106 responds to the information stored in the fuse cell 101 by the main memory area 108. It is determined whether or not to start the erase operation of the main memory area, and a main memory area erase activation signal is output.

The main memory area erasing circuit 107 performs an erasing operation of the main memory area 108 in response to the main memory area erasing activation signal.

FIG. 2 is a block diagram showing a configuration example of the read voltage generation circuit 104. Read voltage generation circuit 10
4 is a VCC level detection circuit 201, an output level control logic circuit 202, a Pch MOS transistor 203 and an NchM
It comprises an OS transistor 204.

The VCC level detecting circuit 201 detects the power supply voltage V
When the level of CC is high, that is, the power supply voltage V is applied to the gate terminal of the fuse cell 101 having the initial threshold level.
When the level of the sense circuit 102 cannot be detected as an off cell even when CC is applied, the output signal CHKVCC is set to “High”. Conversely, when the level of the power supply voltage VCC is low, “Low” is set.
".

The output level control logic circuit 202 determines that the fuse cell read activation signal TFREAD is "High"
Except when the KVCC signal is in the "High" condition, "Low" data is output, and when the above conditions are met, "High" data is output. Thereby, the gate voltage VFU at the time of reading is obtained.
When the output of the output level control logic white stage 202 is “High”, “VCC-α” is given to SEREAD and “Low”
In the case of, "VCC" is given.

Next, the operation will be described. As shown in FIG. 3, the fuse cell 101 has Vthinit (3
V). Therefore,
When reading the fuse cell 101, a read voltage VFUSEREAD (about 2 V in FIG. 3) is generated by the read voltage generation circuit 104 and applied to the gate terminal of the fuse cell 101 via the gate driver 103. Then, the sense circuit 102 detects that the fuse cell 101 is an off-cell and outputs “High” information.

When the fuse storage information is changed, the fuse cell 101 is erased by using the fuse erase circuit 105 so that the voltage VFUSEREAD is changed to the fuse cell 10.
Threshold level V that turns on even when applied to gate terminal 1
The threshold value is reduced to thtrim (about 0 to 1 V in FIG. 3). Thus, when reading of the fuse cell 101 is performed, the fuse cell 101 outputs “Low” information via the sense circuit 102.

Main memory area erase activation control circuit 106
Controls whether or not an erasing operation can be performed on the main memory area 108 according to the determination result of the sense circuit 102. That is, when the erase flag is established, the sense circuit 102
When the threshold level of the fuse cell 101 is the initial threshold level Vthinit, that is, when the “High” information is being output, the main memory area erase activation signal is established and the erase operation for the main memory area 108 is performed. Allow

When the threshold level of the fuse cell 101 is the trimmed threshold level Vthtrim, that is, when the sense circuit 102 is outputting "Low" information, the sense circuit 102 outputs the main memory area erase activation signal. The control is performed to prohibit the erasing operation for the main memory area 101 without being established.

As described above, in the present embodiment, when the fuse cell 101 has an initial threshold level that is increased by diffusion, the read voltage generation circuit 1
When the read voltage VFUSEREAD generated in step 04 is applied to the gate terminal of the fuse cell 101 via the gate driver 103, the sense circuit 102
Is determined to be an off-cell. When the fuse storage information is changed, the fuse cell 101 is erased by the fuse erase circuit 105 and the threshold level is lowered, so that the sense circuit 102 determines that the fuse cell 101 is an on cell.

Therefore, according to the present embodiment, the fuse cell is always erased in the test process for the purpose of setting the default threshold level, and writing is performed only when the storage information is changed, as in the conventional example. Since it is not necessary to set complicated fuse storage information and it is possible to control the on / off switching of the fuse storage information only by the erase operation,
There is an advantage that the complexity of the fuse information setting control circuit and the complexity of the fuse information setting procedure can be eliminated.

Further, as a method of reading a fuse cell having an initial threshold level, a high voltage capable of determining that the sense circuit is an ON cell is applied to the gate terminal of the fuse cell at the time of reading, and the threshold voltage is used to change stored information. Although it is conceivable to provide only a means for increasing the value, as the power supply voltage becomes lower, the voltage for driving the gate terminal of the fuse cell at the time of reading is increased from the power supply voltage by a charge pump. A circuit such as a circuit or a boost circuit that requires a huge boosting capacity is required, and there is a problem that a control circuit for setting a fuse cell becomes large. For this reason, this embodiment employs means for lowering the level applied to the gate terminal of the fuse cell from the power supply voltage.

FIG. 4 is a block diagram showing a configuration of a nonvolatile semiconductor memory device having a fuse cell according to a second embodiment of the present invention. Here, the configuration of the circuit for determining the storage information of the fuse cell and the non-volatile semiconductor storage device are shipped as “products that can be written and erased electrically” or “products that can be written only once”
The configuration in the case where the storage information of the fuse cell is used for the function switching of whether or not to be shipped.

As compared with the first embodiment, the means for reading out a fuse cell having an initial threshold level as an off-cell is different. In the first embodiment,
Although a means for controlling the voltage applied to the gate terminal of the fuse cell when reading the fuse cell is provided, in this embodiment, the voltage applied to the gate terminal is kept at the power supply voltage VCC, and The same effect is sometimes obtained by providing a means for supplying a current to the digit line DIGFUSE of the fuse cell.

Referring to FIG. 4, a nonvolatile semiconductor memory device according to the present embodiment has a fuse cell 401 composed of an electrically rewritable nonvolatile semiconductor memory element, and a threshold voltage of fuse cell 401 connected to fuse cell 401. A sense circuit 402 for detecting an on cell or an off cell by detecting a level, a gate driver 403 connected to the fuse cell 401 and driving the gate terminal of the fuse cell 401 with the power supply voltage VCC, and a fuse circuit 401 connected to the fuse cell 401 and connected to the fuse cell 401. A fuse erase circuit 404 for electrically erasing (lowering the threshold level); a read current source 408 which is activated when reading the fuse cell and supplies a current from VCC to the digit line DIGFUSE of the fuse cell; Is provided.

The main memory area erasure activation control circuit 405 is connected to the sense circuit 402 and determines whether or not to start the erasure operation on the main memory area 407 according to the storage information of the fuse cell 401 when the erasure flag is established. And outputs a main memory area erase activation signal.

The main memory area erasing circuit 406 receives the main memory area erasing activation signal and performs an erasing operation of the main memory area 407.

FIG. 5 is a circuit diagram showing a configuration example of the current source 408 at the time of reading in this embodiment. The read-time current source 408 includes a PchMOS transistor 501 and an Nch
It is composed of MOS transistors 502-504.

The read-time current source 408 is activated when the fuse cell read activation signal TFREAD becomes "High", and when the power supply voltage VCC is at a high level, that is, the threshold voltage of the three Nch MOS transistors 502 to 504. When the level exceeds the level represented by the sum of the above, a current is supplied to the fuse cell digit line DIGFUSE. That is,
It detects that the power supply voltage VCC is at such a level that the fuse cell is turned on even when applied to the gate terminal of the fuse cell having the initial threshold level, and supplies a current to the fuse cell digit line DIGFUSE. Is performed.

Next, the operation will be described. The fuse cell 401 has a threshold level of Vthinit (about 3 V) after diffusion. When reading,
The gate terminal of the fuse cell 401 is driven by the gate driver 403 with the power supply voltage VCC.

When the power supply voltage VCC is 4 V, the fuse cell 401 having the initial threshold level Vthinit is turned on, and the difference between the threshold level Vthinit of the fuse cell 402 and the voltage VCC applied to the gate (△
Vth = 1V), the read-time current source 408 supplies a current set to be equal to the above-mentioned on-cell current from the power supply voltage VCC to the fuse cell digit line DIGFUS.
To flow toward E, the sense circuit 402 determines that the fuse cell 402 is an off cell in a pseudo manner and outputs “High” information.

When the fuse storage information is changed, the fuse cell 401 is erased using the fuse erase circuit 404, so that the power supply voltage VCC is changed to the fuse cell 401.
Threshold level Vthtrim (approximately 0 V) for determining that the sense circuit 402 is in an on-cell state even when applied to the gate terminal of
Lower the threshold level to Thereby, when reading of the fuse cell 401 is performed, the fuse cell 4
01 outputs “Low” information via the sense circuit 402.

Main memory area erase activation control circuit 405
Controls whether or not an erasing operation can be performed on the main memory area 407 according to the determination result of the sense circuit 402. That is, when the erase flag is established, the sense circuit 402
When the threshold level of the fuse cell is the initial threshold level Vthinit, that is, when “High” information is output, the main memory area erasing activation signal is established, and the erasing operation for the memory array area 407 is performed. To give permission.

When the threshold level of the fuse cell 401 is the trimmed threshold level Vthtrim, that is, when the sense circuit 402 is outputting "Low" information, the sense circuit 402 outputs the main memory area erase activation signal. The control is performed to prohibit the erase operation for the memory area 407 without being established.

Next, a storage medium according to the present invention will be described. The above-described operation according to each embodiment of FIGS.
It can be executed using a computer system including a PU and a memory. In that case, the memory storing the program for executing the above-described operation constitutes a storage medium according to the present invention.

As the storage medium, a semiconductor storage device,
A magneto-optical disk, an optical disk, a magnetic recording medium, or the like can be used. These storage media are ROM, RAM, C
It can be configured and used in a D-ROM, a magnetic tape, a magnetic card, a memory card, and the like.

[0052]

The first effect is that the control circuit for setting the fuse cell can be reduced. The reason is that the voltage VFUSERE that reliably determines a fuse cell having an initial threshold level that has increased diffusion as an off-cell.
A read operation is performed by inputting AD to the gate terminal of the fuse cell or keeping the voltage applied to the gate terminal at the power supply voltage VCC and supplying a current to the digit line DIGFUSE of the fuse cell at the time of reading.
This is because the threshold level of the fuse cell can be set only by the erasing means, and no means for writing the fuse cell is required.

A second effect is that the test time for setting a fuse cell can be reduced. The reason is that the voltage VFUSERE that reliably determines a fuse cell having an initial threshold level that has increased diffusion as an off-cell.
A read operation is performed by inputting AD to the gate terminal of the fuse cell or keeping the voltage applied to the gate terminal at the power supply voltage VCC and supplying a current to the digit line DIGFUSE of the fuse cell at the time of reading.
This is because the test time for setting the threshold level of the fuse cell to the default threshold level can be omitted.

The third effect is that the fuse cell information can be reliably rewritten after the fuse cell is set. The reason is that there is no means for writing a fuse cell. For this reason, the fuse cell is used to switch the function of whether the electrically erasable nonvolatile semiconductor memory device is shipped as an electrically erasable and erasable product, or whether it is shipped as an electrically erasable product. When using the stored information of
It is possible to prevent a product that has been shipped as a product that can be electrically written only once from being changed to a product that can be electrically rewritten.

Further, by providing erasure control means for controlling erasure of the main memory area in accordance with the judgment of the sense means, the above function can be switched using the storage information of the fuse cell.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration example of a read voltage generation circuit in FIG. 1;

FIG. 3 is a characteristic diagram illustrating an operation according to the first exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram showing a configuration example of a current source at the time of reading in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a characteristic diagram for explaining an operation of a conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

 101, 401 fuse cell 102, 402 sense circuit 103, 403 gate driver 104 read voltage generation circuit 105, 404 fuse erase circuit 106, 405 main memory erase activation control circuit 107, 406 main memory area erase circuit 108, 407 main memory area 408 Current source for reading

Claims (6)

[Claims] 1. A fuse cell comprising an electrically writable and erasable nonvolatile semiconductor memory element, and a threshold level of the fuse cell is detected to determine whether the fuse cell is an ON cell or an OFF cell. Sensing means; gate driver means for driving a gate terminal of the fuse cell; read voltage generation means for generating a read voltage applied to the gate terminal by the gate driver means when reading the fuse cell; A fuse cell erasing means for erasing and lowering a threshold level of the fuse cell, wherein a read voltage generated by the read voltage generating means is:
A nonvolatile semiconductor memory device characterized in that when the fuse cell has an initial threshold level indicating immediately after diffusion, the voltage of the fuse cell is such that the sensing means can be determined to be an off cell. 2. A fuse cell comprising an electrically writable and erasable nonvolatile semiconductor memory element, and a threshold level of the fuse cell is detected to determine whether the fuse cell is an ON cell or an OFF cell. Sensing means; gate driver means for driving a gate terminal of the fuse cell; read current source means connected to a digit line of the fuse cell for supplying a current based on a power supply voltage when reading the fuse cell; Fuse cell erasing means for erasing a cell and lowering a threshold level of the fuse cell, wherein a current amount output from the current source means at the time of reading the fuse cell having the initial threshold level Wherein the sensing means is set to an amount of current that can be determined as an off-cell. The semiconductor memory device. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising an erasing control unit for erasing a main memory area in accordance with a determination of said sensing unit. 4. A judging process for judging whether the fuse cell is an on-cell or an off-cell by detecting a threshold level of a fuse cell composed of an electrically erasable nonvolatile semiconductor memory element; A driving process for driving a gate terminal of the fuse cell, a read voltage generation process for generating a read voltage applied to the gate terminal by the driving process when reading the fuse cell, and a process for erasing the fuse cell and holding the fuse cell. A program for executing a fuse cell erasing process for lowering a threshold level is stored, and a read voltage generated by the read voltage generating process is used when the fuse cell has an initial threshold level indicating immediately after diffusion. A voltage at which the fuse means can determine that the sense means is an off-cell. Storage medium storing a program, characterized in that. 5. A determination process of detecting a threshold level of a fuse cell comprising an electrically erasable nonvolatile semiconductor memory element to determine whether the fuse cell is an ON cell or an OFF cell; A driving process for driving a gate terminal of the fuse cell; a current supply process connected to a digit line of the fuse cell for supplying a current based on a power supply voltage at the time of reading the fuse cell; and erasing the fuse cell to erase the fuse cell. A program for executing a fuse cell erasing process for lowering the threshold level of the memory cell is stored. The amount of current supplied by the current supply process is determined by determining whether a fuse cell having the initial threshold level is off-cell. A storage medium storing a program set to the amount of current that can be determined as 6. A storage medium storing a program according to claim 4, wherein a program for executing an erasure control process for erasing a main memory area in accordance with the determination in said determination process is stored.