JP2001054129A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a convergence correction circuit with less deterioration in correction accuracy when a video synchronizing frequency is increased. SOLUTION: The convergence correction circuit is provided with a generating circuit decision means 12, a coordinate conversion means 13 that outputs a horizontal coordinate (x) and a vertical coordinate (y) in matching with a display size and position, a waveform generating means 18 that outputs a convergence correction fundamental waveform, a shift quantity decision means 15 that outputs a circuit propagation delay amount, a delay means 23 that delays a correction fundamental waveform, a waveform generating means 19 that outputs a sine waveform, a waveform generating means 20 that outputs an attenuated waveform, a multiplier means 21, an adder means 22, a DAC 25 for a convergence correction waveform value, an AMP 28 that converts a current of CY coils 51, 52 into a voltage and provides an output of it, an ADC 27, a residual component detection means 17 that detects a residual noise component from the output denoting the current of the CY coils and the correction fundamental waveform component, and a waveform generation condition decision means 16 that eliminates the residual noise component.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence correction circuit for a display apparatus using a cathode ray tube (CRT), and more particularly to a digital convergence apparatus suitable for use in a convergence correction circuit of a multi-scan type direct-view display apparatus. About.

[0002]

2. Description of the Related Art A direct-view display device using a CRT is, for example, an in-line R (red) G (green) B
The electron guns for (blue) are arranged in a line, and the electron beam is scanned while changing the output level according to the signal level of each video signal. Further, the electron beam is scanned right and left and up and down (raster scan) by a magnetic field modulation by a deflection yoke provided on the CRT neck portion, and after passing through a shadow mask or an aperture grille, a portion of the portion having image information of the luminescent paint provided on the tube surface is provided. The desired image display is performed by irradiating the pixels.

In such a display device, the distance from the electron gun to the tube surface is not uniform between the respective tube surface positions due to the tube surface shape and the tube surface shape distortion, and the deflection yoke characteristics are not uniform. Of the RGB electron beam
Irradiation to the B phosphor becomes non-uniform on the tube surface, and if it is, color shift occurs.

Therefore, separately from the deflection yoke, a convergence yoke (hereinafter, referred to as a correction yoke) for correcting the positional relationship between the RGB electron beams.
(Referred to as CY) to realize accurate irradiation of each screen phosphor on the screen surface of the electron beam, thereby preventing color shift.

As a convergence correction process, for example,
A method using a CY having a six-pole structure has been conventionally used for products. This is achieved by arranging a 4H coil for vertical line correction (4H correction) for correcting the amount of horizontal deviation and a 4V coil for horizontal line correction (4V correction) for correcting the amount of vertical deviation. This is for correcting the amount of deviation between the electron beam and the B electron beam. In this case, it is realized by applying current values I (4H) and I (4V) only for correcting the deviation amount at each tube surface position from the coil sensitivity (CY sensitivity) determined by the applied current and the correction amount. Things.

Further, the present invention is realized by static convergence correction for correcting the entire screen according to the conditions for applying the correction current, and dynamic convergence correction for dividing the screen into small sections and performing optimum correction for each section. Further, the correction waveform shape corresponding to the correction amount is determined in advance, and is realized by reproducing for each correction.

An CY having an eight-pole structure is used to correct the amount of deviation between the G electron beam and the R electron beam and between the G electron beam and the B electron beam. This is achieved by increasing the number of poles of the above-described six-pole structure CY and correcting the vertical line (6H correction) to correct the horizontal deviation, and the horizontal line correction (6V correction) to correct the vertical deviation.
This is realized by:

Further, as an application to a product having the above-mentioned CY structure, a system is determined based on a balance between an allowable value of a deviation amount and a detrimental factor such as an amount of purity change and deterioration of sensitivity of a deflection yoke.

However, in order to respond to the sophistication of image processing applications as a display device in recent years, it is necessary to flexibly cope with a plurality of video frequencies and timing conditions with high definition, high image quality and a large screen by improving the corresponding video frequency. There is a demand for an improvement in image reproducibility by multi-scanning and further by flattening the tube surface. On the other hand, it goes without saying that cost reduction is an essential condition.

In addition, the above-mentioned corrected waveform shape may differ for each video frequency depending on the frequency characteristics and timing of the circuit, and it is necessary to store the corrected waveform shape for each corresponding video frequency in advance. In order to deal with problems such as the frequency characteristics of the circuit, and further, for high-definition, high-quality, flat-panel displays, the correction waveform shape becomes more complicated, and when only analog circuits are used, it is difficult to achieve cost and accuracy. there were.

From this, for example, Japanese Patent Application Laid-Open No. 4-250
In the conventional digital convergence display described in Japanese Patent Publication No. 78, it is possible to reproduce a variety of corrected waveforms at low cost, and to realize highly accurate convergence correction. Here, this known example is described in RGB
Is a digital convergence correction processing method for a CRT projection display in which images from three CRTs are enlarged by a lens and displayed on a screen in a superimposed manner. It is equally applicable.

A conventional digital convergence correction method will be described with reference to FIG. The digital convergence correction circuit includes a PLL (Phase Locked Loop) circuit 61.
, A vertical retrace pulse signal input T62, a vertical address signal generation counter (VAD) 62, input selection switches 63 to 65, and an EEPROM (Electrically erasablean).
d Programmable Read Only Memory) 66, a microprocessor 67, a coordinate system conversion ROM 68, and a RAM.
69, a DA converter 70, an amplifier 71, a horizontal retrace pulse signal input terminal T61, and a vertical retrace pulse signal input terminal T62. The convergence correction circuit outputs a convergence correction signal to convergence yokes (CY) 51 and 52 of the CRT 45 for three-color projection.

The PLL circuit 61 has a phase detector (Δφ) 6
11, a voltage controlled oscillator (VCO) 612, and a horizontal address signal generation counter (HAD) 613.

The microprocessor 67 includes an address signal generator (GEN) 671 and an interpolator (VSI) 672 for vertical slope interpolation.

Horizontal address signal generation counter 613
Counts the horizontal retrace pulse signal and outputs a 4-bit horizontal address signal X.

The vertical address signal generation counter 62 receives a horizontal retrace pulse signal from a horizontal retrace pulse signal input terminal T61 and a vertical retrace pulse signal from a vertical retrace pulse signal input terminal T62, and generates an address signal to be described later. Part (G
EN) 67, the maximum value yM of the output y is input, the pulses are counted, and the vertical address signals Y and y are output. Output Y is the upper 4 bits of the vertical address,
The output y is a lower 8-bit vertical address signal. Output Y and output y are both reset by the input of the vertical retrace pulse signal.

The portion for counting the lower 8 bits of the vertical address signal generation counter 62 is reset to the starting point every time the count output y reaches the maximum value yM. that time,
The value of the output Y increases by one.

As shown in FIG. 6, the horizontal address X and the vertical address Y function as coordinates for determining a representative grid point on the screen. In FIG. 6, a solid grid pattern represents an effective display image area, and a hatched pattern represents an overscan section or a retrace period section. The maximum value yM is the actual number of scanning lines per vertical grid section. The maximum value y
The value of M has different values depending on the format (horizontal frequency, vertical frequency, number of scanning lines, etc.) of the input signal to the display. On the other hand, the EEPROM 66
The correction amount in the horizontal and vertical directions is stored as 8-bit data as data at 16 × 12 (192) grid points shown in FIG.

The coordinate system conversion ROM 68 stores input signals y, y
The address is designated by M, and the conversion table data z stored at the address is output. this is,
As a result of the vertical address signal y normalized by the maximum value yM,
That is, by expressing the relative vertical position coordinates of one section of the grid,
Even if the vertical frequency changes, the vertical positional relationship does not change.

The vertical slope interpolator (VSI) 672 is
The correction amount Dz for the vertical position z is obtained from the correction amounts at the preceding and succeeding grid points by linear approximation or curve approximation.
In addition, the smoothing of the interpolation processing smoothes the change in the relative luminance, thereby preventing a harmful step-like luminance change disturbance.

The RAM 69 holds the correction data obtained by the vertical slope interpolator 672 at the time when the scanning format of the input video signal to be displayed on the display is completed, and at the time of scanning, the horizontal address X and the vertical address The correction data held at the address specified by Y and y is read. The read data is stored in the DA converter 7
The convergence correction is realized by converting the data into analog data at 0 and the amplifier 71 and generating a correction magnetic field at the CYs 51 and 52 by current driving.

When the input image format is changed, the vertical slope interpolator 672 calculates the R and R again.
Data is written to AM69.

By the above processing, the corrected waveform information is
One type of data is prepared, and even if the image formats are different, a corrected waveform corresponding to the absolute position of the display position can be reproduced by coordinate conversion and interpolation processing. for that reason,
Since no correction waveform is prepared for each image format, it is possible to minimize the storage medium for holding data.

Further, since correction data is not determined for each image format, it is only necessary to perform convergence adjustment for any one image format.
The adjustment time can be easily reduced.

[0025]

However, the recent improvement in the processing capability of a computer is also accompanied by the demand for a display device having a larger screen size, higher image quality and higher resolution. Further, with the densification of images, it is required to improve image reproducibility without screen distortion. Also, as the screen size of the CRT increases,
With the increase in the size of the display device, the installation area on a desk is limited.

Therefore, in a CRT, high picture quality and high resolution are achieved by increasing the frequency of the input video synchronization signal and improving the pixel frequency. Further, image reproducibility is improved by suppressing image distortion due to flattening of the tube surface. Further, by increasing the deflection angle of the electron beam of the CRT, the required distance from the electron gun to the tube surface can be reduced, thereby preventing the display device from increasing in depth.

However, in the convergence correction circuit, an increase in the input video synchronizing frequency causes an increase in a ringing component depending on the CY coil frequency response performance. Period. As a result, during the period in which the convergence correction waveform is deteriorated, desired convergence correction cannot be performed, and deterioration in image reproducibility is induced.

On the other hand, in order to cope with a plurality of input video synchronization frequencies, it is necessary to adjust circuit characteristics so as to obtain optimum compensation characteristics in each frequency domain, which makes the circuit configuration complicated and increases product cost. It is susceptible to variations in element characteristics and aging, making it difficult to ensure stable operation. It is also desirable to avoid an increase in the number of processing circuit elements from the viewpoint of power saving.

An object of the present invention is to provide a display device having a low-cost and high-accuracy digital convergence correction circuit corresponding to a plurality of input video synchronization frequencies in view of the above-mentioned prior art.

Another object of the present invention is to provide a display device which achieves higher image quality by applying not only the convergence correction circuit but also the removal of the ringing waveform component of the main deflection control and the focus correction.

[0031]

In order to solve the above-mentioned problems, the invention of claim 1 corrects deflection distortion or the amount of electron beam overlap deviation by a predetermined correction basic waveform at the time of electron beam deflection scanning. In the display device configured as above, at least a correction basic waveform generation unit, a generation condition determination unit that generates waveform information for compensating a transfer characteristic of the magnetic field generation coil and the drive circuit, a compensation waveform generation unit,
Calculating means for obtaining the respective output waveforms of the corrected basic waveform generating means and the compensated waveform generating means by addition or multiplication; and at the time of electron beam deflection scanning, corrected basic waveform information and compensation waveforms which are outputs of the calculating means. The result of addition or multiplication is applied as correction waveform information to the magnetic field generating coil and the drive circuit.

According to a second aspect of the present invention, in the display device of the first aspect, conversion means for converting a current value flowing through the magnetic field generating coil into actual correction waveform information by converting the waveform, and indicating a propagation delay amount of the circuit. Means for determining the amount of shift to be performed;
Delay means for delay-outputting the corrected basic waveform according to the shift amount determining means; subtracting means for extracting residual noise based on a difference between the actual corrected waveform information and the corrected basic waveform information of the delay means; and residual means for detecting residual noise component information. A component detecting means is provided, and the waveform information for compensating the transfer characteristics of the magnetic field generating coil and the drive circuit is appropriately optimized according to the residual noise component information.

According to a third aspect of the present invention, in the display device according to the first aspect, the generation condition determination means and the compensation waveform generation means include a frequency component, an amplitude, and the like of the correction basic waveform generated by the correction basic waveform generation means. A phase compensation amount, a frequency component as a ripple component elimination condition and an attenuation condition are determined from a known transfer characteristic of a magnetic field generating coil and a drive circuit, and a compensation waveform is generated.

According to a fourth aspect of the present invention, in the display device according to the second aspect, the generation condition determining means and the compensation waveform generating means include a frequency component, an amplitude, and the like of the corrected basic waveform generated by the corrected basic waveform generating means. A phase compensation amount, a frequency component as a ripple component removal condition and an attenuation condition are determined from a known transfer characteristic of a magnetic field generating coil and a drive circuit, a compensation waveform is generated, and a residual component is detected for each deflection control. Based on the residual noise component from the means, the frequency component and the attenuation condition are appropriately optimized, and the residual noise component is reduced by generating a compensation waveform.

According to a fifth aspect of the present invention, in the display device according to any one of the first to fourth aspects, the correction basic waveform generated by the correction basic waveform generating means is set as follows when the deflection control is in a blanking period. The waveform information at the display area deflection start position is held in advance. According to a sixth aspect of the present invention, in the display device according to any one of the first to fifth aspects, the waveform generating means is provided in the convergence correction circuit.

According to a seventh aspect of the present invention, in the display device according to any one of the first to fifth aspects, the waveform generating means is provided in the main deflection waveform generating circuit.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a digital convergence correction circuit in a direct-view CRT display device according to a first embodiment of the present invention will be described below in detail with reference to FIG.

(First Embodiment) Although not shown in the block diagram of FIG. 1, the digital convergence correction circuit includes a display system main control microcomputer (hereinafter referred to as a display control circuit section) as another display control circuit section. , An external CPU), and a means for generating a deflection control main clock (hereinafter, MCLK) by a PLL from an input video synchronization signal from outside the display.

In this embodiment, as in most input video synchronization signals, the video display period is approximately 70 to 80% for both the horizontal synchronization signal and the vertical synchronization signal, and the rest is the blanking period. A description will be given using the example described above.

The convergence correction processing in the present embodiment is performed when an electron beam is emitted by an RGB in-line type electron gun, and the amount of overlap deviation of each of the RGB electron beams applied to the RGB phosphor screen is determined by a predetermined target value. A method using a convergence yoke (CY) having a six-pole structure will be described as a method of controlling so as to be within the range. This is because a CY coil for vertical line correction (4H correction) for correcting the amount of horizontal deviation and a CY coil for horizontal line correction (4V correction) for correcting the amount of vertical deviation are arranged, so that the R electron beam is based on the G electron beam. This is for correcting the amount of deviation between the electron beam and the B electron beam. In addition, the amount of convergence loss at each position on the tube surface is measured in advance, and according to the coil sensitivity (CY sensitivity) determined by the applied current and the correction amount,
This is realized by applying a current value that makes the deviation amount within a predetermined target value.

In order to solve the above problem, as shown in FIG. 1, a digital convergence correction circuit 10 of a display device according to the present invention comprises a clock number counting means 11, a frequency determination means 12, a line number counting means. 13
A coordinate conversion unit 14, a shift amount determination unit 15, a generation condition determination unit 16, a residual component detection unit 17, a first
Waveform generating means 18, second waveform generating means 19, third waveform generating means 20, multiplying means 21, and adding means 2
2, delay means 23, subtraction means 24, digital
Analog conversion means (DAC) 25, current drive amplification means (AMP) 26, and analog-digital conversion means (A
DC) 27 and amplification means (AMP) 28.

Further, the digital convergence correction circuit 10 has a horizontal synchronization signal Hfly input terminal T1, a clock MCLK input terminal T2, a vertical synchronization signal Vsync input terminal T3, and a condition set value input / output terminal T4. . The digital convergence correction circuit 10 includes 4H (vertical line correction CY coil) 51 and 4H of the direct-view CRT 40.
It is connected to a V coil (horizontal line correction CY coil) 52.

The Hfly signal input terminal T1 is connected to FIG.
Hfl which is a horizontal synchronization signal synchronized with the video display area shown in FIG.
The y signal (B) is input.

A clock MCLK synchronized with an Hfly signal generated by an external PLL (Phase Locked Loop) is input to an input terminal T2 of the clock MCLK.

The vertical synchronization signal Vsync is input to the vertical synchronization signal Vsync input terminal T3.

An external CP is connected to the condition set value input / output terminal T4.
The condition setting value from U is input.

The clock number counting means 11 counts the number of MCLK during the Hfly period, and uses the counted value as a horizontal coordinate value X.
The pulse HP indicating the head position of the horizontal coordinate value X is output to the line number counting means 13 while being output to the frequency determination means 12 and the coordinate conversion means 14.

The frequency determining means 12 calculates the horizontal coordinate value X,
From the maximum values of the vertical coordinate values Y, the horizontal synchronization frequency fH and the vertical synchronization frequency fV are determined, and the coordinate conversion means 14 is used.
And output to the shift amount determining means 15.

That is, the frequency determining means 12 determines the horizontal synchronizing frequency fH and the vertical synchronizing frequency fV from the maximum values of the horizontal coordinate value X and the vertical coordinate value Y. Further, the result of determining the synchronization frequency may be read from an external CPU via the input / output terminal T4. Thus, when the input video signal frequency is changed, it is possible to assist in determining the condition settings 4a to 4f in the external CPU.

The line number counting means 13 outputs the vertical synchronizing signal V
sync and a pulse HP indicating the head position of the horizontal coordinate value X are input, the horizontal synchronization signal Hfly existing in the vertical synchronization period is counted, and the counted value is set as the vertical coordinate value Y, and the frequency determination means 1
2 and to the coordinate conversion means 14.

That is, the line number counting means 13 counts the pulse signal HP of the clock number counting means 11 existing within one period of the vertical synchronization signal Vsync from the input terminal T3, and sets the counted value as a vertical coordinate value Y. Output. Further, the vertical coordinate value Y is initialized for each vertical synchronization signal Vsync.

The coordinate conversion means 14 calculates the horizontal coordinate value X from the clock number counting means 11, the vertical coordinate value Y from the line number counting means 13, the horizontal synchronization frequency fH and the vertical synchronization frequency fV, and the video display period. The vertical coordinate value Y display size and display position information 4a set by the external CPU so as to be displayed over the entire CRT displayable area are input, and the horizontal coordinate value x matching the display size and display position is input.
And the vertical coordinate value y to the first waveform generation means 18, the second waveform generation means 25, and the third waveform generation means 20, and determines the shift amount of the horizontal retrace period THB and the vertical retrace period TVB. Output to the means 15 and the generation condition determining means 16.

That is, the coordinate conversion means 14 obtains the display size and the display position information by the condition setting 4a from the external CPU so that the display can be performed over the entire CRT displayable area in accordance with the video display period, and the horizontal address X, the vertical address Y
And outputs a horizontal coordinate value x and a vertical coordinate value y normalized to match the screen absolute position. At the same time, the screen display area is set to an integer K and L
It is divided into pieces and indicates the position coordinates of each grid point. On the other hand, during the retrace period, the coordinates are converted into fixed values or position coordinates normalized by the retrace period and output. In this case, flag information for identifying either the video display period or the flyback period may be output simultaneously. Further, a horizontal retrace period THB and a vertical retrace period TVB are output.

The shift amount determining means 15 converts the conversion information 4b input from the external control unit via the condition set value input / output terminal T4, and outputs the horizontal synchronization frequency fH and the vertical synchronization frequency fV.
, The horizontal retrace period THB and the vertical synchronizing frequency TVB, the amplitude change amount Vpp from the first waveform generation means 18, and the attenuation information 17a from the residual component detection means 17, are input as CY as a circuit propagation delay amount. A phase condition Pa corresponding to the coil driving side and a phase condition Pb corresponding to the return side are generated. The phase condition Pa is sent to the generation condition determining means 16 and the second waveform generating means 19, and the phase condition Pb is sent to the generation condition determining means 1 respectively.
6 and output to the delay means 23.

That is, the shift amount determining means 15 outputs the horizontal retrace period THB and the vertical retrace period TVB of the coordinate transformation means 14.
And the amplitude change amount VPP from the first waveform generating means 18 is obtained, and the circuit delay amount corresponding to the phase condition corresponding to the CY coil driving side is output Pa and the phase corresponding to the return side is obtained as the circuit propagation delay amount. A circuit delay amount corresponding to the condition is defined as an output Pb. This output Pa indicates a start position of a damping waveform 21a described later.

The multiplication means 21 generates the second waveform generation means 19
And the decay waveform dum of the third waveform generation means 20
Multiplies and outputs p. The multiplied output is added to the first
The actual convergence correction waveform is generated and output by adding to the convergence correction basic waveform base which is the output of the waveform generation means 18. In addition, a plurality of circuits may be prepared as the above-described 4H, 4V convergence correction waveform generation calculation processing, and the calculation may be performed by time-parallel processing. However, there is no problem, and the present invention is not restricted at all.

Here, the propagation delay time of the circuit is a phase delay of the analog circuit portion and the amount of attenuation, and is roughly determined by the frequency component and the amplitude. The conversion information of the circuit delay amount with respect to the period TVB and the amplitude is set for each of the CY coil driving side and the return side by the condition setting 4b. Also, an error occurs between the conversion information 4b and the actual delay amount due to the operating conditions of the circuit and the variation in the characteristics of the elements. For this reason, the increase / decrease information 17a of the residual component detecting means 17 described below indicates a decrease. Circuit delay P with fine adjustment of phase advance / delay
a and Pb may be output.

The generation condition determining means 16 includes a phase condition Pa corresponding to the CY coil driving side and a phase condition Pb corresponding to the return side, a horizontal retrace period THB, a vertical retrace period TVB,
The waveform for removing the residual noise component is input with the amplitude change amount Vpp of the first waveform generating means 18, the external setting condition 4f, and the attenuation information 17a and the expansion / contraction information 17b from the residual component detecting means 17. Generation conditions are determined, and a damping frequency Ef, an attenuation period Td, an amplitude value Tdm, and a residual noise component detection period Tdw shown in FIG. The damping frequency Ef is output to the second waveform generator 19, the attenuation period Td and the amplitude value Tdm are output to the third waveform generator 20, and the residual noise component detection period Tdw is output to the residual component detector 17.

The residual component detecting means 17 comprises a circuit propagation noise Er from the subtracting means 24 and an output 23a from the delay means 23.
Is input, the attenuation information 17a and the expansion / contraction information 17b relating to the residual noise component are detected, and the former is output to the shift amount determining means 15 and the generating condition determining means 16, and the latter is output to the generating condition determining means 16.

The first waveform generating means 18 calculates the horizontal coordinate value x
, A vertical coordinate value y, and a preset generation condition 4c are input, and the basic waveform base of the horizontal and vertical convergence correction waveforms is generated and output in a time division manner, and at the same time, the amplitude change amount Vpp before and after the retrace period is output. I do. The basic waveform base of the convergence correction waveform is output to the addition means 22 and the delay means 23, and the amplitude change amount Vpp is output to the shift amount determination means 15 and the generation condition determination means 16, respectively.

The first waveform generating means 18 previously measures the convergence loss amount of the CRT in the state of no convergence correction, and determines the CY coil current corresponding to the convergence correction amount according to the CY sensitivity. The convergence correction basic waveform shown in ()) is obtained in advance. In this case, the horizontal coordinate value x and the vertical coordinate value y are given and the basic waveform base of the convergence correction waveform in the horizontal direction and the vertical direction is generated and output in a time-division manner according to the generation conditions set in advance, and the amplitudes before and after the retrace period are simultaneously The change amount VPP is output.

Thus, in the external CPU, the horizontal frequency fH and the vertical frequency fV obtained by the frequency determination means 12 are obtained.
Then, the order and the coefficient are set by the condition setting 4c as the generator polynomial condition. The convergence-corrected basic waveform is obtained by giving the horizontal coordinate value x and the vertical coordinate value y as variables of the respective generator polynomials.

In this case, K = 16, L
= 12, the above-described conventional EEPROM 110, coordinate system conversion ROM 120, vertical slope interpolator 121,
The convergence correction basic waveform base with the configuration of the RAM 122
Generate

On the other hand, as another method of the first waveform generating means 18, a polynomial expressed by a power may be used. this is,
The above K = 16, L = 12 grid points are determined, and the
A correction waveform corresponding to the correction amount of each of the horizontal component and the vertical component of the grid point (grid point line) is approximated by a polynomial to determine the order and coefficient. At the same time, the other 11 lines are similarly obtained.

In this case, the horizontal coordinate value x and the vertical coordinate value y are given, and the basic waveform base of the convergence correction waveform in the horizontal direction and the vertical direction is generated and output in a time-division manner according to a preset generation condition. And outputs the amplitude change amount VPP.

On the other hand, as another method of the first waveform generating means 18, a polynomial expressed by a power may be used. this is,
The above K = 16, L = 12 grid points are determined, and the
A correction waveform corresponding to the correction amount of each of the horizontal component and the vertical component of the grid point (grid point line) is approximated by a polynomial to determine the order and coefficient. At the same time, the other 11 lines are similarly obtained.

That is, the second waveform generating means 19 calculates the horizontal coordinate value x, the vertical coordinate value y, the phase condition Pa corresponding to the CY coil driving side, the damping frequency Ef, and the condition 4d.
Is input, and the horizontal retrace period TH and the vertical retrace period TVB
, And outputs a sine wave sin shown in FIG. 2E in accordance with the phase condition Pa specified by the shift amount determining means 15.

In the second waveform generating means 19, the ringing noise determined by the generating condition determining means 16 according to the CY coil drive side circuit delay Pa of the shift amount determining means 15 and the horizontal retrace period THB and the vertical retrace period TVB. A frequency Ef is obtained, and a sine wave sin is generated and output according to the screen position coordinates x and y.
As a method of generating the sine wave sin, the sine wave may be obtained by waveform calculation, or basic waveform data of the sine wave may be prepared as a look-up table, and the table may be referred to at a cycle that matches a desired frequency. good.

The third waveform generating means 20 receives the horizontal coordinate value x, the vertical coordinate value y, the decay period Td and the amplitude value Tdm from the generating condition determining means 16, and the condition 4e.
The attenuation waveform du shown in FIG.
Output mp.

That is, the third waveform generating means 20 obtains the delay amount Pa of the shift amount determining means 15, the amplitude Tdm of the sine wave sin from the generating condition determining means 16 and the attenuation amount Td represented by the attenuation period, Output the attenuation waveform dump.

The multiplying means 21 includes a second waveform generating means 19
Output value sin and output value dump of the third waveform generation means 20
And outputs a multiplied value (damping waveform) 21 a to the adding means 22.

The multiplication means 21 generates the second waveform generation means 19
And the decay waveform dum of the third waveform generation means 20
Multiplies and outputs p. The multiplied output is added to the first
The actual convergence correction waveform is generated and output by adding to the convergence correction basic waveform base which is the output of the waveform generation means 18. In addition, a plurality of circuits may be prepared as the above-described 4H, 4V convergence correction waveform generation calculation processing, and the calculation may be performed by time-parallel processing. However, there is no problem, and the present invention is not restricted at all.

The adding means 22 includes a first waveform generating means 18
Base waveform of convergence correction waveform output from
And the output value (damping waveform) 21a of the multiplying means 21 and the damped waveform is output to the DAC 25.

The delay means 23 includes a first waveform generation means 18
4H, 4V basic convergence correction waveform ba
se and the frequency delay amount Pb of the shift amount determining means 15 are input, and the convergence correction waveform value base is delayed by a delay amount Pb corresponding to an analog circuit delay described later to output delay correction waveforms 23a and 23b.

The delay means 23 outputs the 4H, 4V convergence correction waveform value base in accordance with the delay amount Pb on the CY coil return side which is the output of the shift amount determining means 15. Here, instead of the delay processing by the delay means 23, there is no problem if the first waveform generation means 18 generates and outputs a delayed waveform by delaying the operation start position by time division. Rather, the circuit scale can be reduced by eliminating the need for a storage medium required for delay processing. Further, it is possible to easily deal with different delay amounts flexibly, for example, only by setting the start position.

The subtraction means 24 outputs the output value C, which represents the CY coil current value of the ADC 27 shown in FIG.
3 is output as the circuit propagation noise Er shown in FIG.

The DAC 25 converts the 4H and 4V convergence correction waveform values represented by digital values output in a time division manner into voltage values at the output of the adding means 22.

The current drive amplification means 26 has a 4H coil (C
The current flowing through each of the Y coil 51 and the 4V coil (CY coil) 52 is amplified.

The ADC 27 converts the voltage value of the amplifying means 28 into a digital value.

The amplifying means 28 converts the current value C flowing through the 4HCY coil 51 (FIG. 2 (D)) into the current value D flowing through the 4VCY coil 52, and adjusts the range.

The convergence correction circuit having such a configuration reduces the ringing noise component by controlling the system so that the circuit compensation waveform is superimposed on the convergence correction waveform base in advance so that the residual noise component Er is reduced. Driving a CY coil with a convergence correction waveform to achieve highly accurate convergence correction;
For a plurality of input video synchronization frequencies, the convergence correction can be achieved only by changing the circuit compensation waveform generation condition without changing the basic waveform shape.
Since the generation of the unnecessary magnetic field component generated by the noise component is suppressed, the adverse effect on the deflection control can be reduced.

The operation of the convergence correction circuit according to this embodiment will be briefly described below. First, the clock number counting means 11 counts one cycle period of the horizontal synchronizing signal Hfly input from the input terminal T1 using MCLK input from the input terminal T2, and outputs the counting result as a horizontal coordinate value X. This horizontal coordinate value X is initialized for each Hfly. Further, the clock number counting means 11 calculates the horizontal coordinate value X
Output a pulse HP representing the head position of. However, there is no problem even if the pulse HP is used as the Hfly signal itself. Here, the frequency of MCLK has at least a value that achieves a desired accuracy as the frequency detection accuracy of the horizontal synchronization signal Hfly.

According to the present invention, even when the frequency of the input video signal is changed, it is possible to shift to a stable operation state corresponding to the frequency of the input video signal after an appropriate time has elapsed.

On the other hand, the convergence correction amount between the horizontal grid points is determined by giving a horizontal coordinate value x to the generator polynomial, and the interpolation of the correction value between the vertical grid points is performed in the horizontal direction above and below the grid point line. The vertical coordinate value y is obtained by interpolation from the correction amount at the coordinate value x. In this case, the interpolation method may be obtained by primary interpolation, but the correction component obtained in the vertical direction (lattice point sequence) of 16 lattice points by the same processing previously determined for the lattice point line. May be interpolated by a polynomial approximation formula for the vertical coordinate value y. Further, the interpolation between the lattice points may be obtained by an approximate polynomial of the preceding and succeeding lattice points.

Here, in this embodiment, K = 16, L
Although the description has been made assuming that = 12, the present invention is not limited to this, and there is no problem if the number is increased or decreased. For example, by increasing the number of grid points, more accurate convergence correction can be performed.
On the other hand, the reduction in the number of grid points enables a reduction in the capacity of the generation condition storage medium that holds the polynomial generation conditions, a reduction in the amount of calculation processing of the correction waveform, and a reduction in adjustment time at the time of factory adjustment.

Hereinafter, a method of generating an attenuation waveform will be specifically described. First, the attenuation waveform shape is determined in advance by a polynomial approximation with respect to the waveform shape matched to the tracking characteristics of the circuit, and
The coefficient is determined by the condition setting 4e from the external CPU. The amplitude is determined by Tdm. The screen position coordinate x as a variable
Is normalized by the decay period Td.

An approximate polynomial is calculated under the above conditions to determine an attenuation waveform dump. Also, to calculate the waveform for each line,
High-speed tracking of a temporal change of a residual noise component is realized.

FIG. 2 shows the waveforms of the circuit shown in FIG. 1, wherein (A) the input video signal Video, (B) the horizontal synchronizing Hfly signal, and (C) the first waveform generating means 18. (D) shows the ringing waveform at point C in FIG. 1, (E) shows the sine wave output sin of the second waveform generating means 19, and (F) shows the third waveform generating means 20. (G) shows the residual eddy component detection period Tdw of the generation condition determination means 16, and (H) shows the output Er of the subtraction means 24.

Here, by providing a plurality of waveform generating means constituted by the second waveform generating means 19, the third waveform generating means 20, and the multiplying means 21, it is possible to cope with a plurality of frequency components of ringing noise. Alternatively, the circuit may be processed in a time-division manner to cope with a plurality of frequency components.

The 4H correction and 4V correction convergence correction waveforms generated as described above are converted into voltage amplitude values by the DAC 25, respectively, and the current is driven by the current drive amplifier 26 in accordance with the voltage amplitude values.

By applying convergence correction currents of 4H and 4V to the CY coils 51 and 52, the deviation of each electron beam is corrected in the horizontal and vertical directions by the convergence correction amount corresponding to the CY sensitivity. .

Hereinafter, a specific example of the configuration of the amplifier 26 will be described.
This will be described with reference to FIG. The amplifier 26 includes a voltage amplifier 260 for amplifying a convergence correction amount represented by the amplitude of the DAC 25 to a desired amplitude level, an amplifier 261 for flowing a current through a CY coil according to an output value of the voltage amplifier 260, and an oscillation prevention damper circuit. 262, a resistor 263, a current detection resistor 264, and a phase compensation circuit 265.

The voltage amplifier 260 amplifies the convergence correction amount represented by the amplitude of the DAC 25 to a desired amplitude level. The amplifier 261 allows a current to flow through the CY coil according to the output value of the voltage amplifier 260. The current detection resistor 264 detects a current flowing through the CY coil. Phase compensation means 26
5 compensates for the phase of the current flowing through the CY coil.

Here, the frequency of the input video synchronizing signal is improved, and the circuit transmission delay in the oscillation preventing damper circuits 262, 263 cannot be ignored. In particular, when the amplitude greatly changes before and after the horizontal retrace period, the phase lag is maximized.
By changing the amplitude to the top of the line in the horizontal retrace period and within the frequency tracking range of the circuit as shown in (2), securing a flat period and adding a current in advance, the pseudo absorption of the phase delay By reducing the phase compensation means 265, the cost of the means can be reduced.

Further, even when a ringing component is generated in the drive current in response to a frequency change and a sharp change in the current value during the flyback period, the operation is stabilized in a flat region during the flyback period. Therefore, the return frequency component in the flyback period can be increased in order to secure the flat period.

As shown by the broken line in FIG. 2C, the waveforms before and after the retrace period are generated not by primary interpolation but by higher-order interpolation as the convergence correction basic waveforms of the first waveform generator 18. A convergence correction basic waveform that is smoothly connected can be used. As a result, it is possible to suppress a steep change in the frequency component, and to reduce the deviation of the frequency response of the analog means from the followable range.

The amplifier 28 converts the current values flowing through the horizontal and vertical convergence correction 4HCY coils 51 and the convergence correction 4VCY coils 52 into voltage values and outputs them. As an example, a voltage waveform diagram at a point C in FIG. 1 is shown in FIG.

The ADC 27 converts the output voltage value of the amplifying means 28 into a digital value and outputs it. The gain is corrected so that the voltage amplitude value after the AD conversion matches the amplitude value of the waveform output of the first waveform generation unit 18. In this case, according to the amplitude of the basic correction waveform 23b, even if the amplitude value of the waveform output is determined by the reference potential that determines the conversion rate of the ADC 27,
Alternatively, the information after AD conversion may be subjected to amplitude conversion using a digital value, but any method may be used. However, by performing amplitude conversion using a digital value, it is possible to minimize the influence of circuit characteristic changes and the like. Becomes

The subtraction means 24 outputs the output value of the ADC 24 representing the CY coil current value and the convergence correction basic waveform.
The difference Er from the base is obtained. In this case, the convergence correction basic waveform is delayed by the amount of delay of the circuit element by the delay unit 23 so that the phase thereof matches the output value of the ADC 27. Here, the difference Er is detected as circuit propagation residual noise Er that cannot be completely removed by the dump waveform 21a superimposed on the convergence correction basic waveform base.

The residual component detecting means 17 obtains the circuit propagation residual noise Er and the residual noise detection period Tdw, detects the amount of circuit propagation residual noise Er generated in the residual noise detection period Tdw, and determines the amount as the residual noise component. Output. The residual noise detection period Tdw is a signal indicating a period in which unnecessary error information in the flyback period is removed, which is equal to the attenuation period Td of the dump waveform 21a and is delayed by the circuit element delay amount Pb.

On the other hand, as the detection of the amount of circuit propagation residual noise Er, the residual noise amount at each screen coordinate position x within the residual noise detection period Tdw is converted to an absolute value, and then cumulatively added.
The accumulated value at the dw end position is detected as a residual noise component. Further, it manages the increase / decrease of the residual noise component between the lines, and increases / decreases information 17 indicating any of the increase / constant / decrease directions.
Outputs a. Further, a residual noise disappearance position where the circuit propagation residual noise Er becomes zero is detected within the line, and expansion / contraction information 17 indicating a shift direction of the residual noise disappearance position between the lines.
Output b.

Hereinafter, in this embodiment, a line for which raster display has been completed in the past is referred to as a previous line, a line for detecting a residual noise component is referred to as a target line, and a line for reflecting a detection result is referred to as a next line.

When generating the increase / decrease information 17a and the expansion / contraction information 17b, information from a plurality of previous lines is obtained by a weighted average as a process between the previous line and the line of interest so as to avoid the influence of sudden noise mixing. It may be. Also,
In the first line of the frame, the transient response is absorbed by allocating the line to a plurality of lines outside the image display area, and the operation is stabilized in the image display area.

During the display period using the same synchronous frequency, weighted averaging is performed for each line between frames to store and retain increase / decrease information 17a and expansion / contraction information 17b. In that case, the increase / decrease information 17a and the expansion / contraction information 17b may be determined by averaging the increase / decrease information 17a of the previous frame and the expansion / contraction information 17b. This prevents excessive response control to sudden noise and improves the stability of the system. Further, the residual noise component may be detected by frequency component analysis using FFT (Fast Fourier Transform).

The reduction of the residual noise component is realized by controlling the decreasing direction of the increase / decrease information 17a and the contracting direction of the expansion / contraction information 17b as described above. When the system is stabilized, the increase / decrease information 17a and the expansion / contraction information 17b are constant. The control accuracy and sensitivity of the system are determined by the resolution of the increase / decrease information 17a and the resolution of the expansion / contraction information 17b.

Further, even when the convergence correction waveform is modulated in a frame, the increase / decrease information 17a and the expansion / contraction information 17b can follow, thereby achieving stable control. Furthermore, in order to avoid system stability in an erroneous area, a disturbance may be applied to promote stability deviation.

The generation condition determining means 16 outputs the phase condition Pa corresponding to the CY coil driving side and the circuit delay amount Pb corresponding to the return side, which are the outputs of the shift amount determining means 15, and the increase / decrease information 17a of the residual component detecting means 17. And the expansion / contraction information 17b is obtained, and the damping frequency Ef, the amplitude value Tdm of the attenuation waveform dump, the attenuation period Td, and the residual component detection period Tdw are determined as the conditions for generating the damping waveform 21a.

The details of the processing in the generation condition determining means 16 will be described below. First, as the damping frequency Ef,
The frequency components THB and TVB during the flyback period are obtained from the coordinate conversion means 14. In this case, when a flat region is defined in the convergence correction basic waveform in the retrace period, the frequency component is indicated by a value excluding the period. The characteristics of the analog circuit are known in advance, and the frequency components of the ringing waveform with respect to the frequency components THB and TVB are roughly determined.
The initial value Ef0 of the damping frequency Ef is set. Although this initial value Ef0 is not shown, the frequency components THB and TVB
There is no problem even if it is obtained and set from an external CPU. However, the analog circuit does not always match the target analog circuit due to factors such as variations in circuit element characteristics, temperature characteristics, and deterioration over time.

First, at the head of a line in a frame, a damping waveform is generated at the damping frequency Ef0 and applied to the CY coil to obtain increase / decrease information 17a for the line of interest. However, the increase / decrease information 17a is obtained without giving consideration to the increase / decrease information 17a, for example, as the damping frequency Ef for the next line as the first correction value Ef1 lower than the initial value Ef0. In this case, when the increase / decrease information 17a indicates an increase, it is determined that the frequency component of the actual ringing waveform is higher than the initial value Ef0, and the second line frequency component is raised from the initial value Ef0 for the next line. The correction value Ef2 is given, and the validity of the control direction is also determined based on the increase / decrease information 17a. on the other hand,
If the increase / decrease information 17a indicates a decrease, it is determined that the frequency component of the actual ringing waveform is lower than Ef1, and a second correction value in which the frequency component is lower than the first correction value Ef1 for the next line. Ef2 is given, and the validity of the control direction is also determined based on the increase / decrease information 17a.

The above-described processing is sequentially performed for each line, and a frequency at which the increase / decrease information 17a is stabilized is determined as an optimum damping frequency Ef.

By the same processing as described above, the increase / decrease information 1
Based on 7a, the amplitude value Tdm of the attenuation waveform dump is also obtained. Here, the initial value Tdm0 of the amplitude value Tdm is roughly determined by the frequency components THB and TVB and the amplitude change amount Vpp of the first waveform generating means 18 during the retrace period.
It may be generated by a conversion table (not shown) set by the condition setting 4f by the external CPU, or may be set by the condition setting 4f by the external CPU.

When the convergence correction basic waveform is modulated in the vertical direction, Vpp changes in line units, but does not change greatly between lines.
Sufficient follow-up control is possible.

For the decay period Td, the initial value Td0 and the optimal decay period Td are determined by the same processing as described above and the follow-up control based on the expansion / contraction information 17b, thereby realizing the stable operation of the system. The residual component detection period Tdw is
The convergence correction basic waveform is delayed by Pb of the shift amount determining means 15 to generate and output a control signal using the attenuation period Td as window information, and the residual component detecting means 17 detects the window information for detecting the circuit propagation residual noise. Used as of course,
The purpose of this window information is to eliminate unnecessary noise components during the flyback period, and does not depend on the attenuation period Td, and there is no problem even if the window information is set to coincide with the image display period. However, by limiting the detection period, the calculation processing time and the processing amount can be reduced.

By the processing described above, Pa and Pb in the shift amount determining means 15 and Er and T in the generation condition determining means 16 are obtained.
Optimal control of d, Tdm, and Tdw can be realized. Here, the respective optimal controls may be performed at the same time, or may be performed individually sequentially to simplify the control. The condition is to avoid extending the image display period.

By the above processing, even if the frequency component generated in the flyback period is raised and the circuit oscillates,
By superimposing the optimal damping waveform on the convergence correction basic waveform, it is possible to effectively attenuate the ringing component generated in the convergence correction waveform,
The effect on the image display period can be minimized.

In the present embodiment based on the present invention, an example in which a circuit is used as the realizing means has been described. However, it is needless to say that a digital signal processor (D
SP: Digital Signal Processor) arithmetic processing, C
The convergence correction waveform may be generated by the method shown in the present embodiment based on the present invention regardless of the method such as the arithmetic processing by the PU or the arithmetic processing by the entire hardware configuration.

(Effects of this embodiment) With the above configuration and processing, a convergence correction basic waveform for correcting the amount of convergence blur generated due to factors such as the CRT tube surface shape and the characteristics of the deflection coil when generating a convergence correction waveform. Thus, it is possible to generate an optimized damping waveform for compensating for analog circuit characteristics determined for each frequency of a video signal. Thus, it is possible to prevent the convergence correction waveform from deteriorating due to unnecessary frequency components due to the transfer characteristic of the analog circuit, which is a cause of image quality deterioration due to color misregistration. , The amount of convergence of each of the RGB electron beams can be kept within a predetermined range over the entire CRT display area, and high-quality image reproduction with reduced color shift can be achieved.

Further, since the so-called feedback control is used, it is possible to construct a stable system which is hardly influenced by disturbances or the like.

Further, the frequency characteristics of the damper circuits 262 and 263 required for a case where a static compensating circuit is used are widened, and an obscure circuit which requires a compensating circuit for a plurality of video signal frequencies is added. Can be simplified. At the same time, the simplification of the analog circuit section minimizes the degradation of the transfer characteristics of the analog circuit, minimizing the deviation of the convergence correction point from the target position due to the circuit delay, supporting high-frequency video frequencies, and improving circuit cost. And power consumption can be reduced.

(Second Embodiment) Hereinafter, another embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a direct-view display device having a digital convergence correction circuit according to a second embodiment of the present invention.

The configuration shown in FIG. 4 is different from the convergence correction circuit described above with reference to FIG. 1 in that the residual component detecting means 17, the delay means 23, the subtracting means 24, the ADC 27, and the amplifier 28 constituting the feedback portion are provided. Is deleted.
Blocks having the same reference numerals as those of the circuit shown in FIG. 1 perform almost the same operation, and thus description thereof will be omitted.

In this embodiment, the shift amount determining means 15
This is characterized in that a shift amount determining means 29 is provided in place of, and a generation condition determining means 30 is provided in place of the generation condition determining means 16.

The shift amount determining means 29 performs the same processing as the shift amount determining means 15, but omits fine adjustment of the output of Pb and the advance / delay of the phase. Line periods THB, TVB and first waveform generating means 18
, And outputs the start position Pa of the damping waveform 21a.

[0124] The generation condition determination means 30 includes the coordinate conversion means 1
From 4, the frequency components THB and TVB of the retrace period are obtained. In this case, when a flat area is defined in the convergence correction basic waveform in the retrace period, the frequency component is indicated by a value excluding the period.

The characteristics of the analog circuit are known in advance, and the frequency components of the ringing waveform with respect to the frequency components THB and TVB are roughly determined, and the damping frequency Ef is set by the condition setting 4f by the external CPU.

The amplitude value Tdm of the attenuated waveform dump is roughly determined by the frequency components THB and TVB and the amplitude change amount Vpp of the first waveform generating means 18 during the retrace period, and is set in advance by the condition setting 4f. It may be generated by a conversion table, or may be determined by the condition setting 4f by the external CPU, and the value may be determined in line units.

By the above processing, even if the frequency component generated in the flyback period is raised and the circuit oscillates,
By superimposing the optimal damping waveform identified in advance on the convergence correction basic waveform, it is possible to effectively attenuate the ringing component generated in the convergence correction waveform, and minimize the effect on the image display period. It is.

As a result, the same effects as shown in the first embodiment can be obtained, and at the same time, the circuit configuration can be simplified, and the circuit system construction can be simplified by reducing the amount of arithmetic processing, thereby reducing the circuit cost. Can be achieved.

As described above, the first and second embodiments based on the present invention have been described only in the case where the present invention is applied to the convergence correction circuit of a direct-view CRT display device. For example, even when applied to vertical main deflection and horizontal main deflection of a direct-view CRT display device, unnecessary frequency components can be removed by similar processing, and for the same reason, high-definition image quality can be realized. can do.

Further, the CRT 40 shown in FIG. 1 or FIG.
It is needless to say that a similar effect can be obtained by adapting to a convergence correction device or the like of a projection type CRT display device by using a configuration as the CRT 45 for color projection.

Further, by applying not only the convergence correction circuit but also the removal of the ringing waveform component of the main deflection control and the focus correction, it is possible to achieve a display device which achieves higher image quality.

As described above, the present invention is applied to the convergence correction circuit of the display device.
The control target is not limited to an analog circuit at all. For example, the present invention is applied to a transient response control of a seek operation of a read / write head of a recording / reproducing medium such as a CD, a DVD, an HD, etc. By superimposing the control waveform component that suppresses the flutter of the head, a stable seek operation is realized, and it is also easy to realize a high seek time. Further, in this case, since no special control device is required, an increase in product cost can be suppressed. Similarly, it is suitable for operation control of other mechanical devices, and can easily realize a stable control system at low cost.

[0133]

According to the present invention, when a convergence correction waveform of a direct-view CRT display device is generated, a convergence correction basic waveform for correcting an amount of convergence blur generated by factors such as a CRT tube surface shape and characteristics of a deflection coil. Thus, it is possible to optimally generate a damping waveform for compensating for analog circuit characteristics determined for each of several video signal frequencies. Thus, it is possible to prevent the convergence correction waveform from deteriorating due to unnecessary frequency components due to the transfer characteristic of the analog circuit, which is a cause of image quality deterioration due to color misregistration. , It is possible to keep the amount of convergence of each of the RGB electron beams within a predetermined range in the entire CRT display area, and to achieve high-quality image reproduction with suppressed color shift.

Further, since the circuit response characteristics are improved by so-called feedback control, it is possible to construct a stable system which is not easily influenced by disturbances and the like.

Further, it is possible to simplify the bandwidth of the frequency characteristic of the damper circuit required when a static compensating circuit is used, and to add a complicated circuit required for a compensating circuit to cope with a plurality of video signal frequencies. it can.

Simultaneously, the simplification of the analog circuit section is to suppress the transfer characteristic deterioration of the analog circuit as much as possible, to suppress the deviation of the convergence correction point from the target position due to the circuit delay, and to cope with the high frequency video frequency. Thus, it is possible to reduce the circuit cost and the power consumption.

As a result, it is possible to achieve an increase in the screen size while suppressing an increase in the depth size of the apparatus, further improvement in image quality and resolution, and improvement in image reproducibility.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a CRT display device including a convergence correction circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart supplementing the operation of the convergence correction circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a CY amplifier.

FIG. 4 is a block diagram illustrating a configuration of a CRT display device including a convergence correction circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a circuit configuration of a conventional projection CRT display.

FIG. 6 is a relationship diagram showing a relationship between a display image display area and grid points.

[Explanation of symbols]

 T1, T2, T3 input terminals T4 input / output terminals 10 convergence correction circuit 11 clock number counting means 12 frequency determination means 13 line number counting means 14 coordinate conversion means 15 shift amount determination means 16 generation condition determination means 17 residual component detection means 18 1 waveform generation means 19 second waveform generation means 20 third waveform generation means 21 multiplication means 22 addition means 23 delay means 24 subtraction means 25 digital-analog conversion means (DAC) 26 current drive amplification means 27 analog-digital conversion Means (ADC) 28 Range adjustment amplifying means 40 Direct view type CRT 51, 52 CY coil

Continued on the front page F-term (reference) 5C060 CA04 CE03 CF04 CG01 CG07 CH00 CH03 CH04 HA02 HA07 HB00 HB16 HB24 HB26 HB27 JA01

Claims (7)

[Claims] 1. A display device for correcting deflection distortion or an amount of electron beam displacement by a predetermined correction basic waveform during deflection scanning of an electron beam, comprising: at least a correction basic waveform generating means; The output waveforms of the generation condition determination means for generating the waveform information for compensating the transfer characteristics of the coil and the drive circuit, the compensation waveform generation means, the corrected basic waveform generation means and the compensation waveform generation means are added or multiplied. Calculating means to be sought,
And applying the result of addition or multiplication of the compensation basic waveform information and the compensation waveform, which is the output of the calculating means, to the coil for generating a magnetic field and the drive circuit as the compensation waveform information during the deflection scanning of the electron beam. A display device characterized by the above-mentioned. 2. The display device according to claim 1,
Further, conversion means for converting the value of the current flowing through the magnetic field generating coil into actual correction waveform information by waveform conversion, shift amount determination means for instructing the propagation delay amount of the circuit, and delay output of the correction basic waveform according to the shift amount determination means. And delay means for extracting residual noise based on the difference between the actual corrected waveform information and the corrected basic waveform information of the delay means, and residual component detection means for detecting residual noise component information. A display device, characterized in that waveform information for compensating transfer characteristics of a magnetic field generating coil and a drive circuit is appropriately optimized according to component information. 3. The display device according to claim 1, wherein the generation condition determination means and the compensation waveform generation means include a frequency component, an amplitude, and the like of the correction basic waveform generated by the correction basic waveform generation means, and a magnetic field known in advance. A phase compensation amount, a frequency component as a ripple component elimination condition and an attenuation condition are determined from a transfer characteristic of a generating coil and a drive circuit, and a compensation waveform is generated. 4. The display device according to claim 2, wherein the generation condition determination means and the compensation waveform generation means include a frequency component, an amplitude, and the like of the correction basic waveform generated by the correction basic waveform generation means, and a magnetic field known in advance. From the transfer characteristics of the generating coil and the drive circuit, a phase compensation amount, a frequency component and an attenuation condition as a ripple component elimination condition are determined, a compensation waveform is generated, and a residual noise from the residual component detecting means is generated for each deflection control. A display device comprising: appropriately optimizing a frequency component and an attenuation condition based on a component; and reducing a residual noise component by generating a compensation waveform. 5. The display device according to claim 1, wherein the correction basic waveform generated by the correction basic waveform generating means is provided at a next display area deflection start position during a deflection control flyback period. Wherein the waveform information is stored in advance. 6. The display device according to claim 1, wherein the convergence correction circuit includes a waveform generation unit. 7. The display device according to claim 1, wherein the waveform generation means is provided in the main deflection waveform generation circuit.