JP2001054109A - Alignment device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an alignment device that can detect a start code of an MPEG video decoder at a high-speed with a simple circuit configuration. SOLUTION: In the case that a pre-processing circuit 1 aligns a coded video stream in compliance with the MPEG standards into a coded video stream of a parallel 8-bit configuration and also aligns the coded video stream of the parallel 8-bit configuration into a coded video stream of a parallel 32-bit configuration, the pre-processing circuit 1 inserts dummy data of a parallel 8-bit configuration to the coded video stream of the parallel 8-bit configuration as required so as to apply word-alignment to a start code, and a 32-bit alignment circuit 2 aligns the coded video stream of the parallel 8-bit configuration outputted from the pre-processing circuit 1 into a coded video stream of a parallel 32-bit configuration and gives it to a video decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPEG (Moving
The present invention relates to an aligning apparatus suitable for decoding an encoded video stream of the Picture Experts Group standard.

[0002]

2. Description of the Related Art A video stream encoded according to the MPEG1 or MPEG2 standard contains a special bit pattern called a start code.
By detecting the start code from the encoded video stream, the video decoding device for the G system can start the decoding operation of the subsequent video data based on the start code.

[0003] The start code consists of a 3-byte prefix and a 1-byte ID.
“0000 0000 0000 0000 0000
A code value of "0001" is assigned, and there is no code value other than the start code.

For example, a code value "0000 0000" is assigned to the ID portion for a picture start code, and a code value "1011 0011" is assigned to a sequence head code.

[0005]

In a conventional video decoding apparatus for an MPEG system, a start code is detected by performing pattern matching while shifting an encoded video stream one bit at a time. There is a problem that high-speed detection cannot be performed.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide an alignment apparatus which can detect a start code in a video decoding apparatus for an MPEG system with a simple circuit configuration and at a high speed. And

[0007]

SUMMARY OF THE INVENTION The aligning apparatus of the present invention converts an encoded video stream of the MPEG standard into a parallel stream.
A preprocessing circuit for inserting dummy data into an MPEG standard encoded video stream, if necessary, so that the start code is word-aligned when the encoded video stream is bit-aligned; The encoded video stream output from
And a 32-bit aligning circuit for aligning the encoded video stream with a 2-bit configuration.

According to the present invention, since a start code can be word-aligned, a video decoding apparatus for an MPEG system can simply execute a 32-bit unit without shifting a coded video stream by one bit and performing pattern matching. The start code can be detected only by monitoring the data.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block circuit diagram showing a main part of one embodiment of the present invention. In FIG. The encoded video stream output from is input, and the encoded video stream having the parallel 8-bit configuration is aligned with the encoded video stream having the parallel 8-bit configuration. If necessary, as if the start code were word aligned,
This is a preprocessing circuit for inserting dummy data “00000000” having a parallel 8-bit configuration into an encoded video stream having a parallel 8-bit configuration.

Reference numeral 2 denotes a unit for aligning a parallel 8-bit coded video stream output from the preprocessing circuit 1 with a parallel 32-bit coded video stream.
The bit alignment circuit 3 is a control circuit for controlling the preprocessing circuit 1 and the 32-bit alignment circuit 2.

FIG. 2 is a block circuit diagram showing the configuration of the pre-processing circuit 1 and the control circuit 3. In FIG. 2, reference numeral 4 denotes an encoded video stream of a parallel 8-bit configuration which is output from the demultiplexer. Is a byte-aligned circuit.

Reference numerals 5-1 to 5-8 denote flip-flop circuits constituting a latch circuit for latching the parallel output BA of the byte alignment circuit 4, and reference numerals 6-1 to 6-8 denote flip-flop circuits 5-1 to 5--8. And a flip-flop circuit constituting a latch circuit for latching eight parallel outputs. These flip-flop circuits 5-1 to 5-8, 6-1 to 6-8
Is, when the write enable signal WE is at the H level,
When the writing is enabled and the write enable signal WE is at the L level, the writing is disabled.

Reference numeral 7 denotes a selector whose selection operation is controlled by the selector control signal SL. When the selector control signal SL is at the L level, the selector 7 selects the parallel outputs of the flip-flop circuits 6-1 to 6-8. When the selector control signal SL is at the H level, the dummy data "00000000" having a parallel 8-bit configuration is selected.

Reference numeral 8 denotes the number of times of byte alignment processing in the byte alignment circuit 4 and a count value B
A byte counter that repeatedly updates C in the order of 0 → 1 → 2 → 3 → 0 → 1 → 2 → 3, 9 is a parallel output of the byte align circuit 4 and a parallel output of the flip-flop circuits 5-1 to 5-8 And a start code front part detection circuit for detecting the front part of the start code from the parallel outputs of the flip-flop circuits 6-1 to 6-8.

Reference numeral 10 denotes a selector control circuit for controlling the selector 7 by generating a selector control signal SL. When the start code preceding part detecting circuit 9 detects the preceding part of the start code, the count of the byte counter 8 is counted. If the value BC is not zero, the selector control signal S is output until the count value BC of the byte counter 8 becomes zero next time.
L is set to H level, and otherwise, the selector control signal SL is set to L level.

Reference numeral 11 denotes a write enable signal generating circuit for generating a write enable signal WE. This write enable signal generating circuit 11 detects when the start code preceding portion detecting circuit 9 detects the preceding portion of the start code. If the count value BC of the byte counter 8 is not zero, the write enable signal WE is changed to L until the count value BC of the byte counter 8 becomes zero next time.
In other cases, the write enable signal WE is set to the H level.

FIG. 3 is a block circuit diagram showing the configuration of the 32-bit alignment circuit 2. In FIG.
Reference numeral 8 denotes a flip-flop circuit forming a latch circuit for latching the parallel output of the selector 7, and reference numerals 13-1 to 13-8 denote flip-flops forming a latch circuit for latching the parallel outputs of the flip-flop circuits 12-1 to 12-8. circuit,
14-1 to 14-8 are flip-flop circuits 13-1 to 13-8
Flip-flop circuits constituting latch circuits for latching parallel outputs of 13-8, 15-1 to 15-8 represent flip-flop circuits constituting latch circuits for latching parallel outputs of flip-flop circuits 14-1 to 14-8 It is.

These flip-flop circuits 12-1 to 12-1
2-8, 13-1 to 13-8, 14-1 to 14-8, 1
In 5-1 to 15-8, writing is enabled when the write enable signal WE is at the H level, and writing is disabled when the write enable signal WE is at the L level.

FIG. 4 is a timing chart showing an operation example of one embodiment of the present invention. The operation cycle, the operation clock CLK, the parallel output BA of the byte alignment circuit 4, and the flip-flop circuits (FF) 5-1 to 5- 8, 6-1 to 6
-8, 12-1 to 12-8, 13-1 to 13-8, 14
-1 to 14-8, parallel output of 15-1 to 15-8, count value BC of byte counter 8, selector control signal SL
And a write enable signal WE.

Here, a start code is present in the sixth to ninth column portions (dotted portions) of the encoded 8-bit video stream output from the byte-aligned circuit 4. In the first cycle, the byte alignment circuit 4 outputs the 0-th column of the encoded video stream having a parallel 8-bit configuration as an example.

As a result, in the second cycle, the byte alignment circuit 4 outputs the first column of the coded video stream having a parallel 8-bit configuration, and the flip-flop circuit 5-1.
From 0 to 5-8, the 0th column of the encoded video stream having a parallel 8-bit configuration is output.

Then, in the seventh cycle, the flip-flop circuits 12-1 to 12-8 output the third column of the encoded video stream having a parallel 8-bit configuration, and the flip-flop circuits 13-1 to 13-8. Output a second column of the encoded video stream having a parallel 8-bit configuration,
The first column of the parallel 8-bit coded video stream is output from the flip-flop circuits 14-1 to 14-8, and the first column of the parallel 8-bit coded video stream is output from the flip-flop circuits 15-1 to 15-8. Zero columns will be output.

In this example, since the counter value BC of the byte counter 8 is initialized to be zero in the seventh cycle, the flip-flop circuits 12-1 to 12-8, 13-1 to 13-8, 14-
1 to 14-8 and 15-1 to 15-8 are supplied to the video decoding apparatus as parallel 32-bit encoded video data (D1) output as parallel 32-bit encoded video data. Will be controlled.

Thereafter, in the ninth cycle, the parallel output of the byte align circuit 4 becomes “0000 0001”, the parallel outputs of the flip-flop circuits 5-1 to 5-8 become “0000 0000”, and Since the parallel outputs of 6-1 to 6-8 are "0000 0000", the start code preceding part detection circuit 9
Code value assigned to the front part of the start code “0000 0000 0000 0000 0000
0001 "is detected.

Here, in the ninth cycle, the count value BC of the byte counter 8 is 2 and the count value BC of the byte counter 8 becomes 0 next in the eleventh cycle. Period of the eleventh cycle,
The selector control signal SL is at H level and the write enable signal WE is at L level.

As a result, in the tenth cycle and the eleventh cycle, the selector 7 selects the dummy data instead of the parallel outputs of the flip-flop circuits 6-1 to 6-8. After the fifth column of the coded video stream, two columns of dummy data “0000 0000” and “0000 0000” having a parallel 8-bit configuration are inserted.

As a result, in the eleventh cycle, the flip-flop circuits 12-1 to 12-8, 13-1 to 1
3-8 outputs dummy data having a parallel 8-bit configuration, and flip-flop circuits 14-1 to 14-8 output the fifth column of the encoded video stream having a parallel 8-bit configuration. ~ 15-8
From the encoded video stream of parallel 8-bit configuration
The columns will be output.

In the eleventh cycle, the counter value BC of the byte counter 8 becomes 0. Therefore, in the eleventh cycle, the flip-flop circuits 12-1 to 12-8, 1
3-1 to 13-8, 14-1 to 14-8, 15-1 to 1
Control is performed so that the encoded video data (D2) of the parallel 32-bit configuration output from 5-8 is supplied to the video decoding device as encoded video data aligned in parallel 32-bit.

Thereafter, in the fifteenth cycle, the ninth column of the encoded video stream having a parallel 8-bit configuration is output from the flip-flop circuits 12-1 to 12-8, and the flip-flop circuits 13-1 to 13-8 output the ninth column. The eighth column of the 8-bit coded video stream is output, and the flip-flop circuits 14-1 to 14-8 output the seventh column of the parallel 8-bit coded video stream, and the flip-flop circuit 15-1 From 15 to 15-8, the sixth column of the encoded video stream having the parallel 8-bit configuration is output.

In the fifteenth cycle, the counter value BC of the byte counter 8 becomes 0. Therefore, in the fifteenth cycle, the flip-flop circuits 12-1 to 12-8, 1
3-1 to 13-8, 14-1 to 14-8, 15-1 to 1
The control is performed so that the encoded video data (D3) of the parallel 32-bit configuration output from 5-8 is supplied to the video decoding device as encoded video data aligned in parallel 32-bit.

Hereinafter, the same operation is performed. Note that D4
Shows encoded 32-bit encoded video data supplied to the video decoding device after the encoded 32-bit encoded video data.

Here, for example, when the encoded video stream output from the separation device is an encoded video stream such as 20h FCh 39h 00h 00h 01h B3h 52h 3Ch... (The underlined portion is Start code), when this is directly aligned with the encoded video stream of the parallel 32-bit configuration, the alignment is performed as follows: 20h, FCh, 39h, 00h 00h , 01h , B3h , 52h 3ch ,. Are not word-aligned, but according to one embodiment of the invention, as required, such as 20h, FCh, 39h, 00h (dummy data) 00h , 00h , 01h , B3h 52h, 3Ch,. By inserting a dummy code before the start code It can be word-aligned the start code.

FIG. 5 shows an MPE having an embodiment of the present invention.
It is a block circuit diagram which shows the principal part of an example of a G decoding device,
In FIG. 5, reference numeral 16 denotes a separating device for separating a multiplexed coded stream of the MPEG standard into a coded video stream, a coded audio stream, and a coded private stream.

Reference numeral 17 denotes an aligning device according to an embodiment of the present invention, and reference numeral 18 denotes an aligning device 17 according to an embodiment of the present invention.
This is a video decoding device that decodes an encoded video stream of a parallel 32-bit configuration output from a.

Reference numeral 19 denotes an audio decoding device for decoding the encoded audio stream output from the separation device 16, and reference numeral 20 denotes a private decoding device for decoding the encoded private stream output from the separation device 16.

FIG. 6 is a block circuit diagram showing the structure of the video decoding device 18. In FIG. 6, reference numeral 21 denotes a parallel 32-bit coded video stream output from the aligning device 17 according to one embodiment of the present invention. This is a video data buffer to be stored.

A start code detector 22 detects a start code from a video stream of a parallel 32-bit structure stored in the video data buffer 21.
Is a variable length decoding unit that decodes a variable length code to obtain a quantization coefficient and a motion vector.

An inverse quantization unit 24 performs inverse quantization.
Reference numeral 25 denotes an inverse DCT unit that performs an inverse discrete cosine transform, 26 denotes a motion compensation unit that performs an inter-frame prediction motion compensation, and 27 denotes a display control unit that controls display on a monitor.

In the MPEG decoding device shown in FIG.
The encoded video stream output from the separation device 16 is aligned by an aligning device 17 according to an embodiment of the present invention into an encoded video stream having a parallel 32-bit configuration so that the start code is word-aligned, and the video decoding device 18.

Therefore, the start code detecting section 22 of the video decoding device 18 does not perform pattern matching by shifting the coded video stream output from the video data buffer 21 by 1 bit, but simply executes the parallel 32-bit data. The start code can be detected simply by monitoring the start code, so that the start code can be detected at a high speed with a simple circuit configuration.

As described above, since the start code can be detected at a high speed, for example, when decoding an encoded video stream, decoding of a normal image is skipped, and the start code of a forward or backward image is detected. Even when necessary, the start code can be detected at a high speed, so that the speed of image display can be increased.

If the encoded video stream contains a grammatical error, it is necessary to detect the next start code, but this start code can also be detected at high speed. Therefore, it is possible to minimize image disturbance when a grammatical error is included in the encoded video stream.

When the encoded video stream is missing, it is necessary to detect the start code immediately after the data loss. However, the start code can be detected at high speed. Can be minimized when the image is missing.

Since the start code is word-aligned and supplied to the video decoding device 18, when the start code detecting section 22 detects a start code of an upper layer, the start point is stored. In this case, the start code of the lower hierarchy can be easily detected in byte units from this detection point.

Here, when the contents of one embodiment of the present invention are arranged, at least the present invention includes the following aligning apparatus.

(1) When the encoded video stream of the MPEG standard is aligned with the encoded video stream of the parallel 32-bit configuration, the encoded video stream of the MPEG standard is used as necessary so that the start code is word-aligned. A pre-processing circuit for inserting dummy data into the stream; and a 32-bit aligning circuit for aligning the encoded video stream output from the pre-processing circuit with a parallel 32-bit encoded video stream. Alignment equipment.

(2) The aligning apparatus according to (1), wherein the dummy data is data in units of data in which "0" s are arranged in 8 bits in parallel.

(3) In the aligning apparatus according to (2), the pre-processing circuit includes a byte-aligned circuit that aligns the encoded video stream with a parallel 8-bit encoded video stream; A first latch circuit for latching a parallel output; a second latch circuit for latching the parallel output of the first latch circuit; and a selector for selecting the parallel output or dummy data of the second latch circuit. An aligning device.

(4) In the alignment apparatus according to (3), a byte counter for counting the number of times of byte alignment processing in the byte alignment circuit, a parallel output of the byte alignment circuit, and the first and second latches A start code front part detection circuit for detecting a front part of a start code from the parallel output of the circuit; anda write enable signal based on the count value of the byte counter and the output of the start code front part detection circuit, and A write enable signal generation circuit for controlling a write permission / non-permission operation of the second latch circuit; and a selector control signal based on the count value of the byte counter and the output of the start code preceding part detection circuit to output a selector control signal. A selector control circuit for controlling the select operation. Aligned and wherein the.

(5) In the aligning device according to (4), the 32-bit align circuit has a third latch circuit that controls a write enable / disable operation by the write enable signal and latches a parallel output of the selector. ,
A write enable / disable operation controlled by the write enable signal, a fourth latch circuit for latching a parallel output of the third latch circuit, and a write enable / disable operation controlled by the write enable signal; A fifth latch circuit for latching a parallel output, wherein the parallel output of the third, fourth and fifth latch circuits is
An alignment device, which is configured to be an output of a bit alignment circuit.

(6) In the aligning apparatus according to the above (5), the byte aligning circuit sets the count value to n.
(Where n is an integer) → n + 1 → n + 2 → n + 3 → n → n
The selector control circuit is configured to update the count value of the byte counter to n when the start code preceding portion detection circuit detects the preceding portion of the start code.
Otherwise, the count value of the byte counter is n
And the selector controls the selector so that the selector selects the parallel output of the second latch circuit otherwise. The enable signal generating circuit, when the count value of the byte counter is other than n, when the count value of the byte counter is other than n, when the count value of the byte code is other than n, the count value of the byte counter is n. Until said
It is configured to generate a write enable signal for setting the fifth latch circuit to a non-writable state, and otherwise setting the first to fifth latch circuits to a writable state. An alignment device characterized by the following.

[0052]

As described above, according to the present invention, the MPE
Since the video decoding device for the G system can detect the start code simply by monitoring the data of the parallel 32-bit configuration without performing pattern matching by shifting the encoded video stream one bit at a time,
The start code can be detected at a high speed with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a block circuit diagram illustrating a configuration of a preprocessing circuit and a control circuit included in an embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a configuration of a 32-bit alignment circuit included in an embodiment of the present invention.

FIG. 4 is a timing chart showing an operation example of one embodiment of the present invention.

FIG. 5 is a block circuit diagram illustrating a main part of an example of an MPEG decoding device including an embodiment of the present invention.

6 is a block circuit diagram showing a configuration of a video decoding device provided in the MPEG decoding device shown in FIG.

[Explanation of symbols]

 (FIG. 1) 1 Pre-processing circuit 2 32-bit align circuit 3 Control circuit (FIG. 2) 4 Byte align circuit 5-1 to 5-8 Flip-flop circuit 6-1 to 6-8 Flip-flop circuit 7 Selector 8 Byte counter 9 Start code preceding part detection circuit 10 Selector control circuit 11 Write enable signal generation circuit (FIG. 3) 12-1 to 12-8 flip-flop circuits 13-1 to 13-8 flip-flop circuits 14-1 to 14-8 flip-flop circuits 15-1 to 15-8 Flip-Flop Circuit (FIG. 5) 16 Separation Device 17 Alignment Device of One Embodiment of the Present Invention 18 Video Decoding Device 19 Audio Decoding Device 20 Private Decoding Device (FIG. 6) 21 Video Data Buffer 22 Start Code Detection unit 23 variable length decoding unit 24 inverse quantization unit 2 Inverse DCT unit 26 the motion compensation unit 27 display control unit

Claims (1)

[Claims] When an encoded video stream of the MPEG standard is aligned with an encoded video stream of a parallel 32-bit configuration, the encoded video stream of the MPEG standard is processed as necessary so that the start code is word-aligned. A pre-processing circuit that inserts dummy data into the stream; and a 32-bit alignment circuit that aligns the encoded video stream output from the pre-processing circuit with a parallel 32-bit encoded video stream. Alignment equipment.