JP2001053621A - Crc generation part and crc calculation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently generate a CRC when discrete data in the main storage of a computer are stored into a transmission data storage part for transmission and to efficiently check the normality of transmitted data with a small circuit scale. SOLUTION: An AND circuit 1037 ANDs the output of a transmit data register 1033 stored with transmit data and the output of a byte effectiveness register 1036 stored with a transmit byte effectiveness showing effectiveness or ineffectiveness and an XOR circuit 1034 XORs the output of the AND circuit 1037 and the output of a halfway result register 1032. A selecting circuit 1038 selects the output of the XOR circuit 1034 or the output of a CRC calculating circuit 1035 according to the final bit of the byte effectiveness register, stores it into a reception handling register 1039 or reception handling register 103A, and stores it into the CRC halfway result register 1032 through a selecting circuit 1031.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRC generator,
More particularly, the present invention relates to a CRC generation unit and a CRC calculation device that efficiently calculate a CRC from discrete transmission data and efficiently check the normality of received data.

[0002]

2. Description of the Related Art As a technique relating to CRC (Cyclic Redundancy Check), there is a technique described in, for example, Japanese Patent Application Laid-Open No. 7-1070200. This technique is based on the following: "an N-byte shift register for inputting bit-synchronized input data, a compensation polynomial driving unit connected to an output terminal of the N-byte shift register, and the bit-synchronized input data, An operation unit that receives an output of the compensation polynomial driving unit and performs compensation polynomial modulo-2 subtraction and generation polynomial modulo-2 division, a block synchronization identification unit connected to the operation unit, the N byte shift register, and a block synchronization A 64: 8 data selection unit connected to the identification unit for outputting byte-synchronized output data, and identifying the block boundary in units of bits to start byte-synchronized and block-synchronized data. It is an object of the present invention to provide a simple cyclic redundancy check (CRC) synchronizer having an output before time point.

As a technique related to CRC (Cyclic Redundancy Check), for example, there is a technique described in Japanese Patent Publication No. 9-507118.

[0004]

The above-mentioned problem of the prior art is that the efficiency is poor when the discrete data in the byte unit stored in the main memory is added to the CRC as the transmission data and transmitted. .

[0005] The reason is that the configuration does not take into account the discrete data in byte units.

SUMMARY OF THE INVENTION It is an object of the present invention to efficiently generate a CRC and reduce the normality of transmitted data when storing discrete data in a main memory of a computer in a transmission data storage unit for transmission. This is to implement it efficiently on a circuit scale.

[0007]

A first CRC generator of the present invention comprises: (a) a transmission data register for storing transmission data including valid byte data to be transmitted; and (b) each byte of the transmission data. (C) a byte valid register for storing a byte valid signal in units of bytes indicating valid / invalid of
(D) an AND circuit for calculating an AND of an output of the transmission data register and an output of the byte valid register;
(E) an XOR circuit for creating an exclusive OR of an output of the CRC intermediate result register and an output of the AND circuit; (f) the XOR CRC from circuit output
And (g) selecting the output of the CRC calculation circuit when the byte valid signal for the last byte of the byte valid register indicates valid, and when the byte valid signal for the last byte indicates invalid. A first selection circuit for selecting an output of the XOR circuit and outputting the result as an intermediate result or a final result of CRC; and (h) holding an output of the first selection circuit for a data receiving device.
(I) selecting one of an intermediate result of the CRC of the output of the first selection circuit, an intermediate result of the CRC of the output of the one or more reception corresponding registers, and an initial value of the CRC; A second selection circuit that outputs the result to the CRC intermediate result register.

[0008] The first CRC calculation device of the present invention comprises:
A data transmission device having the first CRC generation unit, and adding a CRC generated by the first CRC generation unit to transmission data and transmitting the transmission data; (b) transmitting data transmitted from the data transmission device; A network for transferring a CRC, and (c) having the first CRC generation unit, receiving transmission data from the data transmission device transferred via the network as reception data, and receiving a CRC;
It is characterized by having one or more data receiving devices for comparing the CRC generated by the first CRC generator from the received data with the received CRC and checking the normality of the received data.

A second CRC calculation device according to the present invention is the first CRC calculation device, wherein a main storage unit for storing transmission data in discrete bytes, a transmission data storage unit,
A first CRC generation unit, a selection circuit unit, and a control unit, and (a) data including valid transmission data read at once from the main storage unit via the selection circuit; Sequentially storing only valid data in accordance with the instruction of the control unit, and then storing the CRC from the first CRC generation unit; and (b) once from the main storage unit. According to the byte valid signal from the control unit, the read data including the valid transmission data is subjected to a CRC.
And (c) the selection circuit unit that selects one of data from the main memory and a CRC from the first CRC generation unit according to an instruction from the control unit. (D) the control unit for transmitting transmission data and a CRC from the transmission data storage unit to the one or more data reception devices via the network;
The data transmission device comprising:

[0010] A third CRC calculation device according to the present invention is the first or second CRC calculation device, wherein a main storage unit for storing discrete bytes of received data, a received data storage unit, A first CRC generation unit, a comparison circuit unit,
And (a) storing transmission data transferred from the data transmission device via the network as reception data, and storing a CRC transferred from the data transmission device via the network. A reception data storage unit; and (b) the first CRC for generating a CRC according to a byte valid signal from the control unit for data including data to be written from the reception data storage unit to the main storage unit at one time. A generation unit; and (c) a CR from the first CRC generation unit in accordance with an instruction from the control unit.
C: a comparison circuit for comparing C with the CRC from the reception data storage unit; and (d) the control unit for determining that the reception data is normal if the comparison result in the comparison circuit unit matches; The data receiving device comprising:

[0011] A second CRC generation unit according to the present invention, when the byte length of data read out from the main storage unit at a time is an integral multiple of the byte length of data that can be written into the transmission data storage unit at one time, The AND circuit, the XOR circuit, the CRC calculation circuit, and the first selection circuit have an integral multiple.

A fourth CRC calculation device according to the present invention comprises: (a)
A data transmission device having the second CRC generation unit, and adding the CRC generated by the second CRC generation unit to transmission data and transmitting the transmission data; and (b) transmitting data transmitted from the data transmission device; A network for transferring a CRC, and (c) having the second CRC generation unit, receiving transmission data from the data transmission device transferred via the network as reception data, and receiving a CRC;
There is at least one data receiving device that compares a CRC generated by the second CRC generator from the received data with the received CRC and checks the normality of the received data.

A fifth CRC calculation device according to the present invention is the fourth CRC calculation device, wherein: a main storage unit for storing transmission data in discrete bytes; a transmission data storage unit;
A second CRC generation unit, a selection circuit unit, and a control unit, and (a) data including valid transmission data read at once from the main storage unit via the selection circuit; Sequentially storing only valid data according to the instruction of the control unit, and then storing the CRC from the second CRC generation unit; and (b) once from the main storage unit. According to the byte valid signal from the control unit, the read data including the valid transmission data is subjected to a CRC.
And (c) the selection circuit unit that selects one of data from the main memory and a CRC from the second CRC generation unit according to an instruction from the control unit. (D) the control unit for transmitting transmission data and a CRC from the transmission data storage unit to the one or more data reception devices via the network;
The data transmission device comprising:

The sixth CRC calculation device of the present invention is the fourth or fifth CRC calculation device, wherein: a main storage unit for storing discrete bytes of received data; a received data storage unit; A second CRC generation unit, a comparison circuit unit,
And (a) storing transmission data transferred from the data transmission device via the network as reception data, and storing a CRC transferred from the data transmission device via the network. A reception data storage unit, and (b) the second CRC for generating a CRC according to a byte valid signal from the control unit for data including data to be written from the reception data storage unit to the main storage unit at one time. A generation unit, and (c) a CR from the second CRC generation unit in accordance with an instruction from the control unit.
C: a comparison circuit for comparing C with the CRC from the reception data storage unit; and (d) the control unit for determining that the reception data is normal if the comparison result in the comparison circuit unit matches; The data receiving device comprising:

[0015]

Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. Referring to FIG. 1, an embodiment of the present invention includes a data transmitting device 10
, A data receiving device 20, a data receiving device 40, and a network 30 connecting the data transmitting device 10, the data receiving device 20, and the data receiving device 40.

Further, the data transmitting apparatus 10 includes a main storage unit 1
01, the transmission data storage unit 102, and the CRC generation unit 10
3, a selection circuit unit 104, and a control unit 105.

The data receiving device 20 and the data receiving device 40 include a main storage unit 201, a CRC generation unit 203,
The control unit 205 includes a control unit 205, a reception data storage unit 206, and a comparison circuit unit 207.

FIG. 2 is a block diagram showing details of the CRC generator 103 in FIG. Referring to FIG. 2, the CRC generation unit 103 includes a selection circuit 1031, a CRC intermediate result register 1032, a transmission data register 1033, an XOR circuit 1034 having an exclusive OR function,
A calculation circuit 1035, a byte valid register 1036,
AND circuit 1037 having a logical product function and selection circuit 1
038, a reception correspondence register 1039, and a reception correspondence register 103A. The CRC generation unit 203 has the same configuration as the CRC generation unit 103.

If the transmission data from the main storage unit 101 is a CRC
The transmission data register 1033 of the generation unit 103 and the transmission data storage unit 102 are supplied via the selection circuit unit 104, and the transmission byte valid signal is supplied from the control unit 105 to the transmission data storage unit 102 and the byte valid register 1036. . Here, the transmission data is 4 [bytes],
The transmission byte valid signal is supplied with a value of “1” when each byte of the transmission data is valid, and with a value of “0” when the byte is invalid. Therefore, the transmission byte valid signal is 4 [bits].
It is.

The AND circuit 1037 performs an AND operation on the output of the transmission data register 1033 and the output of the byte valid register 1036 in byte units. That is, a valid byte has the same value, and an invalid byte is “0”.
Is output.

In the CRC calculation circuit 1035, for example, the remainder obtained by shifting the output of the XOR circuit 1034 to the left by 32 [bits] and dividing by the hexadecimal value "FD3EE249" is calculated.

In the selection circuit 1038, when the signal corresponding to the last byte (for example, the rightmost byte) of the transmission data register 1033 in the byte valid register 1036 is valid, the output of the CRC calculation circuit 1035 is selected. When the signal corresponding to the byte is invalid, the output of the CRC intermediate result register 1032 and the AND circuit 1037
The output of the XOR circuit 1034 which has calculated the exclusive OR of the outputs of the above is selected.

The output of the selection circuit 1038 is
31, and as an intermediate result of the CRC calculation,
If it is for the data receiving device 20, it is held in the reception correspondence register 1039, and if it is for the data reception device 40, it is held in the reception correspondence register 103A and further held in the CRC intermediate result register 1032.

If the last byte of the last four bytes of the transmission data is not the data to be transmitted, padding data (dummy data) such that the last byte signal of the transmission byte valid signal indicates validity. Is supplied and supplied.

Next, the operation of the first embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows transmission data,
FIG. 9 is an explanatory diagram showing an array of received data. FIG. 4 is a time chart illustrating the operation of the first exemplary embodiment of the present invention. Referring to FIG. 3, the main storage unit 101 stores transmission data X1, X2, X3,
X4, X5, X6, X7, X8, X9, X10, X1
1, X12 are stored. Transmission data X1, X2,
X3 is discontinuous by 1 [byte] each, and transmission data X4 to X12 are continuous by 9 [bytes].

The transmission data X1, X2, and X3 are located at the 0th byte, the 3rd byte, and the 2nd byte, respectively, on the 4-byte boundary, and the transmission data X4 to X6 are the first to third bytes, respectively. In the byte, the transmission data X7 to X10 are
In the third byte, the transmission data X11 to X12 are located at the 0th to the 2nd byte.

Similarly, the main storage unit 101 stores transmission data Y 1, Y 2, Y
3, Y4, Y5, Y6, Y7, and Y8 are stored.
The transmission data Y1, Y2, and Y3 are each 1 byte.
The transmission data Y4 to Y5 are continuous for 2 [bytes], and the transmission data Y6 to Y8 are continuous for 3 [bytes].

The transmission data Y1, Y2, and X3 are respectively located at the second byte, the first byte, and the second byte on the 4-byte boundary, and the transmission data Y4 to Y5 are the 0th to the first byte, respectively. The transmission data Y6 to X8 are located in the second to zeroth bytes.

First, in accordance with an instruction from the control unit 105, the main storage unit 101 stores four bytes on the 4-byte boundary including the transmission data X1.
[Byte] (X1, *, *, *) is read and the CRC
The data is output to the transmission data storage unit 102 via the generation unit 103 and the selection circuit unit 104 (* indicates 1 [byte] data that is not transmitted).

Next, 4 [bytes] (*, *, Y1, *) on a 4-byte boundary including the transmission data Y1 and 4 [bytes] (*, Y2, 4) on a 4-byte boundary including the transmission data Y2 are sequentially.
*, *), 4 bytes (*, *, *, X2) on a 4-byte boundary including the transmission data X2, and 4 including the transmission data Y3
4 [bytes] at byte boundaries (*, Y3, *, *), 4 [bytes] at 4 byte boundaries including transmission data Y4 to Y5
(Y4, Y5, *, *), 4 bytes at the 4-byte boundary including the transmission data X3 (*, *, X3, *), and 4 bytes at the 4-byte boundary including the transmission data X4 to X6 (* ,
X4, X5, X6), 4 including transmission data X7 to X10
4 bytes at the byte boundary (X7, X8, X9, X1
0), 4 bytes at a 4-byte boundary including transmission data X11 to X12 (X11, X12, *, *), and 4 bytes at a 4-byte boundary including transmission data Y6 to Y7 (*,
*, Y6, Y7) and 4 [bytes] (Y8, *, *, *) on a 4-byte boundary including the transmission data Y8 are read out, and the transmission data storage unit 102 and the CRC generation unit 103 are sequentially read.
Is output to

Further, the control unit 105 sequentially outputs a transmission byte valid signal (4 [bits]) corresponding to 4 [bytes] at each 4-byte boundary to the transmission data storage unit 102 and the CRC generation unit 103. You.

As shown in FIG. 3, only the transmission data to be transmitted is packed and stored in the transmission data storage unit 102 in accordance with the transmission byte valid signal for each area of the data receiving device 20 and the data receiving device 40. Is done.

First, the operation of the data transmission device 10 will be described.

The CRC generation unit 103 first controls the control unit 10
5 stores the CRC initial value (for example, all the values of “0”) in the CRC intermediate result register 1032 via the selection circuit 1031 and transmits the data (X1, *, *, *) And the corresponding transmission data transmission byte valid signal (1, 0, 0, 0) from the control unit 105, respectively.
033, stored in byte valid register 1036, CRC
The output (X) of the XOR circuit 1034 which has calculated the exclusive OR of the output (0, 0, 0, 0) of the intermediate result register 1032 and the output (X1, 0, 0, 0) of the AND circuit 1037
1, 0, 0, 0) is selected by the selection circuit 1038. Further, the transmission data (X1) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (the cycle T in FIG. 4).
0).

Next, the CRC generation unit 103
5 via the selection circuit 1031 and the CRC
Initial value (0,0,0,0) is set to CRC intermediate result register 1
032, and the output (X1, 0,
(0, 0) is stored in the reception correspondence register 1039, and the next data (Y1, *, *, *) and the transmission data transmission byte valid signal (1, 0, 0, 0) are respectively stored in the transmission data register 1033, The data is stored in the byte valid register 1036, and the output (0, 0,
0, 0) and the output of the AND circuit 1037 (Y1, 0, 0,
0), the output (Y1, 0, 0, 0) of the XOR circuit 1034, which has been calculated by the exclusive OR operation, is selected by the selection circuit 1038. Further, the transmission data (Y1) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T1 in FIG. 4).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (Y1,
(0, 0, 0) is stored in the CRC intermediate result register 1032, and the output (Y1, 0, 0, 0) of the selection circuit 1038 is stored in the reception correspondence register 103A, and the next data (*, Y
2, *, *) and the transmission data transmission byte valid signal (0, 1, 0, 0), respectively.
033, stored in byte valid register 1036, CRC
Output of the intermediate result register 1032 (Y1, 0, 0, 0)
And the output (Y) of the XOR circuit 1034 that is obtained by calculating the exclusive OR of the output (0, Y2, 0, 0) of the AND circuit 1037
1, Y2, 0, 0) is selected by the selection circuit 1038. Also, the transmission data (Y2) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (see cycle T in FIG. 4).
2).

Next, the CRC generation unit 103
5, the output (X1, 0, 0, 0) of the reception correspondence register 1039 is transmitted to the C
The data is stored in the RC intermediate result register 1032 and the selection circuit 10
38 (Y1, Y2, 0, 0) are stored in the reception register 103A, and the next data (*, X2, *, *)
And transmission data transmission byte valid signal (0, 1, 0,
0) are respectively stored in the transmission data register 1033 and the byte valid register 1036, and the output (X1, 0, 0, 0) of the CRC intermediate result register 1032 and the AND circuit 1
The output (X1, X2, 0, X1, X2, 0, 0) of the XOR circuit 1034 which calculated the exclusive OR with the output (0, X2, 0, 0) of the bit 037
0) is selected by the selection circuit 1038. Further, the transmission data (X2) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T3 in FIG. 4).

Next, the CRC generation unit 103
5 in response to the output (Y1, Y2, 0, 0) of the reception correspondence register 103A through the selection circuit 1031.
The data is stored in the RC intermediate result register 1032 and the selection circuit 10
The output (X1, X2, 0, 0) is stored in the reception correspondence register 1039, and the next data (*, *, Y3, *),
And transmission data transmission byte valid signal (0, 0, 1,
0) are stored in the transmission data register 1033 and the byte valid register 1036, respectively, and the output (Y1, Y2, 0, 0) of the CRC intermediate result register 1032 and the output (0, 0, Y3, 0) of the AND circuit 1037 are stored in the transmission data register 1033 and the byte valid register 1036, respectively. Of the XOR circuit 1034 (X1, Y2, Y3)
3,0) is selected by the selection circuit 1038. The transmission data (Y3) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T4 in FIG. 4).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (Y1,
Y2, Y3, 0) in the CRC intermediate result register 1032
And the output (Y1, Y2, Y
(3, 0) is stored in the reception correspondence register 103A, and the next data (*, *, *, Y4) and the transmission data transmission byte valid signal (0, 0, 0, 1) are respectively stored in the transmission data register 1033, The data is stored in the byte valid register 1036, and the output (Y1, Y
2, Y3, 0) and the output of the AND circuit 1037 (0, 0,
0, Y4) and an XOR circuit 10 that has performed an exclusive OR operation with the XOR circuit 10
34 (Y1, Y2, Y3, Y4) are input to a CRC calculation circuit 1035 to calculate a CRC, and the CRC (C1
, C12, C13, C14) are selected by the selection circuit 1038. Further, the transmission data (Y4) is transmitted to the selection circuit unit 104.
(FIG. 4, cycle T5).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (C1
, C12, C13, C14) to the CRC intermediate result register 1032 and the output (C1
1, C12, C13, and C14)
3A, the next data (Y5, *, *, *) and the transmission data transmission byte valid signal (1, 0, 0, 0) are stored in the transmission data register 1033 and the byte valid register 1036, respectively. CRC intermediate result register 10
32 outputs (C11, C12, C13, C14) and AN
The output (C21, C21, X21) of the XOR circuit 1034 that has calculated the exclusive OR with the output (Y5, 0, 0, 0) of the D circuit 1037
C12, C13, and C14) are selected by the selection circuit 1038. The transmission data (Y5) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T6 in FIG. 4).

Next, the CRC generation unit 103
5, the output (X1, X2, 0, 0) of the reception correspondence register 1039 is passed through the selection circuit 1031.
The data is stored in the CRC intermediate result register 1032 and the selection circuit 1
038 (C21, C12, C13, C14) is stored in the reception correspondence register 103A, and the next data (*,
*, X3, *) and the transmission data transmission byte valid signal (0, 0, 1, 0), respectively.
033, stored in byte valid register 1036, CRC
The output of the intermediate result register 1032 (X1, X2, 0,
0) and the output of the AND circuit 1037 (0, 0, X3, 0)
The selection circuit 1038 selects the output (X1, X2, X3, 0) of the XOR circuit 1034 that has performed the exclusive OR operation with. Further, the transmission data (X3) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T7 in FIG. 4).

Next, the CRC generation unit 103
5, the output (X1,
X2, X3, 0) in the CRC intermediate result register 1032
And the outputs (X1, X2, X
3,0) is stored in the reception correspondence register 1039, and the next data (*, *, *, X4) and the transmission data transmission byte valid signal (0, 0, 0, 1) are respectively stored in the transmission data register 1033, The data is stored in the byte valid register 1036, and the output (X1, X
2, X3, 0) and the output (0, 0,
0, X4) and an XOR circuit 10 that has performed an exclusive OR operation with the XOR circuit 10
34 (X1, X2, X3, X4) are input to a CRC calculation circuit 1035, the CRC is calculated, and the CRC (D1
1, D12, D13, D14) are selected by the selection circuit 1038. Also, the transmission data (X4) is transmitted to the selection circuit unit 104.
Is stored in the transmission data storage unit 102 through the process (cycle T8).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (D1
, D12, D13, D14) in the CRC intermediate result register 1032 and the output (D1
1, D12, D13, D14) in the reception register 10
39, and the next data (X5, X6, *, *) and the transmission data transmission byte valid signal (1, 1, 0, 0)
Are stored in the transmission data register 1033 and the byte valid register 1036, respectively.
032 (D11, D12, D13, D14) and A
The output (D2) of the XOR circuit 1034 that has calculated the exclusive OR with the output (X5, X6, 0, 0) of the ND circuit 1037
, D22, D13, and D14) are selected by the selection circuit 1038. Further, the transmission data (X5, X6) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T9).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (D2
, D22, D13, D14) in the CRC intermediate result register 1032 and the output (D2
1, D22, D13, D14) in the reception register 10
39, the next data (*, *, X7, X8) and the transmission data transmission byte valid signal (0, 0, 1, 1)
Are stored in the transmission data register 1033 and the byte valid register 1036, respectively.
032 (D21, D22, D13, D14) and A
The output (D2) of the XOR circuit 1034 that has calculated the exclusive OR with the output (0, 0, X7, X8) of the ND circuit 1037
, D22, D23, D24) by the CRC calculation circuit 103
5, CRC is calculated, and CRC (D31, D3
, D33, D34) are selected by the selection circuit 1038.
Further, the transmission data (X7, X8) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T).
10).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (D3
, D32, D33, and D34) to the CRC intermediate result register 1032 and the output (D3
1, D32, D33, D34) in the reception register 10
39, and the next data (X9, X10, *, *),
And transmission data transmission byte valid signal (1, 1, 0,
0) are stored in the transmission data register 1033 and the byte valid register 1036, respectively, and the outputs (D31, D32, D33, D34) of the CRC intermediate result register 1032 are stored.
And the output of the AND circuit 1037 (X9, X10, 0, 0)
The output (D41, D42, D33, D34) of the XOR circuit 1034 which has calculated the exclusive OR with the selection circuit 103
Select with 8. Further, the transmission data (X9, X10) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T11).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (D4
, D42, D33, D34) to the CRC intermediate result register 1032 and the output (D4
1, D42, D33, D34) in the reception register 10
39, and the next data (*, *, X11, X1
2) and a transmission data transmission byte valid signal (0, 0,
, 1) are stored in the transmission data register 1033 and the byte valid register 1036, respectively, and the outputs (D41, D42, D33, D3) of the CRC intermediate result register 1032 are stored.
4) and the output of the AND circuit 1037 (0, 0, X11, X
XOR circuit 1034 which calculated exclusive OR with 12)
(D41, D42, D43, D44) are input to a CRC calculation circuit 1035, and the CRC is calculated.
51, D52, D53, and D54) are selected by the selection circuit 1038. The transmission data (X11, X12) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T12).

Next, the CRC generation unit 103
5, the output CRC of the selection circuit 1038
(D51, D52, D53, D54) are stored in the reception correspondence register 1039, and the CRC (D51, D52, D5) of the output of the selection circuit 1038 is output via the selection circuit section 104.
, D54) in the transmission data storage unit 102 (cycle 13).

Next, the CRC generation unit 103
5, the output (C21, C12, C13, C14) of the reception correspondence register 103A is selected by the selection circuit 103.
1 is stored in the CRC intermediate result register 1032 via
The next data (*, Y6, Y7, *) and the transmission data transmission byte valid signal (0, 1, 1, 0) are sent to the transmission data register 1033 and the byte valid register 103, respectively.
6 and outputs (C21, C12, C13, C14) of the CRC intermediate result register 1032 and the AND circuit 10
37. The outputs (C21, C22, C22, C22, C22,...) Of the XOR circuit 1034 which calculated the exclusive OR with the outputs (0, Y6, Y7, 0) of the 37
C23, C14) are selected by the selection circuit 1038. Further, the transmission data (Y6, Y7) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T1).
4).

Further, the transmission data (X1, X2, X3, X4) is read from the transmission data storage unit 102 and transmitted to the data receiving device 20 via the network 30 (cycle T14).

Next, the CRC generation unit 103
5, the output of the selection circuit 1031 (C2
, C22, C23, C14) in the CRC intermediate result register 1032 and the output (C2
1, C22, C23, C14) in the reception register 10
3A, the next data (*, *, *, Y8) and the transmission data transmission byte valid signal (0, 0, 0, 1) are stored in the transmission data register 1033 and the byte valid register 1036, respectively. CRC intermediate result register 10
32 outputs (C21, C22, C23, C14) and AN
The output (C21, X21) of the XOR circuit 1034 obtained by calculating the exclusive OR with the output (0, 0, 0, Y8) of the D circuit 1037
C22, C23, and C24) are input to a CRC calculation circuit 1035, the CRC is calculated, and the CRC (C31, C32, C24) is calculated.
33, C34) are selected by the selection circuit 1038. Also,
The transmission data (Y8) is stored in the transmission data storage unit 102 via the selection circuit unit 104 (cycle T15).

Further, the transmission data (X5, X6, X7, X8) is read from the transmission data storage unit 102 and transmitted to the data receiving device 20 via the network 30 (cycle T15).

Next, the CRC generation unit 103
5, the output CRC of the selection circuit 1038
(C31, C32, C33, C34) are stored in the reception correspondence register 1039A, and the CRC (C31, C32, C3
3, C34) is stored in the transmission data storage unit 102 (cycle 16).

Further, the transmission data (X9, X10, X11, X12) is read from the transmission data storage unit 102,
The data is transmitted to the data receiving device 20 via the network 30 (cycle T16 in FIG. 4).

Next, the CRC generation unit 103
5 from the transmission data storage unit 102
C (D51, D52, D53, D54) is read and transmitted to the data receiving device 20 via the network 30 (cycle T17).

Next, the CRC generation unit 103
In response to the instruction from 5, the transmission data (Y1, Y2, Y3, Y4) is read from the transmission data storage unit 102 and transmitted to the data receiving device 20 via the network 30 (cycle T18).

Next, the CRC generation unit 103
In response to the instruction from 5, the transmission data (Y5, Y6, Y7, Y8) is read from the transmission data storage unit 102 and transmitted to the data receiving device 20 via the network 30 (cycle T19).

Next, the CRC generation unit 103
5 from the transmission data storage unit 102
C (C31, C32, C33, C34) is read and transmitted to the data receiving device 20 via the network 30 (cycle T20).

Next, the operation of the data receiving device 20 will be described. FIG. 5 is a time chart showing the operation of the data receiving device 20. The data receiving device 20 transmits the transmission data (X1, X2, X3, X4), (X5, X6,
X7, X8), (X9, X10, X11, X12), C
When the RC (D51, D52, D53, D54) is received, it is packed and stored in the received data storage unit 206 as received data as shown in FIG. The main storage unit 201 stores (X1, X2), (X3, X
4), (X5, X6, X7, X8), (X9, X1
0) and (X11, X12).

First, the CRC generating unit 203 of the data receiving device 20 selects the selecting circuit 10 according to an instruction from the control unit 205.
31 to the CRC initial value (all "0" values)
C, the received data (X1, X2, X3, X4) is read from the received data storage unit 206, and at the same time, the corresponding received data transmission byte valid signal (1, 1, 0, 0) is sent from the control unit 205. ) Are the transmission data register 1033 and the byte valid register 103, respectively.
6 and the output (0, 0, 0, 0) of the CRC intermediate result register 1032 and the output (X
XOR calculated by exclusive OR with (1, X2,0,0)
The output (X1, X2, 0, 0) of the circuit 1034 is selected by the selection circuit 1038. Also, transmission data (X1, X2)
Is stored in the main storage unit 201 (cycle 40 in FIG. 5).

Next, the CRC generation section 203
5, the output (X1,
X2, 0, 0) is stored in the CRC intermediate result register 1032 via the selection circuit 1031 and the next data (X1, 0, 0) is stored.
X2, X3, X4) and the received data transmission byte valid signal (0, 0, 1, 1) are stored in the transmission data register 1033 and the byte valid register 1036, respectively.
The output (X1, X2,
0, 0) and the output (0, 0, X3,
XOR circuit 1034 which calculated exclusive OR with X4)
Output (X1, X2, X3, X4) of the CRC calculation circuit 1
035, CRC is calculated, and CRC (D11, D11
12, D13, D14) are selected by the selection circuit 1038. The received data (X3, X4) is stored in the main storage unit 201.
(Cycle T41 in FIG. 5).

Next, the CRC generation section 203
5, the output of the selection circuit 1038 (D1
, D12, D13, D14) are stored in the CRC intermediate result register 1032 via the selection circuit 1031, and the next data (X5, X6, X7, X8) and the received data transmission byte valid signal (1, 1, 1, 1) are respectively assigned to the transmission data register 1033 and the byte valid register 103.
6 and outputs (D11, D12, D13, D14) of the CRC intermediate result register 1032 and the AND circuit 10
37 output (X5, X6, X7, X8) and the output (D21, D2
, D23, D24) are input to a CRC calculation circuit 1035, and the CRC is calculated, and the CRC (D31, D32, D3) is calculated.
3, D34) is selected by the selection circuit 1038. The received data (X5, X6, X7, X8) is stored in the main storage unit 201.
(Cycle T42 in FIG. 5).

Next, the CRC generation section 203
5, the output of the selection circuit 1038 (D3
, D32, D33, and D34) are stored in the CRC intermediate result register 1032 via the selection circuit 1031 and the next data (X9, X10, X11, X12) and the received data transmission byte valid signal (1, 1, (0, 0) are stored in the transmission data register 1033 and the byte valid register 1036, respectively, and the outputs (D31, D32, D33, D34) of the CRC intermediate result register 1032 and the outputs (X9, X10, 0, 0) of the AND circuit 1037 are stored. ) And the output of the XOR circuit 1034 (D41, D41
42, D33, and D34) are selected by the selection circuit 1038. The received data (X9, X10) is stored in the main storage unit 20.
1 (cycle T43 in FIG. 5).

Next, the CRC generation unit 203
5, the output of the selection circuit 1038 (D4
, D42, D33, D34) are stored in the CRC intermediate result register 1032 via the selection circuit 1031, and the next data (X9, X10, X11, X12) and the received data transmission byte valid signal (0, 0, 1, 1) are stored in the transmission data register 1033 and the byte valid register 1036, respectively, and the outputs (D41, D42, D33, D34) of the CRC intermediate result register 1032 and the outputs (0, 0, X11, X12) of the AND circuit 1037 are stored. ) And the output of the XOR circuit 1034 (D41,
D42, D43, and D44) are input to a CRC calculation circuit 1035, the CRC is calculated, and the CRC (D51, D52, D
53, D54) are selected by the selection circuit 1038. Also,
The received data (X11, X12) is stored in the main storage unit 201 (cycle T44 in FIG. 5).

Next, the data receiving device 20 checks the CRC (D
51, D52, D53, and D54) are stored in the CRC intermediate register 1032, and the output CRCs (D51, D52, D53, and D5) of the selection circuit 1038 of the CRC generation unit 203 are stored.
4) and the CRC (D51,
D52, D53, and D54) are compared by the comparison circuit unit 207, and if the comparison results match, it is determined that transmission and reception have been normally performed (cycle T45 in FIG. 5).

Similarly, in the data receiving device 40, the transmission data (Y1, Y2, Y3, Y4), (Y5, Y
6, Y7, Y8), CRC (C31, C32, C33,
C34) and the CR generated by the data receiving device 40
C is compared with the CRC received from the data transmission device 10 to check the normality of transmission and reception.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 6 shows a second embodiment of the present invention.
It is a block diagram showing an embodiment. The second embodiment of the present invention has the same configuration as that of the first embodiment of the present invention shown in FIG. 1 except that the CRC generation unit 103 and the CRC generation unit 203 are different.

Referring to FIG. 6, a CRC generation unit 103 and a CRC generation unit 203 according to the second embodiment of the present invention include a selection circuit 1031 and a CRC intermediate result register 1032.
A transmission data register 1033, an XOR circuit 1034 having an exclusive OR function, an XOR circuit 2034,
A CRC calculation circuit 1035, a CRC calculation circuit 2035,
Byte valid register 1036 and A having a logical product function
ND circuit 1037, AND circuit 2037, and selection circuit 1
038, the selection circuit 2038, and the reception correspondence register 10
39 and a reception correspondence register 103A.

Here, the transmission data register 1033 and the byte valid register 1036 are twice as large as the transmission data register 1033 and the byte valid register 1036 according to the second embodiment of the present invention (for example, 8 [bytes]). ], 8 [bits]). AND circuit 1037
The logical product of the preceding 4 bits in the byte valid register 1036 and the preceding 4 bytes in the transmission data register 1033 is expressed as AN
The D circuit 2037 calculates the logical product of the last 4 bits in the byte valid register 1036 and the last 4 bytes in the transmission data register 1033.

XOR circuit 1034 calculates the exclusive OR of the output of intermediate result register 1032 and the output of AND circuit 1037, and CRC calculation circuit 1035 calculates the CRC from the output of XOR circuit 1034, and
8 selects one of the XOR circuit 1034 and the CRC calculation circuit 1035 according to the last four bits of the preceding four bits in the byte valid register 1036.

The XOR circuit 2034 includes a selection circuit 1038
The exclusive OR of the output of the AND circuit 2037 and the output of the AND circuit 2037 is calculated.
Then, the selection circuit 2038 calculates the CRC from the output of the XOR circuit 2034 and the CRC calculation circuit 203 according to the last bit of the last 4 bits in the byte valid register 1036.
Select one of 5

The reception correspondence register 1039 and the reception correspondence register 103A hold the output of the selection circuit 2038 for each data reception device. The selection circuit 1031
Reception correspondence register 1039, reception correspondence register 103
A, output of selection circuit 2038, control unit 105, control unit 2
05, the CRC intermediate value register 1032 stores the output of the selection circuit 1031.

Although the transmission data register 1033 and the byte valid register 1036 have been described as being twice as large as described above, the transmission data register 1033 and the byte valid register 1036 may have integer times as large.

In the second embodiment of the present invention, reading from the main storage unit 101 or writing to the main storage unit 201 is different from that in the first embodiment of the present invention.
The maximum is twice as large, and accordingly, the calculation of the CRC is also doubled at the maximum, and the performance is improved.

Although the above description has been made of the case of two data receiving devices 20 and 40, the same can be realized with three or more data receiving devices.

[0075]

A first effect of the present invention is that, in a data transmitting apparatus, a CRC is efficiently generated in parallel with storing byte-based discrete data stored in a main memory in a transmission data storage unit. What you can do.

The reason is that, for data including byte data to be transmitted which can be read at once from the main memory, only the byte data to be transmitted by the AND circuit is made valid according to the transmission byte valid signal, This is because if the last byte of readable data is invalid, control is performed so as not to generate a CRC.

The second effect of the present invention is that, in parallel with storing the received data as discrete data in the main memory, the data receiving apparatus can compare the CRC and efficiently check the normality of the received data. It is.

The reason is that according to the received byte valid signal, only the byte data that can be written to the main memory at once by the AND circuit is made valid, and if the last byte of the data that can be written at one time is invalid, the CRC is not generated. Because you do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a detailed block diagram illustrating a CRC generator of FIG. 1;

FIG. 3 is an explanatory diagram showing an array of transmission data and reception data.

FIG. 4 is a time chart illustrating the operation of the first exemplary embodiment of the present invention.

FIG. 5 is a time chart illustrating an operation of the first exemplary embodiment of the present invention.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 data transmission device 20 data reception device 30 network 40 data reception device 101 main storage unit 102 transmission data storage unit 103 CRC generation unit 104 selection circuit unit 105 control unit 201 main storage unit 203 CRC generation unit 205 control unit 206 reception data storage unit 207 Comparison circuit section 1031 Selection circuit 1032 CRC intermediate result register 1033 Transmission data register 1034 XOR circuit 1035 CRC calculation circuit 1036 Byte valid register 1037 AND circuit 1038 Selection circuit 1039 Reception correspondence register 103A Reception correspondence register 2034 XOR circuit 2035 CRC calculation circuit 2037 AND Circuit 2038 Selection circuit

Claims (8)

[Claims] 1. A transmission data register for storing transmission data including valid byte data to be transmitted, and (b) a byte valid signal in a byte unit indicating validity / invalidity of each byte of the transmission data. A byte valid register;
(C) an AND circuit for calculating the logical product of the output of the transmission data register and the output of the byte valid register;
(D) CRC for storing intermediate results or initial values of CRC
An intermediate result register, (e) an XOR circuit for generating an exclusive OR of an output of the CRC intermediate result register and an output of the AND circuit, and (f) a CRC calculation circuit for generating a CRC from the output of the XOR circuit. And (g) selecting the output of the CRC calculation circuit when the byte valid signal for the last byte of the byte valid register indicates valid,
(H) a first selection circuit for selecting the output of the XOR circuit when the byte valid signal for the last byte indicates invalid, and outputting the result as an intermediate or final result of the CRC;
One or more reception correspondence registers for holding the output of the first selection circuit corresponding to the data receiving device; and (i) an intermediate result of the CRC of the output of the first selection circuit, the output of the one or more reception correspondence registers. A second selecting circuit for selecting any of the CRC intermediate values and the initial value of the CRC and outputting the selected value to the CRC intermediate result register.
RC generator. 2. A data transmitting apparatus having the CRC generating section according to claim 1, wherein the data transmitting apparatus adds a CRC generated by the CRC generating section to transmission data and transmits the data, and (b) the data transmitting apparatus. Data and CRC transmitted from
And (c) having the CRC generating unit according to claim 1, receiving, as reception data, transmission data from the data transmission device transferred via the network, and receiving a CRC. From the data, the CR
A CRC calculation device comprising: at least one data reception device that compares a CRC generated by a C generation unit with a received CRC and checks the normality of received data. 3. A main storage unit for storing transmission data in discrete byte units, a transmission data storage unit, the CRC generation unit according to claim 1, a selection circuit unit, and a control unit,
(A) data including valid transmission data read at once from the main storage unit is sequentially stored via the selection circuit according to an instruction of the control unit, and only valid data is stored;
Next, the transmission data storage unit for storing a CRC from the CRC generation unit, and (b) byte validity data from the control unit for data including valid transmission data once read from the main storage unit. A CRC generating unit that generates a CRC according to a signal; and (c) the selecting circuit unit that selects one of data from the main memory and a CRC from the CRC generating unit according to an instruction from the control unit. , (D)
3. The data transmission device according to claim 2, further comprising: the control unit configured to transmit transmission data and a CRC from the transmission data storage unit to the one or more data reception devices via the network. CRC calculator. 4. A main storage unit for storing reception data in discrete bytes, a reception data storage unit, the CRC generation unit according to claim 1, a comparison circuit unit, and a control unit,
(A) the reception data storage unit that stores transmission data transferred from the data transmission device via the network as reception data, and stores a CRC transferred from the data transmission device via the network;
(B) The CRC for generating a CRC according to a byte valid signal from the control unit with respect to data including data to be written at once from the reception data storage unit to the main storage unit.
A generation unit; (c) a comparison circuit unit that compares a CRC from the CRC generation unit with a CRC from the received data storage unit in accordance with an instruction from the control unit; and (d) the comparison circuit unit. 4. The CRC calculation device according to claim 2, further comprising: the data receiving device including: the control unit that determines that the received data is normal if the comparison result in the above is identical. 5. When the byte length of data read at one time from the main storage unit is an integral multiple of the byte length of data that can be written to the transmission data storage unit at one time, the AND circuit, the XOR circuit, and the CRC 2. The circuit according to claim 1, wherein the calculation circuit and the first selection circuit have an integral multiple.
RC generator. 6. A data transmission device having the CRC generation unit according to claim 5, wherein the data transmission device adds the CRC generated by the CRC generation unit to transmission data and transmits the data. (B) The data transmission device. Data and CRC transmitted from
And (c) the CRC generation unit according to claim 5, wherein the transmission data transmitted from the data transmission device via the network is received as data, and a CRC is received. From the data, the CR
A CRC calculation device comprising: at least one data reception device that compares a CRC generated by a C generation unit with a received CRC and checks the normality of received data. 7. A main storage unit for storing discrete transmission data in byte units, a transmission data storage unit, the CRC generation unit according to claim 5, a selection circuit unit, and a control unit,
(A) data including valid transmission data read at once from the main storage unit is sequentially stored via the selection circuit according to an instruction of the control unit, and only valid data is stored;
Next, the transmission data storage unit for storing a CRC from the CRC generation unit, and (b) byte validity data from the control unit for data including valid transmission data once read from the main storage unit. A CRC generating unit that generates a CRC according to a signal; and (c) the selecting circuit unit that selects one of data from the main memory and a CRC from the CRC generating unit according to an instruction from the control unit. , (D)
7. The data transmission device according to claim 6, further comprising: the control unit configured to transmit transmission data and a CRC from the transmission data storage unit to the one or more data reception devices via the network. CRC calculator. 8. A main storage unit for storing discrete reception data in byte units, a reception data storage unit, the CRC generation unit according to claim 5, a comparison circuit unit, and a control unit,
(A) the reception data storage unit that stores transmission data transferred from the data transmission device via the network as reception data, and stores a CRC transferred from the data transmission device via the network;
(B) The CRC for generating a CRC according to a byte valid signal from the control unit with respect to data including data to be written at once from the reception data storage unit to the main storage unit.
A generation unit; (c) a comparison circuit unit that compares a CRC from the CRC generation unit with a CRC from the received data storage unit in accordance with an instruction from the control unit; and (d) the comparison circuit unit. 8. The CRC calculation device according to claim 6, further comprising: the data reception device including: the control unit that determines that the received data is normal if the comparison result in the above is matched.