JP2001053412A - Chip-mounting module - Google Patents
Chip-mounting moduleInfo
- Publication number
- JP2001053412A JP2001053412A JP22793799A JP22793799A JP2001053412A JP 2001053412 A JP2001053412 A JP 2001053412A JP 22793799 A JP22793799 A JP 22793799A JP 22793799 A JP22793799 A JP 22793799A JP 2001053412 A JP2001053412 A JP 2001053412A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- opening
- bump
- chip mounting
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多層プリント基板
を使用したバンプ接続方式のチップ実装モジュールに関
し、特にチップの埋め込み実装を可能にしたチップ実装
モジュールに関する。本発明はまた、埋め込み実装され
たチップからの熱を効率良く放熱する構造を有したチッ
プ実装モジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip mounting module of a bump connection type using a multilayer printed circuit board, and more particularly to a chip mounting module capable of embedding and mounting a chip. The present invention also relates to a chip mounting module having a structure for efficiently radiating heat from an embedded chip.
【０００２】[0002]
【従来の技術】従来、フレキシブル・プリント基板（Ｆ
ＰＣ）上にＬＳＩ部品を実装する場合は、図２の断面図
に示すように、ＩＣベアチップ１０を電極１１を上に向
けてＦＰＣ基板２０上に搭載し、チップ電極１１とＦＰ
Ｃ基板電極２１との間をＡｕ線３０でワイヤボンディン
グしてから全体を樹脂３１で封止するＣＯＢ（チップ・
オン・ボード）方式が主流であった。2. Description of the Related Art Conventionally, flexible printed circuit boards (F
When mounting LSI components on a PC), the IC bare chip 10 is mounted on the FPC board 20 with the electrode 11 facing upward as shown in the cross-sectional view of FIG.
A COB (chip chip) is formed by wire bonding with the C substrate electrode 21 with the Au wire 30 and then sealing the whole with the resin 31.
The on-board method was the mainstream.
【０００３】一方、最近では、回路の高密度化に伴い、
ＢＧＡ（ボール・グリッド・アレイ）、ＣＳＰ（チップ
・サイズド・パッケージ）、フリップチップなど、チッ
プ下面に電極を配置したバンプ接続方式が採用されるよ
うになってきた。図３はこの一例を示す断面図である。
ベアチップ１０は下面に電極１１を向けて配置され、Ｆ
ＰＣ基板２０の電極２１との間にボール等のバンプ３２
を介在させて接続される。On the other hand, recently, with the increase in circuit density,
A bump connection method, such as BGA (ball grid array), CSP (chip sized package), or flip chip, in which electrodes are arranged on the lower surface of a chip has been adopted. FIG. 3 is a cross-sectional view showing this example.
The bare chip 10 is arranged with the electrode 11 facing the lower surface, and F
Bumps 32 such as balls between the electrodes 21 of the PC board 20
Connected.
【０００４】[0004]
【発明が解決しようとする課題】フリップチップ実装工
法では、ＩＣ電極１１のピッチと同ピッチで基板電極２
１を対向させる必要があるため、微細パターンの形成は
不可避の課題となる。ところが、ＦＰＣ基板２０に両面
（２層）タイプを使用し、表面（上層）回路パターンに
チップを実装する場合、裏面（下層）回路パターンの凹
凸の影響が表面回路にも影響する。そこで、チップ実装
部の下側に位置する裏面回路部分を、ベタパターンのラ
ンドにすることが一般的であり、その部分が回路パター
ン引き回しの支障になる。In the flip chip mounting method, the substrate electrodes 2 are arranged at the same pitch as the pitch of the IC electrodes 11.
1 must be opposed to each other, so that formation of a fine pattern is inevitable. However, when a double-sided (two-layer) type is used for the FPC board 20 and a chip is mounted on the front (upper layer) circuit pattern, the influence of the unevenness of the rear (lower) circuit pattern also affects the front surface circuit. Therefore, it is common to make the back surface circuit portion located below the chip mounting portion a land of a solid pattern, and this portion hinders the circuit pattern routing.
【０００５】また、チップ実装部におけるチップと回路
パターンとの接続部分の周囲には電極間の短絡を防止す
るためのレジストを使用するが、微細パターンであるた
めにレジスト材料の選定、塗布方法の検討を含めて、製
造プロセスに困難な問題を生じさせる。Further, a resist for preventing a short circuit between electrodes is used around a connection portion between a chip and a circuit pattern in a chip mounting portion. However, since the resist is a fine pattern, selection of a resist material and application of a coating method are required. It creates difficult problems in the manufacturing process, including review.
【０００６】更に、フリップチップ実装では、ＩＣチッ
プ１０の背面が上向きになって断熱性の高い空気中に露
出するため、放熱特性上は不利である。このため従来
は、ＩＣチップ１０の背面上に放熱フィン等の放熱部品
を熱伝導性接着剤で接着して放熱性を改善している。し
かしながら、チップ１０の上側から放熱部品を接着する
工法は、放熱部品の重量によってチップ自体およびその
下面の実装部に機械的応力が加わるため、実装部の変
形、破壊の原因となる。Further, in flip-chip mounting, since the back surface of the IC chip 10 faces upward and is exposed to air having high heat insulating properties, it is disadvantageous in terms of heat radiation characteristics. Therefore, conventionally, a heat radiating component such as a heat radiating fin is adhered on the back surface of the IC chip 10 with a heat conductive adhesive to improve heat radiating property. However, the method of bonding the heat dissipating component from the upper side of the chip 10 causes mechanical stress to be applied to the chip itself and the mounting portion on the lower surface thereof due to the weight of the heat dissipating component, thereby causing deformation and destruction of the mounting portion.
【０００７】本発明の１つの目的は、全体を薄型化可能
なバンプ接続方式のチップ実装モジュールを提供するこ
とにある。本発明の他の目的は、チップ実装部にレジス
トを必要としないバンプ接続方式のチップ実装モジュー
ルを提供することにある。本発明の更に他の目的は、実
装されたチップの発熱を効率良く放熱できるバンプ接続
方式のチップ実装モジュールを提供することにある。It is an object of the present invention to provide a bump mounting type chip mounting module which can be made thinner as a whole. Another object of the present invention is to provide a bump mounting type chip mounting module which does not require a resist in a chip mounting portion. Still another object of the present invention is to provide a bump connection type chip mounting module capable of efficiently radiating heat generated from a mounted chip.
【０００８】[0008]
【課題を解決するための手段】本発明のチップ実装モジ
ュールは、層間絶縁層を介在させた少なくとも上層導電
層と下層導電層を有し、チップ実装部が形成された多層
構造のプリント基板と、前記プリント基板のチップ実装
部にバンプ接続方式により実装されるバンプ部が形成さ
れたチップとを備えたチップ実装モジュールであって、
前記チップ実装部は、前記上層導電層に前記チップと適
合するチップ開口部を形成すると共に、このチップ開口
部から露出する前記層間絶縁層に前記チップのバンプ部
に適合するバンプ開口部を形成して、このバンプ開口部
から前記下層導電層を露出させることにより形成され、
前記チップを前記チップ開口部に埋め込んで実装するも
のであることを特徴とする。A chip mounting module according to the present invention has a multilayer printed circuit board having at least an upper conductive layer and a lower conductive layer with an interlayer insulating layer interposed, and having a chip mounting portion formed thereon. A chip mounting module comprising: a chip having a bump portion formed by a bump connection method on a chip mounting portion of the printed board,
The chip mounting portion forms a chip opening compatible with the chip in the upper conductive layer, and forms a bump opening compatible with the bump portion of the chip in the interlayer insulating layer exposed from the chip opening. Formed by exposing the lower conductive layer from the bump opening,
The chip is mounted by being embedded in the chip opening.
【０００９】好ましい実施の形態では、前記ベアチップ
の下部空間に充填される封止材を更に備える。また、前
記バンプ開口部によって露出した前記下層導電層の表面
は、前記チップを実装するランドとして機能するための
表面処理が施されていることが望ましい。In a preferred embodiment, the apparatus further comprises a sealing material filled in a lower space of the bare chip. Preferably, the surface of the lower conductive layer exposed by the bump opening is subjected to a surface treatment for functioning as a land for mounting the chip.
【００１０】本発明の好ましい他の実施の形態では、前
記チップ実装部のチップ開口部とほぼ等しい開口部を有
して前記プリント基板上に配置された平板状の放熱板
と、前記放熱板の開口部内壁と前記チップの側面との間
に充填された熱伝導性接着剤とを更に備える。この場
合、前記放熱板の厚みは、前記放熱板の上面が前記チッ
プ実装部に実装された前記ベアチップの上面より高くな
るように設定されていることが望ましい。In another preferred embodiment of the present invention, a flat plate-shaped heat sink having an opening substantially equal to the chip opening of the chip mounting portion and arranged on the printed circuit board; The semiconductor device further includes a heat conductive adhesive filled between the inner wall of the opening and the side surface of the chip. In this case, it is desirable that the thickness of the heat sink is set so that the upper surface of the heat sink is higher than the upper surface of the bare chip mounted on the chip mounting portion.
【００１１】本発明のチップ実装モジュールによれば、
プリント基板の一部が層間絶縁層まで除去されてチップ
開口部を形成し、層間絶縁層の一部が更に除去されてバ
ンプ開口部を形成することにより、チップ実装部が形成
されているので、チップのバンプ部は、下層導電層と接
続されることになる。これにより、上層導電層と接続さ
れた従来例のように、下層導電層の凹凸がチップとの接
続部に影響を与えることがなく、下層導電層をベタパタ
ーンにする必要もなくなるうえ、チップが基板内に埋め
込まれることにより、薄型化が達成される。また、本発
明によれば、層間絶縁層が電極間の短絡を防止するレジ
ストとして機能するので、従来のようなレジストを形成
する必要が無く、これにより製造プロセスが簡単にな
る。According to the chip mounting module of the present invention,
Since a part of the printed circuit board is removed to the interlayer insulating layer to form a chip opening, and a part of the interlayer insulating layer is further removed to form a bump opening, so that a chip mounting part is formed. The bump portion of the chip is connected to the lower conductive layer. Thereby, unlike the conventional example connected to the upper conductive layer, the unevenness of the lower conductive layer does not affect the connection portion with the chip, and it is not necessary to form the lower conductive layer as a solid pattern. By being embedded in the substrate, a reduction in thickness is achieved. Further, according to the present invention, since the interlayer insulating layer functions as a resist for preventing a short circuit between the electrodes, there is no need to form a conventional resist, thereby simplifying a manufacturing process.
【００１２】[0012]
【発明の実施の形態】以下、図面に示した実施形態を参
照して、本発明を詳細に説明する。図１は、本発明の一
実施形態を示す断面図である。この実施形態のチップ実
装モジュールでは、上層導電パターン層５１と下層導電
パターン層５２を有した両面（２層）ＦＰＣ基板５０を
使用している。両面ＦＰＣ５０は、上層導電層５１と下
層導電層５２の間に層間絶縁層５３を介在させ、更に下
層導電層５２の下にも裏面絶縁層５４を設けて一体化し
たものである。絶縁層５３，５４の素材は、ポリイミド
等の樹脂である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments shown in the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention. In the chip mounting module of this embodiment, a double-sided (two-layer) FPC board 50 having an upper conductive pattern layer 51 and a lower conductive pattern layer 52 is used. The double-sided FPC 50 has a structure in which an interlayer insulating layer 53 is interposed between an upper conductive layer 51 and a lower conductive layer 52, and a back insulating layer 54 is further provided below the lower conductive layer 52. The material of the insulating layers 53 and 54 is a resin such as polyimide.
【００１３】この両面ＦＰＣ基板５０の上層導電層５１
の一部をエッチングして、実装されるチップ１０の外径
に適合するチップ開口部５１Ａを形成する。次いで、そ
の下の層間絶縁層５３に、チップ１０のバンプ３２に適
合するように、レーザ加工でバンプ開口部５３Ａを形成
し、下層導電層５２の一部を露出することで、バンプ接
続方式のチップ実装部２３を形成する。バンプ開口部５
３Ａによって下層導電層５２の一部露出した部分の表面
は、バンプ接続用のランドとなるように、メッキ等の表
面処理が施されている。そしてバンプ開口部５３Ａの周
囲の層間絶縁層５３，５３Ｂ、即ち開口されなかった部
分が均一な厚みを持ったレジストとして機能する。The upper conductive layer 51 of the double-sided FPC board 50
Is etched to form a chip opening 51A that matches the outer diameter of the chip 10 to be mounted. Next, a bump opening 53A is formed in the interlayer insulating layer 53 therebelow by laser processing so as to be compatible with the bump 32 of the chip 10, and a part of the lower conductive layer 52 is exposed, thereby forming a bump connection type. The chip mounting part 23 is formed. Bump opening 5
The surface of the portion of the lower conductive layer 52 that is partially exposed by 3A is subjected to a surface treatment such as plating so as to be a land for bump connection. The interlayer insulating layers 53 and 53B around the bump opening 53A, that is, the unopened portions function as a resist having a uniform thickness.
【００１４】チップ実装部２３にはベアチップ１０がバ
ンプ３２を介して接続される。ベアチップ１０は、代表
的にはフリップチップである。ベアチップ１０の下部空
間は、封止材６０、例えばエポキシ樹脂が充填され、耐
環境性が改善される。ベアチップ１０の下部空間には層
間絶縁層５３Ｂが残っているので、この層間絶縁層５３
Ｂにより封止材６０の充填量を少なくすることができ
る。また、チップ開口部５１Ａにパスコン等のＳＭＴ
（面実装部品）を搭載可能である。The bare chip 10 is connected to the chip mounting section 23 via bumps 32. The bare chip 10 is typically a flip chip. The lower space of the bare chip 10 is filled with a sealing material 60, for example, an epoxy resin, so that environmental resistance is improved. Since the interlayer insulating layer 53B remains in the lower space of the bare chip 10, the interlayer insulating layer 53B
With B, the filling amount of the sealing material 60 can be reduced. Also, an SMT such as a bypass capacitor is inserted into the chip opening 51A.
(Surface mount components) can be mounted.
【００１５】ＦＰＣ基板５０の上側には、ボンディング
シート７０を介して平板状の放熱板８０が配置される。
放熱板８０は、例えばＡｌ素材で、チップ実装部２３に
合わせた開口部８１を有する。この放熱板開口部８１の
内壁とチップ１０の側面との間にはシリコーン等の熱伝
導性接着剤９０が充填される。この放熱構造は、チップ
１０の発熱を接着剤９０を介して放熱板８０に伝達して
放熱する。従って、チップ１０の上には応力を加える放
熱部品は存在しないので、ベアチップ１０及びチップ実
装部２３が変形または破壊されることがない。また、封
止材６０がＩＣ実装自体の信頼性を確保しているので、
接着剤９０は熱伝導性にのみ着目して選択できる。On the upper side of the FPC board 50, a flat heat sink 80 is disposed via a bonding sheet 70.
The heat sink 80 has an opening 81 made of, for example, an Al material and adapted to the chip mounting portion 23. A space between the inner wall of the heat sink opening 81 and the side surface of the chip 10 is filled with a heat conductive adhesive 90 such as silicone. In this heat dissipation structure, heat generated by the chip 10 is transmitted to the heat dissipation plate 80 via the adhesive 90 to dissipate heat. Therefore, since there is no heat dissipating component for applying stress on the chip 10, the bare chip 10 and the chip mounting portion 23 are not deformed or broken. Further, since the sealing material 60 secures the reliability of the IC mounting itself,
The adhesive 90 can be selected by focusing only on the thermal conductivity.
【００１６】放熱板８０の表面は、チップ１０の上向き
の面（チップ背面）より僅かに高くなるように設定され
ている。従って、チップ１０はチップ実装部２３内に完
全に埋設された形になり、全体を薄型化できる。必要で
あれば追加的に放熱フィンのような２次放熱部品を使用
することができる。この２次放熱部品は放熱板８０の上
に良好な密着性をもって搭載できる。２次放熱部品はチ
ップ実装部２３から横方向にずれた位置に搭載されるの
で、チップ１０およびチップ実装部２３に応力を加える
ことがない。The surface of the heat sink 80 is set to be slightly higher than the upward surface of the chip 10 (chip back surface). Therefore, the chip 10 is completely buried in the chip mounting portion 23, and the entire thickness can be reduced. If necessary, a secondary heat radiating component such as a heat radiating fin can be additionally used. This secondary heat radiating component can be mounted on the heat radiating plate 80 with good adhesion. Since the secondary heat radiating component is mounted at a position shifted laterally from the chip mounting portion 23, no stress is applied to the chip 10 and the chip mounting portion 23.
【００１７】チップ実装部に適用されうるバンプ接続方
式は、フリップチップ型だけでなくボールグリッドアレ
イ型またはチップサイズパッケージ型でもよい。本発明
のチップ実装モジュールは、小型化、薄型化が要求され
る電子機器、例えばＰＤＰ（プラズマ・ディスプレイ・
パネル）に適用することができる。この他にも、高電
圧、高密度なバンプ実装品（フリップチップ実装品）に
適用可能である。また、使用する多層プリント基板は、
ＦＰＣに限らず、ＲＰＣ（リジット・プリント基板）で
もよい。The bump connection method applicable to the chip mounting portion may be not only a flip chip type but also a ball grid array type or a chip size package type. The chip mounting module of the present invention is an electronic device that is required to be small and thin, for example, a PDP (plasma display device).
Panel). In addition, the present invention can be applied to high-voltage, high-density bump-mounted products (flip-chip mounted products). The multilayer printed circuit board used is
Not limited to FPC, RPC (rigid printed circuit board) may be used.
【００１８】[0018]
【発明の効果】以上述べた本発明のチップ実装モジュー
ルによると、次の利点がある。 （１）チップが基板内部に埋め込まれるため、モジュー
ル全体が軽量化、小型化（特に薄型化）される。 （２）微細パターンに対応するレジスト層を形成する必
要がないため、製造プロセスが簡単になる。 （３）チップおよびチップ実装部上に放熱部品を配置す
ることなく、放熱できる。 （４）放熱板の表面をＩＣチップの上向きの面より僅か
に高くすることによって、２次放熱板が取り付け易くな
る。According to the chip mounting module of the present invention described above, there are the following advantages. (1) Since the chip is embedded in the substrate, the entire module is reduced in weight and size (particularly, reduced in thickness). (2) Since there is no need to form a resist layer corresponding to the fine pattern, the manufacturing process is simplified. (3) Heat can be dissipated without disposing heat dissipating components on the chip and the chip mounting portion. (4) By making the surface of the heat sink slightly higher than the upward surface of the IC chip, the secondary heat sink can be easily attached.
【図１】 本発明の一実施形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】 従来のＣＯＢ方式のチップ実装を示す断面図
である。FIG. 2 is a cross-sectional view showing a conventional COB chip mounting.
【図３】 従来のバンプ接続方式のチップ実装を示す断
面図である。FIG. 3 is a cross-sectional view showing a conventional bump connection type chip mounting.
１０…ベアチップ、２３…チップ実装部、３２…バン
プ、５０…両面ＦＰＣ、５１…上層（表面）導電層、５
１Ａ…チップ開口部、５２…下層（裏面）導電層、５
３，５３Ｂ…層間絶縁層、５３Ａ…バンプ開口部、５４
…裏面絶縁層、６０…封止材、７０…ボンディングシー
ト、８０…放熱板、８１・・開口、９０…熱伝導性接着
剤。10: bare chip, 23: chip mounting portion, 32: bump, 50: double-sided FPC, 51: upper layer (surface) conductive layer, 5
1A: Chip opening, 52: Lower (back) conductive layer, 5
3, 53B: interlayer insulating layer; 53A: bump opening;
... back insulating layer, 60 ... sealing material, 70 ... bonding sheet, 80 ... heat sink, 81 ... opening, 90 ... heat conductive adhesive.
─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成１２年４月２８日（２０００．４．２
８）[Submission date] April 28, 2000 (200.4.2
8)
【手続補正１】[Procedure amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】特許請求の範囲[Correction target item name] Claims
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【特許請求の範囲】[Claims]
【手続補正２】[Procedure amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００８[Correction target item name] 0008
【補正方法】変更[Correction method] Change
【補正内容】[Correction contents]
【０００８】[0008]
【課題を解決するための手段】本発明のチップ実装モジ
ュールは、層間絶縁層を介在させた少なくとも上層導電
層と下層導電層を有し、チップ実装部が形成された多層
構造のプリント基板と、前記プリント基板のチップ実装
部にバンプ接続方式により実装されるバンプ部が形成さ
れたチップと、前記プリント基板上に配置された平板状
の放熱板とを備えたチップ実装モジュールであって、前
記チップ実装部は、前記上層導電層に前記チップと適合
するチップ開口部を形成すると共に、このチップ開口部
から露出する前記層間絶縁層に前記チップのバンプ部に
適合するバンプ開口部を形成して、このバンプ開口部か
ら前記下層導電層を露出させることにより形成され、前
記チップをその上面が前記上層導電層よりも上に突出す
るように前記チップ開口部に埋め込んで実装するもので
あり、前記放熱板は、前記チップ実装部のチップ開口部
とほぼ等しい開口部を有し、且つその上面が前記チップ
実装部に実装された前記チップの上面より僅かに高くな
るように設定された厚みを有するものであり、前記放熱
板の開口部内壁と前記チップの側面との間には熱伝導性
接着剤が充填されていることを特徴とする。A chip mounting module according to the present invention has a multilayer printed circuit board having at least an upper conductive layer and a lower conductive layer with an interlayer insulating layer interposed, and having a chip mounting portion formed thereon. A chip on which a bump portion is mounted on the chip mounting portion of the printed board by a bump connection method, and a flat plate disposed on the printed board.
A chip mounting module, comprising: a heat sink; and a chip mounting portion, wherein the chip mounting portion forms a chip opening compatible with the chip in the upper layer conductive layer, and forms the chip insulating portion on the interlayer insulating layer exposed from the chip opening. The chip is formed by forming a bump opening corresponding to the bump of the chip and exposing the lower conductive layer from the bump opening, and the upper surface of the chip projects above the upper conductive layer.
Said chip Ri those in <br/> Ah for embedded mounting in openings so that, the heat sink, the chip opening of said chip mounting portion
Having an opening substantially equal to
Slightly higher than the upper surface of the chip mounted on the mounting part
Having a thickness set so that the heat dissipation
Thermal conductivity between the inner wall of the plate opening and the side of the chip
It is characterized by being filled with an adhesive .
【手続補正３】[Procedure amendment 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１０[Correction target item name] 0010
【補正方法】削除[Correction method] Deleted
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E336 AA08 BB03 BC25 CC43 CC58 EE07 GG03 5E338 AA03 BB02 BB19 BB22 CC08 EE02 EE31 5F044 KK03 KK10 KK23 LL11 QQ01 RR10 RR12 RR18 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E336 AA08 BB03 BC25 CC43 CC58 EE07 GG03 5E338 AA03 BB02 BB19 BB22 CC08 EE02 EE31 5F044 KK03 KK10 KK23 LL11 QQ01 RR10 RR12 RR18
Claims (5)
導電層と下層導電層を有し、チップ実装部が形成された
多層構造のプリント基板と、 前記プリント基板のチップ実装部にバンプ接続方式によ
り実装されるバンプ部が形成されたチップとを備えたチ
ップ実装モジュールであって、 前記チップ実装部は、前記上層導電層に前記チップと適
合するチップ開口部を形成すると共に、このチップ開口
部から露出する前記層間絶縁層に前記チップのバンプ部
に適合するバンプ開口部を形成して、このバンプ開口部
から前記下層導電層を露出させることにより形成され、
前記チップを前記チップ開口部に埋め込んで実装するも
のであることを特徴とするチップ実装モジュール。1. A printed circuit board having a multilayer structure having at least an upper conductive layer and a lower conductive layer with an interlayer insulating layer interposed therebetween and having a chip mounting part formed thereon, and a bump connection method to the chip mounting part of the printed board. A chip mounting module comprising: a chip on which a bump portion to be mounted is formed, wherein the chip mounting portion forms a chip opening compatible with the chip in the upper conductive layer, Forming a bump opening corresponding to the bump of the chip in the exposed interlayer insulating layer, and exposing the lower conductive layer from the bump opening;
A chip mounting module, wherein the chip is mounted by being embedded in the chip opening.
材を更に備えたことを特徴とする請求項１記載のチップ
実装モジュール。2. The chip mounting module according to claim 1, further comprising a sealing material filled in a lower space of said chip.
下層導電層の表面は、前記チップを実装するランドとし
て機能するための表面処理が施されていることを特徴と
する請求項１記載のチップ実装モジュール。3. The chip mounting according to claim 1, wherein the surface of the lower conductive layer exposed by the bump opening is subjected to a surface treatment for functioning as a land for mounting the chip. module.
等しい開口部を有して前記プリント基板上に配置された
平板状の放熱板と、 前記放熱板の開口部内壁と前記チップの側面との間に充
填された熱伝導性接着剤とを更に備えたことを特徴とす
る請求項１〜３のいずれか１項記載のチップ実装モジュ
ール。4. A flat plate-shaped heat sink having an opening substantially equal to a chip opening of the chip mounting portion and disposed on the printed circuit board; an inner wall of the opening of the heat sink and a side surface of the chip. The chip mounting module according to any one of claims 1 to 3, further comprising a heat conductive adhesive filled between the two.
が前記チップ実装部に実装された前記ベアチップの上面
より高くなるように設定されていることを特徴とする請
求項４記載のチップ実装モジュール。5. The chip according to claim 4, wherein the thickness of the heat sink is set so that the upper surface of the heat sink is higher than the upper surface of the bare chip mounted on the chip mounting portion. Implementation module.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22793799A JP3182138B2 (en) | 1999-08-11 | 1999-08-11 | Chip mounting module |
| TW089115363A TW561799B (en) | 1999-08-11 | 2000-08-01 | Chip assembly module of bump connection type using a multi-layer printed circuit substrate |
| EP00402237A EP1076361B1 (en) | 1999-08-11 | 2000-08-07 | Chip assembly module of bump connection type using a multi-layer printed circuit substrate |
| US09/635,338 US6442043B1 (en) | 1999-08-11 | 2000-08-09 | Chip assembly module of bump connection type using a multi-layer printed circuit substrate |
| KR1020000046431A KR100768998B1 (en) | 1999-08-11 | 2000-08-10 | Chip Assembly Module of Bump Connection Type Using a Multi-layer Printed Circuit Substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22793799A JP3182138B2 (en) | 1999-08-11 | 1999-08-11 | Chip mounting module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001053412A true JP2001053412A (en) | 2001-02-23 |
| JP3182138B2 JP3182138B2 (en) | 2001-07-03 |
Family
ID=16868631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22793799A Expired - Fee Related JP3182138B2 (en) | 1999-08-11 | 1999-08-11 | Chip mounting module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3182138B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007123617A (en) * | 2005-10-28 | 2007-05-17 | Toshiba Corp | Printed wiring board, electronic apparatus incorporating printed wiring board, and process for producing printed wiring board |
| JP2008021819A (en) * | 2006-07-13 | 2008-01-31 | Matsushita Electric Ind Co Ltd | Heat conducting base board, manufacturing method thereof, power supply unit, and electronic equipment |
| JP2013051432A (en) * | 2012-10-25 | 2013-03-14 | Toshiba Corp | Electronic apparatus, electronic component, and manufacturing method of substrate assembly |
-
1999
- 1999-08-11 JP JP22793799A patent/JP3182138B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007123617A (en) * | 2005-10-28 | 2007-05-17 | Toshiba Corp | Printed wiring board, electronic apparatus incorporating printed wiring board, and process for producing printed wiring board |
| JP2008021819A (en) * | 2006-07-13 | 2008-01-31 | Matsushita Electric Ind Co Ltd | Heat conducting base board, manufacturing method thereof, power supply unit, and electronic equipment |
| JP2013051432A (en) * | 2012-10-25 | 2013-03-14 | Toshiba Corp | Electronic apparatus, electronic component, and manufacturing method of substrate assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3182138B2 (en) | 2001-07-03 |
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