JP2001045073A - Ternary signal transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance reliability of a ternary signal transmission system without deteriorating transmission efficiency by restoring a change in one or other logic level of data through reception of input of a positive or negative pulse signal and identifying that the data include any error through the reception of continuous inputs of either of the positive and negative pulse signals. SOLUTION: A digital differentiation circuit DEF1 converts binary internal output data received from a host computer HOST into a ternary output differentiated signal consisting positive and negative pulse signals, a ternary value decoding circuit 3VC2 decodes the ternary input differentiated signal received from the digital differentiation circuit DEF1 into binary internal output data, which are fed to a digital terminal device through a bus cable BC. Similarly a digital differentiation circuit DEF 2 transmits binary internal input data received from the digital terminal device through the bus cable BC to the host computer HOST.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary signal transmission device, for example, a bus connection device for connecting an IEEE-1394 bus cable to a host computer or a peripheral device, and a digital system including them. The present invention relates to a technique that is particularly effective for improving the reliability.

[0002]

2. Description of the Related Art A so-called IE capable of transferring data at a high speed of 100 Mbps (megabit / second) or more between a host computer and a digital terminal device including various peripheral devices.
There is an EE (EiEiEi) -1394 system. In the IEEE-1394 system, the distance between each device is 2
The paired signal lines are connected to each other via a bus cable composed of a power supply line and a ground (GND) line. However, AC coupling is recommended from the viewpoint of separating and absorbing a potential difference between the devices. For this reason, a link (LINK) provided as an interface circuit on a system side such as a host computer is provided.
Chip and the physical (P
AC coupling means such as a coil or a capacitor is provided between the chip and the HY) chip. In order to support data transfer during this time, a method is used in which digital data is differentiated and processed as a ternary signal.

On the other hand, as one means for detecting and correcting errors in digital data transmitted and received between apparatuses and improving the reliability of the system, for example, a CRC (Cyclic Red) is used.
There is an error correction method using a non-operating check code.

The IEEE-1394 system and its AC coupling method are described, for example, in “IEEE STANDAR”.
D FOR A HIGH PERFORMANCE
SERIAL BUS (IEE Standard for Hyper-Performance Serial Bus), IEEE Std 1394-1995, pp. 245 and 347-348.

[0005]

Prior to the present invention, the inventors of the present invention have proposed various digital devices and the above-mentioned IEEE-1
Engaged in the development of a bus connection device for connecting to a 394 system bus cable, and noticed the following problems.
That is, as shown in FIG. 9, for example, this bus connection device includes a link chip LINK provided on a digital device side such as a host computer HOST, a physical chip PHY provided on a bus cable BC side, and a link chip It comprises a pair of digital differentiating circuits DEF1 and DEF2 and Schmitt circuits SCH1 and SCH2 provided between physical chips, respectively, and a capacitor C serving as AC coupling means.

For example, a digital signal transmitted from the host computer HOST via the link chip LINK, that is, the internal output data DO is, as shown in FIG. 10, by a digital differentiating circuit DEF1 on the link chip LINK side of the bus connection device. It is converted into a ternary output differential signal DEFO comprising a positive pulse signal formed in response to the rise to the high level and a negative pulse signal formed in response to the fall to the low level. The output differential signal DEFO is transmitted to the Schmitt circuit SCH2 on the physical chip PHY side through an AC coupling means such as a capacitor C and is restored to a binary digital signal, and thereafter, is output to the IEEE via the physical chip PHY.
Output to the -1394 bus cable BC.

[0007] On the other hand, a not-shown partner terminal transmits an IEEE
A binary digital signal input via a −1394 bus cable BC is converted into a ternary differential signal by a digital differentiating circuit DEF2 on the physical chip PHY side, and after passing through an AC coupling means such as a capacitor C, The input differential signal DEFI is input to the Schmitt circuit SCH1 on the link chip LINK side. This input differential signal DEF
The level of I is determined by the Schmitt circuit SCH1 with the potential VIT + as the high-level threshold and the potential VIT- as the low-level threshold, becomes binary internal input data DI, and is transmitted to the host computer HOST or the like via the link chip LINK. You.

However, for some reason, for example, the input differential signal DEF input to the Schmitt circuit SCH1
For example, when a pulse signal of, for example, a positive polarity is generated in I due to noise as illustrated in FIG.
H1 mistakenly sets the internal input data DI to a high level,
An error occurs in the received data. In addition, this error continues from the time when the noise occurs until the next normal positive pulse signal is input, resulting in inversion of all the logical values of the received data during that time.

Further, to cope with this, a method of using an error correction method using a CRC code or the like is conceivable.
As is well known, in the error correction method, the number of bits of an error correction code to be added increases according to the number of error bits that can be detected and corrected. Therefore, in order to solve the above-mentioned problem in which the logical values of a plurality of bits are simultaneously inverted by one noise, the number of required bits of the error correction code to be added becomes unnecessarily large, thereby lowering the transmission efficiency of the digital system. However, cost reduction is hindered.

It is an object of the present invention to provide a ternary signal transmission device such as a bus connection device which can easily detect and correct an error due to noise of a ternary differential signal. Another object of the present invention is to enhance the reliability of a digital system employing the IEEE-1394 system without lowering the transmission efficiency and preventing cost reduction.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a ternary signal transmission device such as a bus connection device including an AC coupling device provided between a digital device such as a host computer and an IEEE-1394 bus cable, for example, a positive polarity A ternary restoration circuit that restores the change to high level of the data in response to the input of the pulse signal and restores the change to low level in response to the input of the negative pulse signal has a positive polarity or A function is provided to identify that any error has occurred in the data in response to the continuous input of any of the negative pulse signals, and to output an abnormality detection signal. In addition, CR sent and received between devices
When an error correction code such as a C code is added, an estimated error pattern is generated in the bus connection device based on the restored data output from the ternary restoration circuit and the abnormality detection signal, and a check result based on the error correction code is generated. In addition, an error estimating circuit for correcting a data error is provided.

According to the above means, even if an error over a plurality of bits occurs due to some noise in the ternary differential signal transmitted through the AC coupling means, this can be easily identified and, for example, a data retransmission request or the like can be identified. Appropriate processing can be performed, and if an error correction code is added to the data, the error bit position of the data should be identified together with the check result by this error correction code, and this can be easily corrected. Can be. As a result, the transmission efficiency is reduced, and the cost reduction is not hindered.
The reliability of a bus cable and a bus connection device employing the -1394 system and a digital system including the same can be improved.

[0014]

FIG. 1 shows a bus connection device (ternary signal transmission device) BCE1 and BCE to which the present invention is applied.
2 is a connection diagram of an embodiment of a digital system including the digital camera 2, and FIG. 2 is a block diagram of a first embodiment of a bus connection device BCE <b> 1 included in the digital system. FIGS. 3 and 4 show the bus connection device BC of FIG.
A circuit diagram and a block diagram of an embodiment of the digital differentiating circuit DEF1 and the ternary restoration circuit 3VC1 included in E1 are shown, respectively. FIG. 5 is a signal waveform diagram of an embodiment of the bus connection device BCE1. I have. Based on these figures,
The configuration, operation, and characteristics of the digital system and the bus connection device of this embodiment will be described.

The circuit elements constituting each block shown in FIG. 2 are formed on one or a plurality of semiconductor substrate surfaces such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. In FIG. 2, the bus connection device BC
With the description of E1, the bus connection devices BCE1 and BCE2
And FIG. 3 and FIG. 4 show the digital differentiating circuit DEF.
The digital differentiating circuits DEF1 and DEF2 and the ternary restoring circuit 3V
C1 and 3VC2 will be described respectively.

Referring to FIG. 1, a digital system according to this embodiment includes a host computer HOST and an IEEE-1.
A digital terminal device DDEV coupled to the host computer HOST via a 394 bus cable BC. A bus connection device BCE1 is provided between the host computer HOST and the bus cable BC. Further, a bus connection device BCE2 having a configuration symmetrical to the bus connection device BCE1 is provided between the bus cable BC and the digital terminal device DDEV. Further, the bus cable BC includes two pairs of signal lines, a power line, and a ground line.

Here, the bus connection devices BCE1 and BCE1
2, a link chip LINK provided on the host computer HOST side, a physical chip PHY provided on the bus cable BC side, and a link between the link chip LINK and the physical chip PHY, as represented by the bus connection device BCE1 in FIG. And a capacitor C serving as AC coupling means. Link chip LINK to capacitor C
Between them, a digital differentiating circuit DEF1 (first differential circuit)
Is provided, and the physical chip PHY is
Between them, a ternary restoration circuit 3VC2 (second ternary restoration circuit)
Is provided. A digital differentiating circuit DEF2 (second differentiating circuit) is provided between the physical chip PHY and the capacitor C.
A ternary restoration circuit 3VC2 (second ternary restoration circuit) is provided between the INKs.

Link chip LI of bus connection device BCE1
NK supports an interface to the host computer HOST, and the physical chip PHY
Supports an interface to an EEE-1394 bus cable BC. Also, the digital differentiating circuit D
The EF1 converts binary internal output data supplied from the host computer HOST via the link chip LINK into a ternary output differential signal composed of positive and negative pulse signals, and the ternary restoration circuit 3VC2 After the ternary input differential signal transmitted from the digital differentiating circuit DEF1 via the capacitor C is restored to binary internal output data, the signal is transmitted to the digital terminal device DDEV via the physical chip PHY and the bus cable BC. .

On the other hand, the digital differentiating circuit DEF2 converts the binary internal input data supplied from the digital terminal device DDEV via the bus cable BC and the physical chip PHY into a ternary binary signal composed of positive and negative pulse signals. The ternary restoration circuit 3VC1 converts the ternary input differentiation signal transmitted from the digital differentiation circuit DEF2 via the capacitor C into binary internal input data, and converts the converted signal into binary internal input data via the physical chip PHY. To the host computer HOST.

As a result, the link chip LINK and the physical chip PHY are AC-coupled via the capacitor C, and are connected between the host computer HOST and the digital terminal device DDEV using different DC power supply voltages as operation power supplies. It is assumed that data can be exchanged without any problem.

Here, the digital differentiating circuits DEF1 and DEF2 of the bus connection device BCE1 are, as represented by the digital differentiating circuit DEF1 of FIG. 3, for example, internal output data input from a host computer HOST via a link chip LINK. It includes a flip-flop FF1 receiving DO at a data input terminal D, and an output buffer OB receiving at its input terminal a non-inverted output signal Q of the flip-flop FF1 and outputting an ternary output differential signal DEFO. Clock input terminal C of flip-flop FF1
Is supplied with a serial clock signal SCK from a clock generation circuit (not shown) of the bus connection device BCE1, and a control terminal of the output buffer OB has a flip-flop FF
Three non-inverted output signals Q are provided.

The output buffer OB is a so-called tri-state buffer. The level of the output differential signal DEFO at the output terminal of the output buffer OB is the same as that of the non-inverted output signal Q of the flip-flop FF3 supplied to the control terminal. At this time, when the non-inverted output signal Q of the flip-flop FF1 is set to a predetermined high level potential VOH or the low-level potential VOL selectively according to the logical level of the non-inverted output signal Q of the flip-flop FF1, A predetermined intermediate potential VOM is set. In this embodiment, the high-level potential V of the output differential signal DEFO is
The OH and the low-level potential VOL are not particularly limited, but are, for example, 5 V (volt) and 0 V, respectively, and the intermediate potential VOM is, for example, 2.5 V.

The digital differentiating circuit DEF1 further includes an AND gate AG1 receiving the internal output data DO at one input terminal and an output enable signal EN at the other input terminal, and an AND gate AG1 at its data input terminal D. Flip-flop FF2 receiving an output signal of gate AG1. The serial clock signal SCK is supplied to the clock input terminal C of the flip-flop FF2, and the non-inverted output signal Q is supplied to one input terminal of the exclusive OR circuit EO1. This exclusive OR circuit E
Internal output data DO is supplied to the other input terminal of O1, and its output signal is supplied to one input terminal of an OR (OR) gate OG1.

On the other hand, a direct output signal DIR is supplied to the other input terminal of the OR gate OG1 from a control circuit (not shown) of the bus connection device BCE1, and the output signal is supplied to one input terminal of the AND gate AG2.
An output enable signal EN is supplied from the control circuit to the other input terminal of the AND gate AG2, and the output signal is supplied to the data input terminal D of the flip-flop FF3. The serial clock signal SCK is supplied to the clock input terminal C of the flip-flop FF3, and the non-inverted output signal Q is supplied to the control terminal of the output buffer OB.

Thus, for example, the host computer H
The internal output data DO supplied from the OST via the link chip LINK is taken in and held by the flip-flop FF1 according to the serial clock signal SCK, and the serial output data DO is provided on condition that the output enable signal EN is set to the high level. The data is taken in and held by the flip-flop FF2 according to the clock signal SCK. The internal output data DO further includes an exclusive OR circuit EO1
Is compared with the internal output data DO of the immediately preceding cycle held in the flip-flop FF2, and when both have different logical values, the output signal of the exclusive OR circuit EO1 is selectively set to the high level.

The output signal of the exclusive OR circuit EO1 is transmitted to the AND gate AG2 via the OR gate OG1, and selectively provided on the condition that the output enable signal EN is at a high level. Is set to a high level. The output level of the AND gate AG2 is taken into the flip-flop FF3 according to the serial clock signal SCK and transmitted to the control terminal of the output buffer OB.

As described above, the output buffer OB is of a tri-state type, and its output signal, that is, the output differential signal D
EFO is the non-inverted output signal Q of the flip-flop FF3.
Is at a high level, selectively at a high level or a low level according to the non-inverted output signal Q of the flip-flop FF1, and when the non-inverted output signal Q of the flip-flop FF3 is at a low level, it is set to a predetermined intermediate potential. You.

From these facts, the output signal of the output buffer OB, that is, the output differential signal DEFO is, as illustrated at the timings t3 and t10 in FIG. 5, the internal output data DO having the logic "0", that is, the logic "1" That is, when the signal is changed to the high level, the pulse signal is selectively set to the high level such as the high-level potential VOH for one cycle period of the pulse signal of the positive polarity, that is, the serial clock signal SCK. Further, as illustrated at timings t5 and t11, when the internal output data DO is changed from logic “1”, ie, high level, to logic “0”, ie, low level, a pulse signal of a negative polarity, ie, a serial clock It is set to a low level like the low level potential VOL only for one cycle period of the signal SCK.

In other words, the internal output data DO
Are digitally differentiated by a digital differentiating circuit DEF1 and become a ternary output differential signal DEFO composed of a positive or negative pulse signal. The timings t1 to t1 when the logical value of the internal output data DO does not change t2, t
4, t6 to t9 and t12, the output differential signal DEFO becomes the intermediate potential VO between the high level and the low level.
M. After the output differential signal DEFO passes through the capacitor C, it is transmitted as an input differential signal DEFI to the ternary restoration circuit 3VC2 on the physical chip PHY side. Needless to say, the output differential signal DEFO output from the digital differentiating circuit DEF2 on the physical chip PHY side
Similarly, after passing through the capacitor C, the link chip LIN
The input differential signal DEFI is transmitted to the K-side ternary restoration circuit 3VC1.

Next, the ternary restoration circuits 3VC1 and 3VC2 of the bus connection device BCE1 are connected to the bus connection device BCE of FIG.
1, a Schmitt circuit SCHC, a positive polarity determining circuit PD and a negative polarity determining circuit ND which commonly receive an input differential signal DEFI transmitted via a capacitor C from a digital differentiating circuit DEF2 on the physical chip PHY side. Including. The output signal of the Schmitt circuit SCHC is a link chip L as the internal input data DI.
It is transmitted to the host computer HOST via INK. The output signal PDO (positive pulse reception signal) of the positive polarity determination circuit PD and the output signal NDO (negative pulse reception signal) of the negative polarity determination circuit ND are output from the abnormality detection circuit ED.
Supplied to The output signal of the abnormality detection circuit ED is supplied to the link chip LINK as the abnormality detection signal EDO.

Here, the Schmitt circuit SCHC of the ternary restoration circuit 3VC1 is a hysteretic level judgment circuit having a predetermined high level threshold value VIT + and a low level threshold value VIT-, and its output signal, that is, the internal input data DI is shown in FIG. As illustrated in FIG. 5, the input differential signal DEF
After I exceeds the high-level threshold value VIT + and then becomes lower than the low-level threshold value VIT-, the input differential signal DEFI is continuously set to the high level.
After it becomes lower than IT-, the high level threshold VIT +
Until it exceeds, it is continuously at the low level.

Thus, the input differential signal D, which is a ternary signal, is obtained.
EFI is selectively set to a high level from the time when the pulse signal is changed to a positive pulse signal to the time when the pulse signal is next changed to a negative pulse signal. Until a pulse signal of the same nature as that of FIG.
The result is that the binary digital signal corresponding to O is restored.

As illustrated at timing t7 in FIG. 5, when a noise exceeding, for example, a high-level threshold value VIT + occurs in the input differential signal DEFI in the path including the capacitor C, the Schmitt circuit of the ternary restoration circuit 3VC1 The SCHC regards this as a positive pulse signal,
The internal input data DI is erroneously changed from a low level to a high level. The high level of the internal input data DI is maintained until the next normal positive pulse signal is input, resulting in inversion of all logical values of the internal input data DI during this time. In addition, such a data error over a plurality of bits is difficult to detect even when an error correction code such as a CRC code is added, and in order to reliably detect the error, it is necessary to add a multi-bit error correction code.
The cost reduction of the bus connection device BCE1 and hence of the digital system is hindered.

In order to deal with this, in the bus connection device BCE1 of this embodiment, the ternary restoration circuit 3VC1 is provided with the positive polarity judgment circuit PD, the negative polarity judgment circuit ND, and the abnormality detection circuit ED. Differential signal DEFI
A method of easily detecting the noise is used. That is,
When the level of the input differential signal DEFI exceeds the high-level threshold value VIT +, the positive polarity determination circuit PD of the ternary restoration circuit 3VC1 selectively sets the output signal PDO to a high level. Differential signal DEFI
Is lower than the low level threshold VIT-, the output signal NDO is selectively set to the high level. Further, when the output signals PDO and NDO of the positive polarity determination circuit PD and the negative polarity determination circuit ND are sequentially alternately set to the high level, the abnormality detection circuit ED sets the output signal, that is, the abnormality detection signal EDO to the invalid level, that is, the low level. However, the output signal PDO of the positive polarity determination circuit PD or the negative polarity determination circuit ND
Alternatively, when one of NDO and NDO is continuously set to the high level, the abnormality detection signal EDO is selectively set to the effective level, that is, the high level at that time.

Needless to say, when the output signals PDO and NDO of the positive polarity judgment circuit PD and the negative polarity judgment circuit ND are sequentially turned to the high level, the input differential signal DEFI
Does not generate noise, and when either the output signal PDO or NDO of the positive polarity determination circuit PD or the negative polarity determination circuit ND is continuously at a high level, the input differential signal DEFI has a positive polarity or a negative polarity. This is a state where noise has occurred.

By providing the positive polarity determination circuit PD, the negative polarity determination circuit ND, and the abnormality detection circuit ED in the ternary restoration circuit 3VC1, internal input data DI which is generated in the input differential signal DEFI and becomes reception data is provided. In this case, noise that causes an error over a plurality of bits can be easily detected. The host computer HOST or the like, which is a data receiving device, receives a high level of the abnormality detection signal EDO, for example, makes a data retransmission request to the partner terminal, and can secure normal data. In addition, the abnormality detection processing includes:
The present invention can be realized without increasing the number of bits of the error correction code, thereby reducing the transmission efficiency and preventing the cost reduction. It can increase the reliability of the digital system.

FIG. 6 is a block diagram showing a second embodiment of the bus connection device BCE1 included in the digital system shown in FIG. FIG. 7 is a block diagram of one embodiment of the error estimating circuit ERCC of the bus connection device BCE1 of FIG. 6, and FIG. 8 is a signal waveform diagram of one embodiment of the bus connection device BCE1 of FIG. It is shown. It should be noted that the bus connection device BCE1 of this embodiment basically follows the embodiment of FIGS. 2 to 5, and therefore, a description will be added only for portions different from this.

In FIG. 6, the bus connection device BCE1 of this embodiment includes an error estimating circuit ERCC that receives the output signal of the ternary restoration circuit 3VC1.

In this embodiment, an error correction code of a predetermined bit, that is, a CRC code is added to data transmitted and received between the host computer HOST and the digital terminal device DDEV, and a corresponding predetermined error correction process is performed. That is, for example, when the digital signal to be transmitted is F (x) on the digital terminal device DDEV serving as a transmitting device, the remainder R (x) obtained by dividing F (x) × ³² by the generator polynomial G (x) Is the CRC code and the transmission data M (x)
And send it. The host computer HOST serving as a receiving device identifies whether the remainder pattern obtained by dividing the received data M ^* (x) by the generator polynomial G (x), that is, the syndrome P (x) is zero. , It is determined that no error has occurred in the received data M ^* (x), and if not zero, it is determined that an error has occurred in the bit position corresponding to the syndrome, and Invert the bit and correct it.

Note that C in the IEEE-1394 standard
For the RC code, see the above-mentioned “IEEE Std 139”.
4-1995 ", page 160, and the like.

In order to realize the above error correction processing, the error estimating circuit ERCC of the bus connection device BCE1 of this embodiment is used.
Receives the internal input data DI restored to a binary signal by the ternary restoration circuit 3VC1, as shown in FIG. 7, and receives the internal input data DI, that is, the received data M ^* (x).
Is divided by a generator polynomial G (x) to generate a predetermined remainder pattern, that is, a syndrome P (x).
C1 (first arithmetic circuit) is provided. The error estimating circuit ERCC generates an error pattern generating circuit EPTG that generates a predetermined estimated error pattern Ex based on the abnormality detection signals EDO1 and EDO2 output from the ternary restoration circuit 3VC1.
And a CRC operation circuit CRC2 (second operation circuit) for generating another residue pattern, that is, an error pattern syndrome P ′ (x) based on the estimated error pattern Ex. Further, the syndrome P (x) And an error determination circuit ER that generates a predetermined error correction signal and an error detection signal EDS based on the error pattern syndrome P ′ (x)
DC is provided.

The error correction signal generated by the error determination circuit ERDC is supplied to an error correction circuit ECRC. The error correction circuit ECRC corrects a bit error of the internal input data DI based on the error correction signal, and then supplies the corrected error as the internal input data CDI to the link chip LINK. Further, the error detection signal EDS is supplied to the link chip LINK and used for data retransmission processing and the like.

Here, the abnormality detection signal EDO1 generated by the ternary restoration circuit 3VC1 of the bus connection device BCE1
Is, for example, as shown in FIG.
Alternatively, when either the output signal PDO or NDO of the negative polarity determination circuit ND is continuously set to the high level, the signal is selectively set to the high level for one cycle period. Also,
The abnormality detection signal EDO2 is, for example, an input differential signal DEFI.
This signal is at a high level from the time when an error occurs in the internal input data DI due to the generated noise until the next pulse signal of the opposite polarity, that is, the negative polarity is input.

As is apparent from FIG. 8, the error included in the internal input data DI is detected at the beginning when the abnormality detection signal EDO2 is set to the high level, that is, at the timing t7, or after the abnormality detection signal EDO2 is set to the high level. Signal E
It should exist at the bit position until DO1 is set to the high level, that is, at the timing t8 to t9.

The error pattern generation circuit EPTG of the error estimation circuit ERCC generates an estimated error pattern Ex corresponding to a bit position where an error may exist based on the abnormality detection signals EDO1 and EDO2. Also, CRC
The arithmetic circuit CRC2 generates a predetermined error pattern syndrome P ′ (x) based on the estimated error pattern Ex supplied from the error pattern generation circuit EPTG. further,
The error determination circuit ERDC compares and compares the normal syndrome P (x) generated by the CRC calculation circuit CRC1 with the error pattern syndrome P ′ (x) generated by the CRC calculation circuit CRC2, and when both match. Sends an error correction signal to the error correction circuit ECRC in order to correct the matched part of the internal input data DI, and when they do not match, generates only the error detection signal EDS and ends the processing.

From these facts, in the bus connection device BCE1 of this embodiment, in addition to the normal error correction processing using the CRC code, the syndrome P (x) output from the CRC operation circuit CRC1 and the output from the CRC operation circuit CRC2 are output. The error correction processing based on the error pattern syndrome P ′ (x) can be performed.
It is possible to further enhance the reliability of a bus cable and a bus connection device employing the 394 system and a digital system including the bus cable and the bus connection device.

When the normal syndrome P (x) does not match the error pattern syndrome P ′ (x), the error in the received data is not corrected. However, in such a case, the error detection signal EDS is formed. The normality of data is ensured by a data retransmission request or the like, and IEEE-1394
It is possible to ensure the reliability of the bus cable and the bus connection device adopting the system and the digital system including them.

The operation and effect obtained from the above embodiment are as follows. (1) Digital devices such as a host computer and IEEE
In a ternary signal transmission device such as a bus connection device including an AC coupling unit provided between the 1394 bus cable and an AC coupling unit, for example, when a positive pulse signal is input through the AC coupling unit Either the positive or negative pulse signal is continuous in the ternary restoration circuit that restores the change of data to high level and restores the change to low level in response to the input of the negative pulse signal. Identifying that some error has occurred in the data in response to the input, and having a function of outputting an abnormality detection signal, the ternary differential signal transmitted through the AC coupling means,
Even if an error over a plurality of bits occurs due to some noise, it is possible to easily identify the error and perform an appropriate process such as a data retransmission request.

(2) In the above item (1), when an error correction code such as a CRC code is added to the data exchanged between the devices, the restored data output from the ternary restoration circuit is connected to the bus connection device. By generating an estimated error pattern based on the anomaly detection signal and providing an error estimation circuit that corrects data errors in conjunction with the check result by the error correction code, an error pattern syndrome based on the estimated error pattern and an error correction code In combination with the normal syndrome described above, an effect is obtained that an error bit position of data can be identified and corrected.

(3) According to the above items (1) and (2),
Without increasing the number of bits of the error correction code, that is, without reducing its transmission efficiency and preventing cost reduction, IE
The effect that the reliability of the bus cable and the bus connection device adopting the EE-1394 system and the digital system including them can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the digital system can include a server for centrally managing data, various peripheral devices, and the like, and include a plurality of bus cables and a bus connection device for connecting these devices. Can be. The block configuration and connection form of the digital system can take various embodiments without being limited by this embodiment.

In FIGS. 2 and 6, the capacitor C serving as AC coupling means can be replaced with a coupling circuit centered on a coil, and various block configurations of a bus connection device typified by BCE1 can be considered. . In FIG. 3, the specific configuration of the digital differentiating circuit represented by DEF1 is not restricted by this embodiment.

In FIG. 4, a Schmitt circuit SCHC
For example, contrary to the embodiment, a positive pulse signal of the input differential signal DEFI is received to restore a change in data to a low level, and a negative pulse signal is received to restore the change to a high level. It may be a thing. Further, the Schmitt circuit SCHC can be replaced with a digital processing device having a similar logical structure. Further, a positive polarity determination circuit PD, a negative polarity determination circuit ND, and an abnormality detection circuit E
D may be a separate block from the ternary restoration circuit 3VC1 centered on the Schmitt circuit SCHC, or 3VC
The block configuration of the ternary restoration circuit represented by 1 can also take various embodiments.

In FIG. 7, the error correction code added to the data is not limited to the CRC code, and the block configuration of the error estimation circuit ERCC can take various embodiments. 5 and 8, the effective level of each signal can be set arbitrarily, and the specific time and level relationship between the signals do not affect the gist of the present invention.

In the above description, the invention made mainly by the inventor is based on the bus connection device provided between the digital device and the IEEE-1394 bus cable, and the bus connection device including the same. The case where the present invention is applied to a digital system has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a single unit formed as a bus connection device, various communication systems using a ternary signal system, and the like. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a ternary signal transmission device having a signal transmission function using at least a ternary differential signal and a system including the ternary signal transmission device.

[0056]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a ternary signal transmission device such as a bus connection device including an AC coupling device provided between a digital device such as a host computer and an IEEE-1394 bus cable, for example, a positive polarity A ternary restoration circuit that restores the change to high level of the data in response to the input of the pulse signal and restores the change to low level in response to the input of the negative pulse signal has a positive polarity or By providing a function to identify that an error has occurred in the data in response to the continuous input of one of the negative polarity pulse signals and to output an abnormality detection signal, Even if an error over a plurality of bits occurs in the transmitted ternary differential signal, the error can be easily identified and appropriate processing such as a data retransmission request can be performed. .

When an error correction code such as a CRC code is added to data transmitted and received between devices, an error in the bus connection device is estimated based on the restored data output from the ternary restoration circuit and the abnormality detection signal. By generating a pattern and providing an error estimating circuit for correcting a data error together with the check result by the error correction code, the error bit position of the data is identified together with the check result by the error correction code. Can be easily corrected. As a result,
Without increasing the number of bits of the error correction code added to the data, that is, without lowering the transmission efficiency and preventing cost reduction, a bus cable and a bus connection device adopting the IEEE-1394 system and a digital system including the bus cable and the bus connection device. Reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of a digital system to which the present invention is applied.

FIG. 2 is a block diagram showing a first embodiment of a bus connection device included in the digital system of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a digital differentiating circuit included in the bus connection device of FIG. 2;

FIG. 4 is a block diagram showing one embodiment of a ternary restoration circuit included in the bus connection device of FIG. 2;

FIG. 5 is a signal waveform diagram showing one embodiment of the bus connection device of FIG. 2;

FIG. 6 is a block diagram showing a second embodiment of the bus connection device included in the digital system of FIG. 1;

FIG. 7 is a block diagram showing one embodiment of an error estimating circuit included in the bus connection device of FIG. 6;

FIG. 8 is a signal waveform diagram showing one embodiment of the bus connection device of FIG. 6;

FIG. 9 is a block diagram showing an example of a bus connection device developed by the present inventors prior to the present invention.

FIG. 10 is a signal waveform diagram illustrating an example of the bus connection device of FIG. 9;

[Explanation of symbols]

HOST: Host computer, BCE1-BCE2
…… Bus connection device, BC …… Bus cable, DDEV…
... Digital terminal device. LINK ... link chip, DE
F1 to DEF2: digital differentiation circuit, C: capacitor, 3VC1 to 3VC2: ternary restoration circuit, PHY:
Physical chip. FF1 to FF3 ... flip-flop, EO1 ... exclusive OR circuit, AG1 to AG2 ...
AND gate, OG1 ... OR gate, OB ... output buffer, DO ... internal output data, SCK ... serial clock signal, DIR ... direct output signal, EN ...
... Output enable signal, DEFO ... Output differential signal. S
CHC: Schmitt circuit, PD: Positive polarity determination circuit,
ND: Negative polarity judgment circuit, ED: Abnormality detection circuit, DE
FI: input differential signal, DI: internal input data, PD
O: Positive pulse reception signal, NDO: Negative pulse reception signal, EDO: Abnormality detection signal. t1-t12 ...
Timing, VOH ... ternary high level potential, VOM ...
… Ternary intermediate potential, VOL… ternary low level potential, VI
T +: High level threshold of Schmitt circuit, VIT -...
... Low level threshold of Schmitt circuit. ERCC: error estimation circuit, ECRC: error correction circuit, EPTG: error pattern generation circuit, CRC1 to CRC2: CRC operation circuit, ERDC: error determination circuit, CDI: error-corrected internal input data, EDO1 to EDO1 EDO2: abnormality detection signal, Ex: estimated error pattern, P (x): syndrome, P ′ (x): error pattern syndrome, E
DS ... Error detection signal. SCH1 to SCH2... Schmitt circuits.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihiro Makino 5-22-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super SII Systems Co., Ltd. (72) Inventor Akihiro Fushida Tokyo 5-22-1, Kamimizu Honcho, Kodaira City Within Hitachi Cho SII Systems, Inc. (72) Inventor Kazunori Nakamura 5-221-1, Kamimizu Honcho, Kodaira City, Tokyo Hitachi, Ltd. FSI term in LSI Systems (reference) 5K029 AA02 CC01 DD02 FF03 HH08 HH11 HH16 5K034 AA06 AA10 DD01 FF01 FF11 FF13 GG06 HH02 HH04 HH10

Claims (6)

[Claims] 1. A change in data to one logic level is restored in response to the input of a positive pulse signal, and the other logic level in data is restored in response to the input of a negative pulse signal. And that it is possible to identify that any error is included in the data in response to the continuous input of either the positive or negative pulse signal. A ternary signal transmission device. 2. The ternary signal transmission device according to claim 1, wherein the ternary signal transmission device transmits data output from a predetermined digital device to a predetermined bus cable in an AC manner,
And a bus connection device for transmitting data input through the bus cable to the digital device in an alternating manner. 3. The bus system according to claim 2, wherein the signal system in the bus cable is IEEE-13.
A ternary signal transmission device according to the 94 system. 4. The ternary signal transmitting device according to claim 2, wherein the ternary signal transmitting device includes a link chip provided on the digital device side, a physical chip provided on the bus cable side, and the link from the digital device. The positive pulse signal is generated by receiving a change to one logic level of data transmitted through the chip or transmitted from the bus cable through the physical chip,
A first and a second differentiating circuit for respectively generating the negative pulse signal in response to the change to the other logical level; and a predetermined AC coupling means from the second or the first differentiating circuit. A first and a second for restoring corresponding data based on the transmitted positive or negative pulse signal, respectively.
Wherein each of the first and second ternary restoration circuits receives the positive or negative pulse signal and generates corresponding data, respectively. A positive polarity determination circuit and a negative polarity determination circuit for generating a positive polarity pulse reception signal or a negative polarity pulse reception signal based on the positive polarity or negative polarity pulse signal; and the positive polarity pulse reception signal or the negative polarity pulse. An abnormality detection circuit that selectively sets an abnormality detection signal to an effective level in response to generation of one of the received signals continuously. 5. The data transmission device according to claim 1, wherein a predetermined error correction code is added to the data, and the ternary signal transmission device further comprises: A ternary signal transmission device including an error estimating circuit for correcting the predetermined error based on the syndrome generated based on the error correction code and the abnormality detection signal. 6. The method according to claim 5, wherein the error estimating circuit receives the data restored by the first or second ternary restoring circuit and performs a predetermined error correction code operation to generate the syndrome. And an error pattern generation circuit that generates a predetermined error pattern based on the abnormality detection signal output from the first or second ternary restoration circuit, and an error pattern output from the error pattern generation circuit A second arithmetic circuit that generates an error pattern syndrome based on the error pattern; an error determination circuit that generates a data correction signal and an error detection signal based on the syndrome and the error pattern syndrome; And an error correction circuit for correcting the predetermined error.