JP2001043194A - Information device and communication control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in a communication process. SOLUTION: A communication controller 200 includes a received data register REG(2) where received data are written, a static register REG1 which hold a reception state, and a transmit data register REG(3) where transmit data are written. A CPU (400) once informed of reception by a communication controller 200 gives notice of arrival of the received data. A communication control means 101 once informed of that performs a read process or the received data. A comparing means 104 compares contents of the status register with a prescribed value, and judges whether or not the received data are the final received data and whether or not the read process is as fast as or faster than data reception and informs the communication control means of them. A CPU clock frequency setting means 102 increases the clock frequency of the CPU when the read process is slower than the data reception and writes information giving notice of that to a transmission side in the transmit data register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to information-controlled information equipment and a communication control method, and more particularly to a technique for reducing the power consumption of a CPU in a battery-powered portable terminal.

[0002]

2. Description of the Related Art This kind of conventional technology is called "power control device".
As described in JP-A-06-051862. This technique is used in an interactive information processing apparatus to determine whether or not arithmetic processing for a user's input is in time when a user is performing input, and if so, the arithmetic processing apparatus is operated at a low clock frequency. If it is not, it is to drive the arithmetic processing unit at a high clock frequency.

[0003] This reduces stress on the user caused by not accepting the next input at all until the processing corresponding to the user's input is completed, and occupies a large weight in power consumption in the information processing apparatus. In addition, the power of the arithmetic processing unit can be saved. This technology can be said to be particularly suitable for a portable information device such as a notebook computer which can be driven by a battery, which has been rapidly spread.

[0004]

By the way, in recent years, the tendency of the coupling between information equipment and communication means has been increasing, and the need for communication processing from portable information equipment has been increasing. . Regarding this point, the above-mentioned publication discloses a technique for adjusting a clock frequency in a verbal process in which a user performs a key input, and a description about a non-verbal process such as a communication process is thin. The processing must be performed at a high speed regardless of the state of the user's key input. "Therefore, only the operation of the arithmetic processing device is always driven at a high clock frequency.

However, as described above, the clock frequency control is not performed in the communication processing, and therefore, when the portable information device is driven at a constant high clock frequency during the communication processing, the power consumption is reduced during the communication. There is a first problem that it cannot be reduced.

[0006] Further, the above-mentioned prior art relates to key input of an interactive information processing apparatus, and if the arithmetic processing cannot be performed in time, at least one piece of data will be missed. There is a second problem that it is necessary to perform key input.

In addition, although a clock frequency suitable for the communication speed used in advance is set and operated, if a program having a larger load is operated by replacing other programs, an interrupt processing at the time of reception is performed. However, there is a third problem in that an overrun error occurs and communication error occurs in time. In order to avoid this problem, the clock frequency may be set higher in advance by predicting a high load before performing the communication processing, but by setting the clock frequency higher, large power is consumed, and This leads to a new problem of hassle-free consumption.

An object of the present invention is to provide an information device and a communication control method capable of reducing power consumption during communication processing.

Another object of the present invention is to provide an information device and a communication control method in which, when an arithmetic operation cannot be made in time, a retransmission request is automatically sent to the transmission side, so that the user does not need to input a key again. Is to provide.

It is a further object of the present invention to provide an information device and a communication control method which can cope with a case where a program having a larger load operates.

[0011]

According to a first aspect of the present invention, when the reading process of received data is not in time for data reception, a request for retransmission of the received data is sent to the transmitting side, and the reading process is performed. The clock frequency of the CPU to be instructed is set high, and the CPU speed is increased during data reception processing for the retransmission request.

According to a second aspect of the present invention, there is provided an information device connected to a main device via a communication line, wherein a reception data register into which data received from the main device is written,
A communication controller that reads and writes these registers including a status register that holds a reception state and a transmission data register in which transmission data to the main unit is written, and receives a reception notification of the reception data from the communication controller. CPU that notifies data arrival
When receiving the data arrival notification from the CPU, the communication controller performs reading processing of the received data in the reception register, and notifies the communication controller of the result, and sets the content of the status register to a predetermined value. In comparison, the received data is the last received data, and a comparing unit that determines whether the reading process is in time for the data reception and notifies the communication control unit, and the reading process is in time for the data reception. And a CPU clock frequency setting means for increasing the clock frequency of the CPU according to an instruction from the communication control means when the reading processing is not in time for the data reception. Writing information for notifying the device to that effect to the transmission data register. To.

According to a communication control method of the present invention, in the communication control method in the information equipment connected to the main unit via a communication line, when the data received from the main unit is written into a reception data register, the reception state is changed. Writing the received data into the status register, notifying the CPU of the arrival of the received data, reading the received data from the CPU, and reading the received data in the receiving register. Comparing the contents of the received data with a predetermined value to determine whether the received data is the last received data and whether the reading process is in time for receiving the data and writing the received data in the status register as the receiving state; If the processing is not in time for the data reception, the clock frequency of the CPU should be increased. If, when the reading process has not been in time to the data received, characterized by having a procedure which notifies to the main device.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

First, a terminal device according to the present invention will be described with reference to FIG. In FIG. 2, the terminal device 1 includes a connector 5 for connecting accessory devices such as a scanner 7 and a modem 6 for reading a barcode via a serial transmission cable (for example, an RS232C cable) 2, an input keyboard 8, a data display device, and the like. And a panel 9. Such a terminal device is often used in the distribution industry, for example.

The modem 6 is connected to the modular jack 4 by a telephone cable 3, and from the modular jack 4, a main unit 8 such as a host computer is connected via a general communication line.
24. Specifically, modular jack 4,
Communication line 830, exchange 820, communication line 831, network controller 821, modem 822, and communication controller 8
Through 23, it reaches the main device 824. The terminal device 1 processes input information from an attached device such as the scanner 7 connected to the connector 5 and transmits data to the main device 824 by the modem 6. As a result, the terminal device 1 can communicate with the main device 824 such as a host computer.

Next, an internal configuration of the terminal device 1 will be described with reference to FIG.

The terminal device 1 includes a connector 5 for connecting to an accessory device via an RS232C cable, a communication controller 200 for controlling a serial interface, a memory M1 for storing control programs and data, and a control device for controlling the terminal device 1. The control unit 100 includes a control unit 100, a battery for driving the control unit 100, and a CPU 300. In addition,
The battery for driving the control unit 100 is omitted from the drawing together with the input keyboard 8 and the data display panel shown in FIG.

The memory M1 has a reception data area M10 for storing reception data, a communication controller status data area M11 for storing data read from the status register REG1 of the communication controller, and the main unit 824 having a normal reception of data. A communication controller transmission data area M12 for transmitting an abnormality is provided.

Next, details of the control unit 100 will be described with reference to FIG. The control unit 100 includes a CPU clock frequency setting unit 102 for setting a CPU clock frequency.
Transfer control means 103 for transferring data between the memory M1 and various registers of the communication controller 200;
A comparing means 104 for determining the communication controller status data area M11; and a CPU clock frequency setting means 10
2. The communication control unit 101 performs communication control using the transfer control unit 103 and the comparison unit 104.

The communication controller 200 has a main unit 824
A data register REG2 in which data received from the receiver is written, and a status register R holding the reception state
EG1 and a transmission data register REG3 in which data to be transmitted to the main device 824 is written. When receiving the data from the main device 824, the communication controller 200 writes the data in the reception register REG2, and the CPU 300
, Raises an interrupt signal for notifying reception, and requests the reception of received data. Then, the CPU 300 sets the communication control unit 1
01 is notified of the arrival of the received data.
The received data is read via the. Communication control means 1
01 is delayed, the next received data is written from the communication controller 200 to the reception register REG2, and the status register REG1 is read.
In the field, data indicating that the reception data cannot be received in time is written.

Next, the data structure of the memory M1 will be described. FIG. 4 and FIG. 5 are schematic diagrams showing the data configuration of the memory M1. Referring to FIG. 4, it is shown that the memory M1 includes a reception data area M10, a communication controller status data area M11, and a communication controller transmission data M12 area.

FIG. 5 shows details of the data configuration of the memory M1 shown in FIG. The reception data area M10 includes, for example, data areas M100 to M102, and the content is, for example, “0x43, 0x42, 0x3”. This is a work area in which data received from the main device 824 is stored. “0x03” means the end of the received data,
A value other than “0x03” means that the received data continues.

The communication controller status data area M
11 includes a data area M110, the content of which is, for example, "0x01". This is the communication controller 200
Is a work area for storing data read from the status register REG1. "0x01" means that reading of the received data is not in time, and "0x0"
If it is other than "1", it means that the reading of the received data is in time.

The communication controller transmission data area M
Reference numeral 12 includes data areas M120 and M121, the contents of which are, for example, "0x06" and "0x15". These are data for notifying the main device 824 of whether the data reception from the main device 824 has been normally or abnormally received, and “0x06” means that the received data is normal,
“0x15” means that the received data is abnormal.

Next, the communication control processing of the present invention will be described with reference to the flowchart of the main processing shown in FIG. 6, the flowchart of the CPU clock setting processing shown in FIG. 7, and the communication sequence shown in FIG. In the present embodiment, the value that can be set by the CPU clock frequency setting means 102 is:
There are three types, “high”, “medium” and “low”, and the initial value is set to “low”.

First, a flowchart of the CPU clock frequency change processing subroutine (step S81) will be described with reference to FIG. In step S810, the current CPU clock frequency is determined, and the process branches to each process. That is, if the clock frequency is set to "low", the process proceeds to step S811, and if the clock frequency is set to "medium", the process proceeds to step S811.
After proceeding to step 2, if the clock frequency is set to "high", the CPU clock setting process is terminated and the process returns to the main process without any change.

In step S811, the CPU clock frequency setting means 102 sets the CPU clock to "medium", then ends the CPU clock frequency change processing and returns to the main processing. In step S812, the CPU clock frequency setting means 102 Clock "high"
After setting to, the CPU clock frequency process is terminated and the process returns to the main process.

First, an operation in a low load state where no other program is operating will be described. In this case,
CPU clock frequency is "medium" due to low load condition
Assume that data reception is in time in the configuration.

(1) When the CPU clock frequency is set to "low" in a low load state In step S10 in FIG. 6, an initial value "0" indicating the relative position of the received data is set in the pointer * y, and step S2 is executed.
Go to 0. In step S20, the communication controller 200
Status register REG to determine the
1 is written to the communication controller status data area M11, and the flow advances to step S30. In step S30,
By comparing the content of the communication controller status area M11 read in step S20 with the following predetermined value by the comparing means 104, the content of the communication controller status data area M11 can be set even if the CPU clock frequency is set to “low”. In the case of "0x00", the process proceeds to step S40 as normal (the reading process was completed) received by the communication controller 200, and in the case of "0x01", the process proceeds to step S80 as an overrun error.

In step S80, in order to notify the main unit 824 of abnormal reception of data (the reading process was not completed in time), the communication controller transmission data area M12
Is written into the transmission register REG3 in the data area M121 in step (2), and the process proceeds to step S81 (SEQ2 in FIG. 8). In step S81, the CPU clock frequency is set to “medium” by the CPU clock frequency change process, and the process proceeds to step S10 to receive retransmission data from main device 824.

(2) In the case where the CPU clock frequency is set to "medium" in a low load state: In step S10, an initial value "0" indicating the relative position of the received data is set in the pointer * y, and the flow advances to step S20. In step S20, to determine the reception state of the communication controller 200, the contents of the status register REG1 are written to the communication controller state data area M11, and the process proceeds to step S30. In step S30, the communication controller status data area M read in step S20.
11 is compared with the following predetermined value by the comparing means 104, and when the content of the communication controller status data area M11 is "0x00", it is determined that the reception is normal and step S
The process proceeds to 40, and if “0x01”, the process proceeds to step S80 as an overrun error. As described above, since the load is low and the CPU clock frequency is set to “medium”, normal reception is performed in step S30.

In step S40, the communication controller 20
The received data is read from the 0 received data register REG2, written into the position indicated by the relative position * y of the received data, and the process proceeds to step S50. In step S50, step S4
The data written in the relative position * y of the received data area M10 at 0 is compared with the following predetermined value by the comparing means 104. If the received data is "0x03", it is determined that the received data is the last and the process proceeds to step S70. , "0x03", it is determined that there is received data, and the process proceeds to step S60.

In step S60, the pointer * y is incremented by "+1" with an initial value "0" indicating the relative position of the received data in preparation for writing the next received data into the received data area M10, and the flow advances to step S20. Further, in step S70, in order to notify the main device 824 of the normal reception of data, the data area M in the communication controller transmission data area M12 is transmitted.
The content “0x06” of the content 120 is written into the transmission register REG3, and the communication control process is terminated (SEQ4 in FIG. 8).

Next, a description will be given of an operation example in a high load state in which another program is operating. In this case, since the load is high, it is assumed that the CPU clock frequency is set to “high” so that data reception can be performed in time.

(3) When the CPU Clock Frequency is Set to "Low" Under High Load State In step S10, an initial value "0" indicating the relative position of the received data is set in the pointer * y, and the flow advances to step S20. In step S20, to determine the reception state of the communication controller 200, the contents of the status register REG1 are written to the communication controller state data area M11, and the process proceeds to step S30. In step S30, the communication controller status data area M read in step S20
11 is compared with the following predetermined value by the comparing means 104, and when the content of the communication controller status data area M11 is "0x00", it is determined that the reception is normal and the step S is performed.
The process proceeds to step S40, and if “0x01”, the process proceeds to step S80 as an overrun error.

In this case, since the load is high, the CP
When the U clock frequency is set to “low”, overrun occurs. Therefore, in step S80, in order to notify the main device 824 of the abnormal reception of the data, the content “0x” of the data area M121 in the communication controller transmission data area M11.
"15" in the transmission register REG3, and step S8.
Go to 1 (SEQ2 in FIG. 8). CPU in step S81
The process proceeds to step 10 in order to set the CPU clock frequency to “medium” by the clock frequency changing process and receive retransmission data from main device 824.

(4) In the case where the CPU clock frequency is set to "medium" under a high load state: In step S10, an initial value "0" indicating the relative position of the received data is set in the pointer * y, and the flow advances to step S20. In step S20, to determine the reception state of the communication controller 200, the contents of the status register REG1 are written in the communication controller state data area M11, and the flow advances to step S30M. In step S30, the contents of the communication controller status data area M11 read in step S20 are compared with the following predetermined values by the comparing means 104, so that the communication controller status data area M11
Is "0x00", the process proceeds to step S40 as normal reception, and if "0x01", the process proceeds to step S80 as an overrun error.

In this case, since the load is high, the CP
When the U clock frequency is set to "medium", the overrun occurs. Therefore, in step S80, in order to notify the main device 824 of the abnormal reception of the data, the content “0x” of the data area M121 in the communication controller transmission data area M11.
"15" in the transmission register REG3, and step S8.
Go to 1 (SEQ2 in FIG. 8). CPU clock frequency is set to “high” by the clock frequency changing process in step S81
Then, the process proceeds to step S10 to receive the retransmission data from the main device 824.

(5) When the CPU Clock Frequency is Set to "High" Under High Load State In step S10, an initial value "0" indicating the relative position of the received data is set in the pointer * y, and the flow advances to step S20. In step S20, to determine the reception state of the communication controller 200, the contents of the status register REG1 are written to the communication controller state data area M11, and the process proceeds to step S30. In step S30, the communication controller status data area M read in step S20.
11 is compared by the comparing means 104 with the following predetermined values. When the content of the communication controller status data area M11 is "0x00", the process proceeds to step S40 as normal reception, and when "0x01", the process proceeds as an overrun error. Proceed to S80.

In this case, since the load is high, normal reception is performed when the CPU clock frequency is set to “high”. In step S40, the reception data register RE of the communication controller
Read the received data from G2 and the relative position of the received data *
The process proceeds to writing S50 at the position indicated by y. Step S50
In step S40, the data written in the reception data area M10 * y in step S40 is compared with the following predetermined value by the comparison means 104. If the reception data is "0x03", it is determined that the reception data is the last and the process proceeds to step S70. "0x0
If it is other than "3", it is determined that there is received data and step S
Proceed to 60.

In step S60, in preparation for writing the next received data in the received data area M10, the pointer * y is incremented by "+1" with the initial value "0" indicating the relative position of the received data, and the flow advances to step S20. In addition, in step S70, in order to notify main device 824 of normal reception of data, data area M in communication controller transmission data area M11 is transmitted.
The content “0x06” of the content 120 is written into the transmission register REG3, and the communication control process is terminated (SEQ4 in FIG. 8).

A program for causing a computer to execute the communication control method described above may be stored in a recording medium such as a semiconductor memory or a magnetic disk and read and executed by the computer. Such a program controls the computer and performs the same operation as the control unit 100 shown in FIG.

[0044]

As described above, according to the present invention,
If the communication speed is so fast that the receiving process is not in time,
Even if other programs are running during communication and the load is high and the receiving process is not in time, it is possible to prompt the transmitting side to retransmit and dynamically set the optimal CPU clock frequency. The first effect is that the power consumption of the communication device can be reduced and a communication failure due to a reception error can be avoided.

In addition, when the arithmetic processing cannot be performed in time for data reception, a retransmission request is automatically made to the transmission side, so that the second effect that the user does not need to perform key input again can be obtained.

Furthermore, even when a program with a larger load operates, the third feature is that it can automatically cope with it.
Can also be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of an embodiment of a terminal device according to the present invention.

FIG. 3 is an internal configuration diagram of the terminal device shown in FIG. 2;

FIG. 4 is a schematic diagram showing a data configuration of a memory M1 shown in FIG. 3;

FIG. 5 is a detailed diagram of a data configuration of a memory M1 shown in FIG. 4;

FIG. 6 is a flowchart showing the operation of the terminal device of the present invention.

FIG. 7 is a flowchart of a CPU clock frequency change processing subroutine in FIG. 6;

FIG. 8 is a communication sequence diagram showing an outline of the operation of the terminal device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Terminal device 2 Serial transmission cable 3 Telephone cable 4 Modular jack 5 Connector 6 Modem 7 Scanner 8 Input keyboard 9 Data display panel 100 Control unit 101 Communication control means 102 CPU clock frequency setting means 103 Transfer control means 104 Comparison means 200 Communication Controller 300 CPU 820 Switching center 821 Network controller 822 Modulator / demodulator 822 Communication controller 823 Main unit 830 Communication line 831 Communication line M1 Memory M10 Receive data area M11 Communication controller status data area M12 Communication controller transmission data area

Claims (5)

[Claims] When a process of reading received data is not in time for data reception, a request for retransmission of the received data is sent to a transmission side, and a clock frequency of a CPU for instructing the reading process is set high, and the request for retransmission is set. An information device, wherein the CPU speed is increased at the time of data reception processing for the information processing device. 2. An information device connected to a main unit via a communication line, wherein a reception data register in which data received from the main unit is written, a status register for holding a reception state, and transmission data to the main unit are stored. A communication controller that reads and writes these registers, including a transmission data register to be written; a CPU that notifies the arrival of the reception data when receiving the reception notification of the reception data from the communication controller; When receiving the notification, the communication controller performs reading processing of the reception data in the reception register, notifies the communication controller of the result, and compares the content of the status register with a predetermined value. Received data and whether the reading process is in time for receiving the data Comparing means for notifying the communication control means determines, when the reading process has not been in time to the data received, the CPU an instruction from the communication control means
CPU clock frequency setting means for raising the clock frequency of the data, and the communication controller, when the reading process is not in time for the data reception, sends information for notifying the main device of the transmission data to the transmission data. An information device for writing to a register. 3. When the reading process is not in time for the data reception, the CPU frequency is set to “medium” if the frequency is “low”, and “high” if the frequency of the CPU is “medium”. Item 3. The information device according to item 1 or 2. 4. A communication control method in an information device connected to a main device via a communication line, wherein when data received from the main device is written to a reception data register, a reception state is written to a status register. A step of notifying the CPU of the arrival of the received data, a step of reading the received data in the reception register upon receiving the notification of the arrival of the data from the CPU, and comparing the contents of the status register with a predetermined value. A step of determining whether the received data is the last received data, and determining whether the reading process is in time for the data reception and writing the received data in the status register as the reception state; and the reading process is not in time for the data reception. Sometimes, the step of increasing the clock frequency of the CPU and the step of reading the data A step of notifying the main device when it is not in time for the reception. 5. A communication control method in an information device connected to a main device via a communication line, wherein when data received from the main device is written to a reception data register, a reception state is written to a status register. Receiving the arrival of the received data to the CPU, receiving the notification of the arrival of the data from the CPU, reading the received data in the reception register, and comparing the contents of the status register with a predetermined value. A step of determining whether the received data is the last received data, and determining whether the reading process is in time for the data reception and writing the received data in the status register as the reception state; and the reading process is not in time for the data reception. Sometimes, the step of increasing the clock frequency of the CPU and the step of reading the data To when no match is recorded a computer-readable recording medium a program for implementing the communication control method in a computer and a procedure notifies to the main device.