JP2001043146A5 - - Google Patents

Description

[Document name] Specification [Title of invention] Non-volatile memory device and image forming device [Claims]
[Claim 1]
When the potentials of the first storage means , the second storage means , the capacitor connection terminal, and the capacitor connection terminal rise above a predetermined potential, the data of the second storage means is written or recalled to the first storage means. A non-volatile memory containing a controller that writes or stores the data of the first storage means to the second storage means when the potential drops below a predetermined potential;
Means for detecting the mounting state of the capacitor on the capacitor connection terminal;
A non-volatile memory device comprising.
2.
The means for detecting the mounting state are a switching means for turning on and off the charging path from the capacitor connection terminal to the capacitor, a means for temporarily turning off the switching means, and a means for returning to ON after the switching means is turned off. The non-volatile memory device according to claim 1, further comprising means for holding information indicating normal when the potential of the capacitor is high and abnormal when the potential of the capacitor is low.
3.
The non-volatile according to claim 1 or 2, further comprising a timer means for detecting the mounting state, which causes the controller to periodically store in response to the detection that the mounting state is abnormal. Memory device.
4.
Furthermore, if the CPU that writes and reads data to the non-volatile memory and the means for detecting the mounting state detects that the mounting state is abnormal, a store command is issued to the non-volatile memory. The non-volatile memory device according to claim 1 or 2, further comprising a CPU that is periodically issued and causes the controller to periodically store.
5.
The non-volatile memory device according to claim 1 or 2, further comprising a means for detecting the mounting state, which prohibits access to the non-volatile memory in response to detection that the mounting state is abnormal.
6.
Furthermore, if the CPU that writes and reads data to the non-volatile memory and the means for detecting the mounting state detects that the mounting state is abnormal, its own access to the non-volatile memory is prohibited. The non-volatile memory device according to claim 1 or 2, comprising a CPU.
7.
The non-volatile memory device according to claim 1 or 2, further comprising means for notifying information indicating detection that the mounting state is abnormal, as a means for detecting the mounting state.
8.
Further, the non-volatile memory is provided with a CPU that writes image process conditions, usage history data, and user setting data; the CPU is mounted as a means for detecting the mounting state immediately after the power is turned on. The image forming apparatus using the non-volatile memory apparatus according to claim 1 or 2, which gives a signal for detecting a state.
Description: TECHNICAL FIELD [Detailed description of the invention]
[0001]
[Technical field to which the invention belongs]
The present invention relates to a memory device, for example , when the potentials of a SRAM, an EEPROM, a capacitor connection terminal, and a capacitor connection terminal rise above a predetermined potential, the data of the EEPROM is written or recalled to the SRAM, and the potential is equal to or lower than the predetermined potential. The present invention relates to a memory device mainly composed of a non-volatile memory including a controller that writes SRAM data to EEPROM, that is, stores the data when the value is reduced to. In particular, is the external capacitor connected to the capacitor connection terminal, which temporarily holds the power supply voltage to secure the store when the power is turned off, properly connected or has an appropriate capacity? The present invention relates to a non-volatile memory device that automatically checks for abnormalities such as whether or not there is deterioration. This device is used for non-volatile storage of image formation information such as image process conditions, usage history data, user setting data, and abnormality history data in image forming devices such as printers and copiers. Be done.
0002.
[Previous technology]
In recent years, for example, an image forming apparatus having a high value-added function as shown in the following 1) to 3) has appeared:
1) A copier that stores usage history data such as the number of sheets used in a non-volatile memory and changes the image formation process control parameters according to the data so that stable images can be obtained over a long period of time.
2) A copier that stores historical data related to failures such as paper jams and self-diagnosis error results in a non-volatile memory so that appropriate aftercare can be received according to the stored results.
3) A copier that can customize the operation procedure by storing the operation procedure data that differs according to the user and purpose business in the non-volatile memory.
0003
By the way, in such an image forming apparatus, the data stored in the non-volatile memory is important as the image forming information, and there must be no problem such as data destruction. Further, in recent years, NVRAM is often used as a non-volatile memory for such purposes. This NVRAM has an advantage that it is smaller / cheaper than a magnetic memory such as a hard disk and does not require a power supply for backup as compared with a DRAM or SRAM.
0004
The NVRAM is a storage cell in which the cells of the SRAM and the cells of the EEPROM have a one-to-one correspondence, and has a function of storing the data of the SRAM in the EEPROM and a function of recalling the data of the EEPROM to the SRAM. FIG. 1 shows an example of a combination of NVRAM and its peripheral devices. As shown in FIG. 2, the NVRAM 9 is composed of a SRAM 92 and an EEPROM 91, stores the contents of the SRAM 92 in the EEPROM 91, and recalls the contents of the EEPROM 91 to the SRAM 92.
0005
The power supply circuit 1 of FIG. 1 supplies (ON) / disconnects (OFF) power to the main control panel 3 by the power supply SW2. After the power is turned on, the CPU 4 starts an operation by a program stored in the ROM 7 and performs a series of controls. FIG. 5 shows an example of the operation of the NVRAM 9. After the power is turned on, the recall operation is started when Vcc exceeds the trigger voltage Vsw. The recall operation usually ends in several tens of μs. After that, it is treated in the same way as a normal SRAM, and data is read / written by the CPU 4. When the power is off, the store operation starts when Vcc drops below the trigger voltage Vsw. The store operation usually ends in about several tens of ms. Conventionally, an external capacitor 10 is directly connected to the capacitor connection terminal (Vcap) of the NV RA M9 so that this store operation can be performed stably regardless of the descent time of the Vcc. The capacitance detection circuit 11 shown in FIGS. 1 and 2 is added by the present invention. The capacity of the capacitor is usually about 100 μF.
0006
Normally, a device such as EEPROM has a life of rewriting (several k times to several hundred k times), and if rewriting is performed every time CPU is accessed, the product life is not satisfied and the operation of the device cannot be guaranteed. There is a fear. On the other hand, in the case of NVRAM, the rewriting to EEPROM is performed only when the power is turned off, so that the product life can be satisfied.
0007
Further, recently, an NVRAM that rewrites (stores) the EEPROM 91 only when the data is updated to the SRAM 92 has been commercialized, and the life is further extended. An example thereof is disclosed in Japanese Patent Application Laid-Open No. 5-81148. In this case, a store request flag is set when the stored contents of the SRAM are changed, and the store is performed on the condition that this flag is present when the power is turned off. As a result, the number of store executions may be smaller than when the store operation is always performed when the power is turned off.
0008
[Problems to be Solved by the Invention]
Although NVRAM has many merits as described above, it has the following drawbacks. When the store operation depends only on the auto-store operation when the power is turned off Since this operation is performed by voltage compensation by the electric charge of the external capacitor 10, the capacitor 10 may come off due to some trouble, or it may be smaller than the target capacity. Or, if the capacity is lost due to deterioration over time, voltage compensation cannot be obtained and there is no voltage for store operation, or the voltage of the capacitor 10 can perform store operation while the store operation is not completed. It may drop to a low potential.
0009
In such a case, although the various important information as described above is updated on the SRAM 92, the data on the SRAM 92 is erased when the power is turned off because the information is not stored in the EEPROM 91. In order to avoid such a problem, if the store operation is performed in the EEPROM 91 every time the data of the SRAM 92 is updated, the long life due to the characteristics of the NVRAM is impaired.
0010
The present invention has been made in view of these points, and the first object of the present invention is to provide a non-volatile memory device that automatically detects the mounting state of a capacitor, and to prevent incomplete execution of store operation. a second object, to secure a second store in the storage means (91) of the data in the first storage means (92) as much as possible as a third object, data of the second storage means (91) The fourth purpose is to prevent the destruction of the capacitor and extend its life. The fifth purpose is to realize these by adding relatively inexpensive hardware.
0011
[Means for solving problems]
(1) When the potentials of the first storage means (92), the second storage means (91), the capacitor connection terminal (Vcap), and the capacitor connection terminal (Vcap) rise above the predetermined potential (Vsw), the first 2 The data of the storage means (91) is written or recalled to the first storage means (92), and when the potential drops below a predetermined potential (Vsw), the data of the first storage means (92) is stored in the second storage. Non-volatile memory (9), including a controller (93), which writes or stores to means (91); and
Means (11) for detecting the mounting state of the capacitor (10) on the capacitor connection terminal (Vcap);
Non-volatile memory device with (Fig. 1 / Fig. 8 / Fig. 11). In addition, in order to facilitate understanding, the reference numerals or corresponding items of the corresponding elements of the examples shown in the drawings and described later are added for reference.
0012
According to the non-volatile memory device of the present invention, since the detecting means (11) detects the mounting state of the capacitor (10), information indicating the mounting state of the capacitor (10) can be automatically obtained. Based on this information, it is possible to prevent incomplete execution of the store operation in the case of an implementation error.
0013
BEST MODE FOR CARRYING OUT THE INVENTION
(2) The means (11) for detecting the mounting state is a switching means (12) for turning on / off the charging path from the capacitor connection terminal (Vcap) to the capacitor (10), and a means for temporarily turning it off (12). 4/20), and a means (4 /) that holds information indicating normal when the potential of the capacitor (10) is high and abnormal when the potential of the capacitor (10) is returned to ON after the switching means (12) is turned OFF. 21); includes (Fig. 1 / Fig. 8 / Fig. 11).
0014.
When the switching means (12) is turned off, the potential is low because the capacitor (10) is not charged when the connection of the capacitor (10) is poor, and when the capacity is small, there is no charging and the potential rapidly increases due to discharge. descend. When the connection is complete and the capacitance is high enough, the potential drop due to discharge is very gradual. Therefore, when the connection is poor or the capacity is insufficient, the potential of the capacitor (10) when the switching means (12) returns to ON is low, and the holding means (4/21) holds the abnormality information. If the proper capacitor (10) is properly connected, the potential of the capacitor (10) is high and the holding means (4/21) holds the normal information. This configuration can be realized with relatively low cost hardware. Immediately after the power is turned on, the switching means (12) is turned off once to hold the abnormal / normal information in the holding means (4/21), and then based on the information of the holding means (4/21) until the power is turned off. Therefore, it is possible to automatically take measures for abnormal / normal response.
(3) Further, the timer means (4/19) of the means (11) for detecting the mounting state, which causes the controller (93) to periodically store in response to the detection that the mounting state is abnormal. (Fig. 1, Fig. 3 / Fig. 7). By setting this store cycle to an appropriate value in advance according to the rewrite frequency life of the non-volatile memory (9) and the assumed frequency of power OFF / ON, the data of the first storage means (92) is less likely to be lost. Moreover, the life of the non-volatile memory (9) is less shortened, and an automatic store is realized while the power is on.
(4) Further, when the CPU that writes and reads data to the non-volatile memory (9) and the means (11) for detecting the mounting state detects that the mounting state is abnormal, It is provided with a CPU (4); which periodically issues a store command to the non-volatile memory (9) and causes the controller (93) to periodically store. A CPU that reads and writes data to the non-volatile memory (9) can give a store command as one of the accesses through the non-volatile memory (9), and the non-volatile memory (9) can be given a store command. ) Executes the store in response to the store command. In this embodiment, utilizing this, the CPU (4) causes the non-volatile memory (9) to periodically store when the mounting state is abnormal. By setting an appropriate cycle in advance in the CPU (4) according to the life of the number of rewrites of the non-volatile memory (9) and the assumed frequency of power OFF / ON, the first storage means (92) can be stored. -The loss of data is small, the life of the non-volatile memory (9) is small, and the automatic store while the power is on is realized by software.
(5) Further, the means for detecting the mounting state (11) is provided with means (22); for prohibiting access to the non-volatile memory (9) in response to the detection that the mounting state is abnormal (Fig. 10). .. When the mounting state is abnormal, the non-volatile memory (9) is automatically disabled, the data of the first storage means (92) is not rewritten, and there is no store. Therefore, the data of the second storage means 91 is not available. -The memory is not destroyed.
(6) Further, when the CPU that writes and reads data to the non-volatile memory (9) and the means (11) for detecting the mounting state detects that the mounting state is abnormal, It is equipped with a CPU (4); which prohibits its own access to the non-volatile memory (9) (FIGS. 12 and 13). The CPU that accesses the non-volatile memory (9) for reading and writing data can set itself information that prohibits specific processing. In this embodiment, utilizing this, the CPU (4) prohibits access to its own non-volatile memory (9) when the mounting state is abnormal. When the mounting state is abnormal, the non-volatile memory (9) is automatically disabled, the data of the first storage means (92) is not rewritten, and there is no store. Therefore, the second storage means (91) Data is not destroyed.
(7) Further, the means for detecting the mounting state (11) is provided with means for notifying information indicating that the mounting state is abnormal (8 in FIG. 3/24 in FIG. 12). The operator or serviceman can check the external capacitor (10) and repair the abnormality according to this notification.
(8) Further, the non-volatile memory (9) is provided with a CPU (4); which writes image process conditions, usage history data, and user setting data; the CPU (4) is powered on. Immediately after, an image forming apparatus using the non-volatile memory device (9) that gives a signal (capacity detection CAD) for detecting the mounting state to the means (11) for detecting the mounting state.
(9) An image forming apparatus having a CPU (4) for writing image process conditions, usage history data, and user setting data into a non-volatile memory (9).
It has an output port (ST / TST) of the device (19) that can be controlled by the CPU (4) or the CPU (4), and the output port (ST / TST) is used as the non-volatile memory (9) to start the store operation. Connect to the external input (HTT) to let
If the detection means (11) detects that the external capacitor (10) is not properly mounted in the non-volatile memory (9), the output port (ST / TST) is periodically stored at the store indication level (L). ), An image forming apparatus characterized in that the store operation is performed regularly.
(10) The CPU (4) writes image process conditions, usage history data, and user setting data to the non-volatile memory (9), and the non-volatile memory (9) inputs commands to the CPU (4). In an image forming device that also performs store operation
When the detection means (11) detects that the external capacitor (10) is not mounted normally, the CPU (4) periodically issues a store command to the non-volatile memory (9) and periodically issues a store command to the non-volatile memory (9). An image forming apparatus characterized in that a store operation is performed.
(11) The CPU (4) writes image process conditions, usage history data, and user setting data to the non-volatile memory (9), and the non-volatile memory (9) inputs commands to the CPU (4). In an image forming device that also performs store operation
When the detection means (11) detects that the external capacitor (10) is not mounted normally, the CPU (4) sets access prohibition to the non-volatile memory (9). Image forming device.
0015.
Other objects and features of the present invention will become apparent from the description of the following examples with reference to the drawings.
0016.
【Example】
− First Example −
FIG. 1 shows a first embodiment of the present invention. This embodiment is a digital copier, and an image signal read by a document scanner (not shown) is sent to a writing controller 18 via a main control panel 3 under the control of a document scanner controller 16. Be done. An electrostatic latent image is formed on a photoconductor (not shown) according to the image signal sent to the writing controller 18, and the electrostatic latent image is developed and processed by a series of electrophotographic processes by the image forming process controller 17. Transfer, fixation and discharge to. The CPU 4 on the main control panel 3 performs a series of operations by the control program stored in the ROM 7. At that time, the RAM 8 is used as a work area, and the NVRAM 9 which is a non-volatile memory is used for storing various important information as described above.
[0017]
FIG. 2 shows the configuration of the feeding system of the NVRAM 9 and the capacitance detection circuit 11 for detecting the mounting state of the external capacitor 10. An electronic SW12 (normally closed switching element) that is normally turned on is provided between the external capacitor 10 and the capacitor connection terminal (Vcap) of the NVRAM 9.
0018
When the power is turned on and a predetermined voltage rises in each part of the image forming apparatus, the output of the reset circuit 6 rises, and in response to this rise, the CPU 4 reads the initialization program from the ROM 7 and executes the initialization process. .. When this initialization is completed, the CPU 4 temporarily turns off the electronic SW12 (detects the mounting state). When a predetermined voltage rises in each part of the image forming apparatus, the electronic SW12 is turned on and charging of the capacitor 10 starts. In the initialization process, the CPU 4 sets the output that turns on the electronic SW12 in the output port TT, so that the electronic SW12 keeps turning on. A constant voltage Vcc is applied to the capacitor 10 via the electron SW12, whereby the electric charge is charged, and the capacitor 10 is charged to substantially Vcc. In this charging process, the NVRAM 9 performs a recall operation when the charging voltage exceeds Vsw (see FIG. 5).
0019
After that, the CPU 4 turns off the power supply SW12 by the output port TT and detects the mounting state of the capacitor 10.
0020
By the way, the voltage during store operation when the power supply (Vcc = + 5V) is OFF is guaranteed by the electric charge of the capacitor 10. Further, although a detailed description of the inside of the NVRAM 9 is omitted, the backflow to the power supply line (Vcc) is blocked by the diode 94 (FIG. 2) so that the electric charge of the capacitor 10 is used only for the store operation.
0021.
If the capacitor 10 is normally mounted, that is, if the capacitance (capacitor 10) between the capacitor connection terminal (Vcap) of the NVRAM 9 and the equipment ground GND is equal to or greater than a predetermined value, the CPU 4 causes the output port TT. While the power supply SW12 is turned off, the potential drop rate of the capacitor 10 is slow, the FET 14 continues to be ON, and the potential of the resistor 15 is maintained at H (approximately + 5 V). However, if the capacitor 10 comes off due to some trouble, the capacity is smaller than the target capacity, or the capacity is lost due to system deterioration, the potential of the base of the FET 14 when the power supply SW12 is turned off. The decrease is rapid, the FET 14 changes from ON to OFF, and the potential of the resistor 15 decreases to L (equipment earth). By reading the potential (H: normal / L: abnormal) of the resistor 15, the detection of the mounting state of the capacitor is completed.
0022.
When a predetermined time tp (threshold value for normal / abnormal determination) elapses after the power supply SW12 is turned off, the potential of the resistor 15 is read, and the power supply SW12 is turned on to bring the normal state. When the power is turned off, the electric charge of the capacitor 10 is supplied to the Vcap via the diode 13 regardless of the ON / OFF state of the electronic SW12. Therefore, when the connection of the capacitor 10 is proper, the recall and the store are opened. It is possible. That is, when the capacitor 10 is charged by applying the voltage Vcc and the potential (charging voltage) of the capacitor 10 exceeds Vsw, the controller 93 of the NVRAM 9 is the storage data of the EEPROM 91 which is the second storage means. Is written to SRAM 92, which is the first storage means (recall). After that, if the voltage Vcc is continuously applied and the data is input or changed to the NVRAM 9 while the operator input and the image formation are repeated, the data of the SRM 92 is rewritten. After that, when the power is turned off and Vcc disappears, the power supply to the capacitor 10 is stopped, so the potential starts to decrease, and when it drops below Vsw, the controller 93 of NVRAM 9 stores the storage data of SRAM 92. Write to EEPROM 91 (store). FIG. 5 shows the change in the potential of the capacitor 10 and the operation of the controller 93 of the NVRAM 9 described above.
[0023]
FIG. 3 shows the contents of the “capacity detection” CAD executed immediately after the initialization of the CPU 4 shown in FIG. 1 immediately after the power is turned on, that is, the detection of the mounting state of the capacitor. When the initialization is completed, the CPU 4 waits for the passage of time td (step 1). When the time dt elapses, the CPU 4 turns off the electronic SW12, starts measuring the elapsed time Tm (steps 2 and 3), and waits for the time tp to elapse (step 4). This time tp is the time during which the potential of the capacitor 10 drops to a low potential after the electron SW12 is turned off when the capacitance (capacitor) of the capacitor 10 is abnormally low, and the tp value is a set value. When the capacitor 10 has a poor connection or an undercapacity, the potential of the capacitor 10 (the + terminal to which the capacitor 10 is connected) is low when tp elapses or immediately before that, so that the FET 14 is turned off (high impedance). -Dance), and the potential of the resistor 15 is L (equipment earth). This L means that the connection state of the capacitor 10 is bad. When the capacitor 10 with sufficient capacitance is properly connected, its potential drop during tp is small, and the FET 14 continues to be on (low impedance) even after tp, thereby causing the resistor 15 to stay on. The potential is H (approximately + 5V). This H means that the connection state of the capacitor 10 is good.
0024
The CPU 4 reads the potential (H: normal / L: abnormal) of the resistor 15 when the time tp elapses (step 5). Then, when it is H, the electron SW12 is turned back on (step 11), and the "capacity detection" CAD is terminated. When the read potential is L, the CPU 4 writes "1" indicating a capacitor connection error to the register FAca (step 7), and writes "NVRAM hardware error" to the liquid crystal display of the operation display board. Display (step 8), start the interrupt timer Tca (software timer with Tca time limit) (step 9), allow the timer Tca interrupt (step 10), turn the electronic SW12 back on (step 11), and then ". "Capacity detection" CAD is terminated.
0025
In the state where the timer Tca interrupt is enabled, the CPU 4 executes the “timer Tca interrupt” ITca shown in FIG. 4 every time the timer Tca times out. That is, when the timer Tca time expires, the process proceeds to the "timer Tca interrupt" ITca, where the timer Tca is restarted (step 21) and L is set in the output port ST (step 22). That is, L for storing is output to the hard store terminal HTT of NVRAM 9. Then, it waits for the time tt to elapse (steps 23 and 24), and when the tt elapses, the output port ST is returned to H (25). Then, the process returns to the process that was being executed immediately before the interrupt process was started. The time tt is a set value slightly longer than the time required to start and complete the store by giving L to the hard store terminal HTT of the NVRAM 9.
0026
In FIG. 6, the connection state of the capacitor 10 is poor, and as described above, the output of the port ST (the input of the hard store terminal HTT of the NVRAM 9) and the operation of the NVRAM 9 when the timer Tca interrupt is permitted. Show the relationship. After the CPU 4 enables the timer Tca interrupt, the CPU 4 uses the hard store terminal HTT to cause the NVRAM 9 to store in the Tca cycle until the power is turned off. Tca is appropriate in advance from the viewpoint of avoiding the loss of the data of the SRAM 92 of the NVRAM 9 as much as possible and reducing the number of stores as much as possible depending on the rewrite frequency life of the NVRAM 9 and the assumed frequency of power OFF / ON. It is set to a value.
[0027]
-Modification of the first embodiment-
As shown in FIG. 1, the CPU 4 has a system configuration for accessing NVRAM 9, initializing NVRAM 9 (clearing data), writing data to NVRAM 9, reading data from NVRAM 9, and NVRAM 9. Store (write the data of SRAM 92 to EEPROM 91) and the like can be performed by using an access command. In the first embodiment described above, when a connection abnormality of the capacitor 10 is detected, the NVRAM 9 is made to perform a store operation at a constant cycle Tca by using the hard store terminal HTT of the NVRAM 9, but in this modification, the hard store is performed. By using an access command, that is, by giving a store command without using the terminal HTT, the CPU 4 causes the NVRAM 9 to perform a store operation at a fixed cycle Tca.
[0028]
− Second Example −
FIG. 7A shows an outline of the second embodiment. When the connection of the external capacitor 10 is abnormal, the CPU 4 of the first embodiment directly causes the NVRAM 9 to perform the store operation, but in the second embodiment, the timer 19 is provided and the NVRAM 9 is subjected to the store operation by the timer 19. Let me. FIG. 7 shows the input / output signals of the timer 19. The CPU 4 of the second embodiment performs the "capacity detection" CAD as in the first embodiment, but when it detects a connection abnormality, it operates the timer 19. That is, the enable signal level given to the timer 19 is switched from the disable (non-operation) instruction H to the enable (operation) instruction L. The timer 19 gives a store instruction pulse (L) to the hard store terminal HTT of the NVRAM 9 at a constant cycle Tca while there is an operation instruction (L). As a result, the NVRAM 9 performs a store operation with a period of Tca.
[0029]
− Third Example −
FIG. 8 shows another embodiment of the capacitance detection circuit, and the input / output signals thereof are shown in FIG. The capacitance detection circuit 11A of this embodiment is obtained by adding a one-shot pulse generator 20 and a D flip-flop (hereinafter referred to as DFF) to the capacitance detection circuit 11 of the first embodiment shown in FIG. The one-shot pulse generator 20 is triggered by the rising edge of the reset signal SETT from the reset circuit 6 (FIG. 1) to start the timed operation of the timed value Td, and when Td elapses, the L pulse (ONE SHOT PULSE) of the set width is started. ) Is output to the electronic SW12 and DFF21. The electronic SW12 is turned off during the L pulse width, and the DFF 21 is the potential of the resistor 15 (H: normal / L:) at the end point of the L pulse, that is, the rising point of the output signal of the pulse generator 20 from L to H. Abnormal) is taken in. That is, it latches and continuously outputs the potential to the Q output end. Therefore, after the one-shot pulse generator 20 outputs a 1-pulse (L) ONE SHOT PULSE in response to the reset signal, if the proper capacitor 10 is properly connected to the NVRAM 9, the Q output of the DFF 21 will be , However, when an appropriate capacitor is not connected to the NVRAM 9, it remains at L, which indicates an abnormality. This detection signal (Q output) is given to the NVRAM access control unit 22 shown in FIG.
[0030]
FIG. 10 shows a main control board 3A equipped with the capacitance detection circuit 11A shown in FIG. The main control board 3A is incorporated in the image forming apparatus 100 in place of the main control board 3 shown in FIG. Although the external capacitor 10 is not shown in FIG. 10, the external capacitor 10 is also connected to the NVRAM 9 and the capacity detection circuit 11A on the main control panel 3A in the manner shown in FIG. ing.
0031
The CPU 4 on the main control plate 3A gives an NVRAM chip select signal (a signal that specifies NVRAM as an access destination) CSNVRAM (L active: L level means NVRAM designation) to NVRAM 9, and NVRAM access control is performed on this signal line. The part 22 is inserted. The NVRAM access control unit 22 has a number 23, and an inverted signal of the inverted signal of the chip select signal CSNVRAM and the logical product of the Q output of the DFF 21 of the capacitance detection circuit 11A is added to the chip select input terminal of the NVRAM 9. ..
[0032]
As a result, when the connection of the capacitor 10 to the NVRAM 9 is appropriate (good connection & high capacitance), the capacitance detection circuit 11A gives H indicating normality to the Nandogate 23, so that the output of the Nandogate 23, that is, the chip to the NVRAM 9 The select signal has the same level as the chip select signal given by the CPU 4, and the CPU 4 can initialize (delete data), recall, write, read, and store the NVRAM 9 by an access command.
0033
However, when the connection of the capacitor 10 to the NVRAM 9 is defective (connection failure or low capacity), the capacitance detection circuit 11A gives L indicating an abnormality to the Nandogate 23, so that the output of the Nandogate 23, that is, the chip select to the NVRAM 9 The signal is the H of the disposable instruction regardless of whether the chip select signal given by the CPU 4 is L for designating (accessing) the NVRAM 9 or H for the diseasable instruction (non-designated = non-access specified). Be restrained. As a result, the CPU 4 cannot access (initialize, recall, write, read, and store) the NVRAM 9. Therefore, the data of the EEPROM 91 of the NVRAM 9 is not changed. Incomplete execution of store operation is prevented.
0034
− Fourth Example −
FIG. 11 shows another embodiment of the capacitance detection circuit. In the capacitance detection circuit 11B of this embodiment, the one-shot pulse generator 20 is omitted from the capacitance detection circuit 11A shown in FIG. 8, a pulse for turning off the electronic SW12 is given from the CPU 4, and a detection signal is given to the CPU 4. It is something like that.
0035.
FIG. 12 shows a main control board 3B equipped with the capacitance detection circuit 11B shown in FIG. This main control plate 3B is also incorporated in the image forming apparatus 100 in place of the main control plate 3 shown in FIG. Although the external capacitor 10 is not shown in FIG. 12, the external capacitor 10 is also connected to the NVRAM 9 and the capacity detection circuit 11B on the main control panel 3B in the manner shown in FIG. ing.
0036
FIG. 13 shows the contents of the “capacity detection” CAD executed immediately after the initialization of the CPU 4 shown in FIG. 12 immediately after the power is turned on, that is, the detection of the mounting state of the capacitor. When the initialization is completed, the CPU 4 waits for the passage of time td (step 1). When the time dt elapses, the CPU 4 switches the output port TT from the high level H to the low level L, turns off the electronic SW12, and starts measuring the elapsed time Tm (steps 2 and 3), and the time tp changes. Wait for it to elapse (step 4). When the time tp elapses, the output port TT is returned to H and the electronic SW12 is returned to ON (step 5A). As described above, an L pulse (L pulse) is given to the electrons SW12 and DFF21 from the output port TT of the CPU 4 during tp. The DFF 21 takes in the potential of the resistor 15 (H: normal / L: abnormal) at the end point of the L pulse, that is, the rising point from L to H. That is, it latches and continuously outputs the potential to the Q output end.
0037
The Q output is given to the abnormality indicator 24 and the CPU 4. When the Q output is L (abnormal), the abnormality indicator 24 outputs H by the inverter 25 to light the light emitting element 26 for displaying the abnormality.
[0038]
The CPU 4 refers to the Q output (step 6A), and if it is L (abnormal), sets an NVRAM access prohibition flag in its own register. That is, the prohibited information is written (step 8A). When the Q output is H (normal), the prohibition flag is lowered. That is, the register addressed to the writing of prohibited information is cleared (7A). After that, until the power is turned off, the CPU 4 refers to the presence / absence of the prohibition flag at the stage (timing) of accessing the NVRAM 9, and if there is a prohibition flag, the actual access to the NVRAM 9 is suspended, and only when there is no prohibition flag. Actually access. Therefore, while the DFF 21 holds (latch) the L (Q output) indicating an abnormality, the CPU 4 prohibits its own access to the NVRAM 9, and does not rewrite or store the data of the NVRAM 9. Incomplete execution of store operation is prevented.
[0039]
In this fourth embodiment, the CPU 4 determines whether or not to actually access the NVRAM 9 by referring to the presence or absence of the prohibition flag according to the program. Therefore, for example, only the data writing (store) to the EEPROM 91 is performed. By stipulating that the recall and reading / writing of data to the SRAM 92 are executed without executing the above, it is possible to realize a mode in which the functions of the SRAM 92 can be used, and it is possible to flexibly deal with the program.
[Simple explanation of drawings]
FIG. 1 is a block diagram showing an outline of an electric system according to a first embodiment of the present invention.
FIG. 2 is an electric circuit diagram showing a connection between the capacitance detection circuit 11 shown in FIG. 1 and a feeder line of the NVRAM 9.
FIG. 3 is a flowchart showing the contents of the function “capacity detection” CAD of the CPU 4 shown in FIG.
FIG. 4 is a flowchart showing the contents of the CPU 4 function “timer Tca interrupt” ITca shown in FIG.
5 is a time chart showing the operation of the NVRAM 9 shown in FIG. 1 in response to a voltage change of the capacitor 10. FIG.
6 is a time chart showing the timing of store operation of NVRAM 9 when the connection state of the capacitor 10 of the CPU 4 shown in FIG. 1 is abnormal. FIG.
FIG. 7A is a block diagram showing an outline of a main part of the configuration of the second embodiment of the present invention, and FIG. 7B is a block diagram in which the timer 19 stores NVRAM 9 when the connection state of the capacitor 10 is abnormal. It is a time chart which shows the timing to make it.
FIG. 8 is a block diagram showing a configuration of a capacitance detection circuit 11A used in the third embodiment of the present invention.
9 is a time chart showing input / output signals of the capacitance detection circuit 11A shown in FIG. 8. FIG.
FIG. 10 is a block diagram showing a main part of the configuration of the third embodiment of the present invention using the capacitance detection circuit 11A shown in FIG.
FIG. 11 is a block diagram showing a configuration of a capacitance detection circuit 11B used in a fourth embodiment of the present invention.
FIG. 12 is a block diagram showing a main part of the configuration of the fourth embodiment of the present invention using the capacitance detection circuit 11B shown in FIG.
FIG. 13 is a flowchart showing the contents of the function “capacity detection” CAD of the CPU 4 shown in FIG.
[Explanation of symbols]
5: Clock oscillator 6: Reset circuit 14: FET 21: D flip-flop 23: Nandogate 24: Abnormality indicator 25: Inverter 26: Light emitting element