JP2001043133A - マルチプロセッサ・システムにおいてライトスルー・ストア・オペレーションでキャッシュ・コヒーレンシを維持するための方法およびシステム - Google Patents

マルチプロセッサ・システムにおいてライトスルー・ストア・オペレーションでキャッシュ・コヒーレンシを維持するための方法およびシステム

Info

Publication number
JP2001043133A
JP2001043133A JP2000180625A JP2000180625A JP2001043133A JP 2001043133 A JP2001043133 A JP 2001043133A JP 2000180625 A JP2000180625 A JP 2000180625A JP 2000180625 A JP2000180625 A JP 2000180625A JP 2001043133 A JP2001043133 A JP 2001043133A
Authority
JP
Japan
Prior art keywords
write
cache
store operation
system bus
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000180625A
Other languages
English (en)
Japanese (ja)
Inventor
Meranio Nunetsu Jose
ホセ・メラニオ・ヌネツ
Albert Petersen Thomas
トーマス・アルバート・ピーターセン
Janette Sullivan Marie
マリー・ジャネット・サリバン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2001043133A publication Critical patent/JP2001043133A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2000180625A 1999-06-18 2000-06-15 マルチプロセッサ・システムにおいてライトスルー・ストア・オペレーションでキャッシュ・コヒーレンシを維持するための方法およびシステム Pending JP2001043133A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US33651699A 1999-06-18 1999-06-18
US09/336516 1999-06-18

Publications (1)

Publication Number Publication Date
JP2001043133A true JP2001043133A (ja) 2001-02-16

Family

ID=23316452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000180625A Pending JP2001043133A (ja) 1999-06-18 2000-06-15 マルチプロセッサ・システムにおいてライトスルー・ストア・オペレーションでキャッシュ・コヒーレンシを維持するための方法およびシステム

Country Status (4)

Country Link
JP (1) JP2001043133A (zh)
KR (1) KR100380674B1 (zh)
CN (1) CN1149494C (zh)
TW (1) TW548547B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320464C (zh) * 2003-10-23 2007-06-06 英特尔公司 用于维持共享高速缓存一致性的方法和设备
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7725619B2 (en) * 2005-09-15 2010-05-25 International Business Machines Corporation Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes
US7568073B2 (en) * 2006-11-06 2009-07-28 International Business Machines Corporation Mechanisms and methods of cache coherence in network-based multiprocessor systems with ring-based snoop response collection
GB0623276D0 (en) * 2006-11-22 2007-01-03 Transitive Ltd Memory consistency protection in a multiprocessor computing system
US20120254541A1 (en) * 2011-04-04 2012-10-04 Advanced Micro Devices, Inc. Methods and apparatus for updating data in passive variable resistive memory
US10970225B1 (en) * 2019-10-03 2021-04-06 Arm Limited Apparatus and method for handling cache maintenance operations

Also Published As

Publication number Publication date
CN1278625A (zh) 2001-01-03
KR20010015008A (ko) 2001-02-26
CN1149494C (zh) 2004-05-12
TW548547B (en) 2003-08-21
KR100380674B1 (ko) 2003-04-18

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