JP2001036482A - Communication fault detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily detect the fault caused by the delay of a common clock signal and to appropriately deal with the fault by specifying a fault factor range at the time of a communication fault caused by step-out in the communication which is subordinately synchronized with the common clock signal. SOLUTION: When a communication fault owing to step-out is detected with an opposite device in a transmission/reception part 18-1, the transmission/ reception part 18-1 informs a signal processing part 16 of it. The signal processing part 16 gives the instruction of the transmission of a test clock signal with a -1/8 clock phase to the transmission/reception part 18-1 to the controller 28 of a clock control part through a bus. The controller 28 receives the instruction, controls a switch part 34 and returns a response signal to the signal processing part 16. The switch part 34 changes over a system to the supply of the test clock signal with the -1/8 clock delay phase from a common clock signal to the transmission/reception part 18-1 with the control of the controller 28. Thus, the transmission/reception part 18-1 executes communication in synchronizing with the test clock of the -1/8 clock phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting a communication failure, and more particularly to a communication failure detection apparatus for performing synchronous communication according to a common clock signal via a transmission line.

[0002]

2. Description of the Related Art A conventional communication failure detecting apparatus will be described with reference to a system block diagram of FIG. FIG. 3 is a block diagram of a system configuration of a communication failure detection device according to the related art.

The clock receiving section 26 of the signal transmitting / receiving device 36
Receives a clock signal and a frame synchronization signal from an external common clock signal device 14 to perform synchronous communication, and supplies the same to the transmission / reception units 12-1 and 12-2 as a transmission clock and a reception clock. Transmission / reception unit 12-1, 1
2-2 transmits the data transmitted from the signal processing unit 16 in synchronization with the received clock signal and frame synchronization signal to the opposing device 12 via the line drivers 20-1 and 20-2.
-1, 12-2. Opposing devices 12-1, 12-
2 is transmitted to the line receivers 22-1 and 22-1,
The data is received by the transmission / reception units 12-1 and 12-2 via 22-2. The transmission / reception units 12-1 and 12-2 receive the received data in synchronization with the clock signal and the synchronization frame signal from the clock reception unit, and transmit the received data to the upper signal processing unit 16. The common clock signal is transmitted to each of the signal transmitting / receiving devices 36 and the opposing devices 12-1, 1 and 1 via a transmission line or a dedicated cable.
2-2, the phase difference of the common clock signal may occur between the devices due to the cable length or the delay of the transmission line.

[0004] In addition, a phase difference may occur due to distortion of the waveform of a clock signal due to line impedance, external noise, or the like. If the phase difference between the clock signals exceeds the allowable value, the synchronous communication between the transmission data and the reception data is disturbed, resulting in transmission and reception of erroneous data. If the clock received by the signal transmitting / receiving device 36 exceeds the allowable value for the common clock signal due to the above-described factors, the transmission data is transmitted to the opposing device 12-1 while being synchronized with the delayed clock. Opposing device 12-1
Assuming that the transmission data transmitted from the signal transmission / reception device 36 is received from the common clock signal device 14 with a delay within the allowable range, the opposite device 12-1 receives the transmission data with a phase difference between the clock signals of the two devices. Detects a communication error. Similarly, the transmission data from the opposing device 12-2 is received by the signal transmission / reception device 36 with the phase difference of the clock signal shifted, and the signal transmission / reception device 36 detects a communication abnormality.

An example of a conventional method for detecting a communication failure is described in Japanese Patent Application Laid-Open No. Hei 3-222525. The duplex automatic switching control method described in this publication
The working and protection line side interface devices of one and the other stations connected via a digital line are provided with a synchronization pattern detection unit, an out-of-synchronization alarm signal detection unit, and a synchronization bit addition unit, respectively.

In this duplex automatic switching control method, when an out-of-synchronization alarm signal from a partner station is detected by an out-of-sync alarm signal detector of its own station, transmission data from its own working line side interface device is transmitted to a protection line side. Returning to the interface device, if the synchronization pattern detection unit of the protection line interface device detects out-of-sync from the input device, it judges that the transmission unit of the working line interface device of its own station has a failure, and the protection line interface device Switch.

Further, in the duplex automatic switching control system, when an out-of-synchronization alarm signal is transmitted from the own station, data from the protection line-side interface device is added back to the synchronization pattern detection unit of the working line-side interface device, and the synchronization is lost. Occurs, it is determined that a failure has occurred in the receiving unit of the working line-side interface device, and the switch is made to the protection line-side interface device.

[0008]

As shown in FIG. 3 described above, the conventional communication failure detecting device, when a phase difference of more than an allowable value occurs between the two communicating devices in the received common clock signal, causes the device to fail. Since it is not possible to identify the magnitude of the delay of the received common clock signal, it is not possible to determine whether the cause is on the own device side or on the opposite device side. Further, it cannot be specified that the cause of the communication abnormality is the delay of the common clock signal. For this reason, it is necessary to perform a loopback test and the like on the opposing device side via the transmission path in order to determine the cause of the communication failure, which takes time.

[0009] The duplex automatic switching control system described in Japanese Patent Application Laid-Open No. 3-222525 is for switching from the active unit to the standby unit by detecting out-of-synchronization. Switching was performed regardless of the cause of the loss of synchronization.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication fault detecting apparatus which eliminates the above-mentioned drawbacks of the communication fault detecting apparatus, can quickly detect a fault due to a delay of a common clock signal, and can take appropriate measures. is there.

[0011]

According to the present invention, there is provided a communication failure detecting apparatus having a transmitting / receiving apparatus for performing synchronous communication in accordance with a common clock signal via a transmission line. A circuit for generating a plurality of clock signals synchronized in phase with a phase shift, and a circuit for switching between the clock signal output from the circuit for generating the clock signal and the received common clock signal for each signal transmitting / receiving circuit And a circuit that detects a loss of synchronization of communication and switches a clock signal to a corresponding transmitting / receiving circuit to either the common clock signal or the generated clock signal under the control of the switching circuit. And

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A communication fault detecting device according to the present invention is a communication fault detecting device having a transmitting / receiving device for performing synchronous communication depending on a common clock signal via a transmission line. A circuit for generating a plurality of clock signals synchronized and phase-shifted stepwise;
A circuit that switches the clock signal output from the circuit that generates the clock signal and the received common clock signal for each signal transmitting and receiving circuit, and detects a loss of synchronization of communication, thereby converting the clock signal to the corresponding transmitting and receiving circuit. A circuit for switching to either the common clock signal or the generated clock signal under the control of a switching circuit.

The configuration of an embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a diagram showing a configuration of a communication failure detection device according to the present invention. FIG. 2 is a block diagram of the transmission / reception device of the present invention.

As shown in FIG. 1, the communication fault detecting device of the present invention includes a transmitting / receiving device 10, opposing devices 12-1 and 12-2, and a common clock signal device 14. Transmitting / receiving device 10
Are connected to the opposing devices 12-1 and 12-2 via transmission lines. Further, in order to perform synchronous communication between the devices, a clock signal and a frame synchronization signal are supplied from the common clock signal device 14 to the transmission / reception device 10 and the opposing devices 12-1 and 12-2.

The signal processing unit 16 of the transmission / reception device 10 is connected to the transmission / reception units 18-1 and 18-2 via a bus, and performs input / output of transmission / reception data. Common clock signal device 1
The four common clock signals and the frame synchronization signal are received by the clock receiving unit 16 and sent to the clock phase control unit 24. The clock phase control unit 24 generates clocks of leading and lagging phases based on the input clock and sends them to the transmitting / receiving units 18-1 and 18-2. The transmission / reception units 18-1 and 18-2 transmit and receive data in synchronization with the clock supplied from the clock generation unit 24, by the line drivers 20-1 and 20-2 and the line receivers 22-1 and 22-2.
-2.

The clock phase controller 24 has a controller 28, a frequency multiplier 30, a clock generator 32, and a switch 34, as shown in FIG. When receiving the common clock signal of the AMI code from the outside, the clock receiving unit 26 extracts the clock signal and the frame synchronization signal, and sends them to the frequency multiplying unit 30. Frequency multiplier 30
Generates an eight-fold frequency synchronized with the input clock signal and sends it to the clock generation unit 32. The clock generation unit 32 generates 1 /
A clock having a lag phase and an advance phase of 8 to 8/8 clocks is generated and sent to the switch unit 34. The switch unit is configured to output the delay phase (hereinafter, “−”) output from the clock generation unit.
) / A clock signal (hereinafter referred to as a test clock signal) having a leading phase (hereinafter referred to as +) and a clock receiving unit 2
The clock signal (hereinafter, referred to as a common clock signal) output from 6 is switched for each of the transmission / reception units 18-1 and 18-2 under the control of the controller 28. Controller 2
Reference numeral 8 inputs and outputs a control signal and a response signal to and from the signal processing unit 16 via a bus.

Next, the operation of the embodiment of the present invention will be described.

If the transmission / reception unit 18-1 detects a communication failure due to loss of synchronization with the opposing device, the transmission / reception unit 18-1 notifies the signal processing unit 16 of the detection. The signal processing unit 16 instructs the controller 28 of the clock control unit via the bus to transmit a test clock signal of −−１ clock phase to the transmission / reception unit 18-1. The controller 28 receives this instruction, controls the switch unit, and returns a response signal to the signal processing unit 16. The switch unit 34 switches the supply of the common clock signal to the supply of the test clock signal having a phase delayed by −１ clock to the transmission / reception unit 202 under the control of the controller. As a result, the transmission / reception unit 18-1 performs communication in synchronization with the test clock having a phase of ク ロ ッ ク clock. As a result, the transmission / reception unit 16
When it detects recovery from communication failure due to loss of synchronization,
This is notified to the signal processing unit 16. The signal processing unit 16 recognizes that the communication failure has been recovered by the test clock having the phase of −１ clock, and stores this information in the memory. −1/8
When the communication failure is not recovered by the test clock of the clock phase, the signal processing unit 16 instructs the controller 28 of the clock control unit to transmit a test clock of −2/8 clock phase.

Similarly, the transmission / reception unit 18-1 operates at -2/8.
Performs communication in clock phase. In this way, the delay phase of the test clock is increased by 1/8 clock at a time, and the restoration of the communication failure is confirmed each time. In the present embodiment, at most -8 /
The phase is increased to 8 clock phases, and if no communication failure is recovered, the test clock is switched to the test clock with the 1/8 clock advance phase, and the test clock is increased to the maximum +8/8 clock advance phase. As a result, it is possible to confirm that the communication failure is recovered by any of the test clocks. In the present embodiment, the allowable value is up to ± 1/8 phase, and the obstacle is ± 2/8 to 8/8 phase.

Further, based on the test results, the signal processing unit 1
In step 6, the latest test result in the other transmitting / receiving unit 18-2 is referred to to determine whether the cause is on the own device side or on the opposite device side. For example, the transmission / reception unit 18-1
If the test result at step (1) is −3/8 phase, the latest test result of the transmission / reception unit 18-2 is referred to. If the result is a failure, the cause is the common clock signal delay and signal processing unit at the own device. The judgment is made at step 16, and a message of "own station clock abnormality" is output.

If the latest result of the transmission / reception unit 18-2 is within the allowable range, it is determined that the common clock signal is delayed on the opposite device side of the transmission / reception unit 18-1. Abnormal "message is output.

[0022]

As described above, the communication failure detecting device of the present invention, when a communication failure occurs due to loss of synchronization, sets the leading or lag phase of the received common clock signal by 1/8 clock at a time. By confirming the restoration of communication failures while increasing the number, the result is compared with the results of other transmission / reception units in the device, so that the cause of the communication failure is either on the local device side or on the opposite device side. Has the effect of being able to detect Also, as a result,
Necessary measures can be taken promptly, and the effect of a communication failure can be minimized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a communication failure detection device of the present invention.

FIG. 2 is a block diagram of a transmitting / receiving apparatus according to the present invention.

FIG. 3 is a block diagram of a system configuration of a communication failure detection device according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Transmission / reception apparatus 12-1, 12-2 Opposition apparatus 14 Common clock signal apparatus 16 Signal processing part 18-1, 18-2 Transmission / reception part 20-1, 20-2 Line driver 22-1, 22-2 Line receiver 24 clock Phase controller 26 Clock receiver 28 Controller 30 Frequency multiplier 32 Clock generator 34 Switch unit 36 Signal transmitting / receiving device

Claims (6)

[Claims] A communication failure detecting device comprising a transmitting / receiving device that performs synchronous communication in accordance with a common clock signal via a transmission line, wherein the communication device performs communication in synchronization with a common clock signal through a transmission line. On the other hand, a communication failure detection device characterized in that a failure factor location is specified when a communication failure occurs due to loss of synchronization. 2. A common clock signal device for supplying a clock signal and a frame synchronizing signal; and a plurality of clock signals synchronized with the received common clock signal and having a phase shifted in steps, A signal and the received common clock signal are switched for each of the transmitting and receiving devices, out-of-synchronization of communication is detected, and a clock signal to the corresponding transmitting and receiving device is controlled to control either the common clock signal or the generated clock signal. The communication failure detection device according to claim 1, further comprising: a transmission / reception device that switches to the communication device. 3. The transmission / reception device is connected to a transmission / reception unit via a bus, receives a common clock signal and a frame synchronization signal, and receives a signal processing unit for inputting / outputting transmission / reception data,
A clock receiving unit to be output, a clock phase control unit that receives the common clock signal and the frame synchronization signal, generates a clock having a leading and lagging phase based on the clock, and sends the clock, and is supplied from the clock phase controlling unit. 3. The communication failure detection device according to claim 2, further comprising: a transmission / reception unit that transmits / receives data in synchronization with the clock via a line driver and a line receiver. 4. The clock phase controller has a controller, a frequency multiplier, a clock generator, and a switch. When receiving the common clock signal, the clock phase controller extracts a clock signal and a frame synchronization signal, and A clock receiving unit to be sent to the multiplying unit, an eight-fold frequency synchronized with the input clock signal generated, and a frequency multiplying unit to be sent to the clock generating unit; 8 (n
Is an integer from 1 to 8) clock lag phase and n /
A clock generation unit that generates a clock having an 8-leading phase and sends the clock to the switch unit; a test clock signal having a delay phase / leading phase output from the clock generation unit; and a common clock output from the clock reception unit A switch unit for switching a signal for each transmission / reception unit under the control of the controller; and a controller for inputting / outputting a control signal and a response signal to / from the signal processing unit via a bus. Item 4. The communication failure detection device according to Item 3. 5. A clock signal having a phase shifted from the common clock signal received by the transmission / reception device in a stepwise manner, recovery of a communication failure is confirmed in each clock signal, and a phase difference between the clock signals is generated. 5. The communication failure detection device according to claim 4, wherein the communication failure detection device identifies the cause of the failure by itself or another device by detecting the failure and comparing the phase difference. 6. A communication fault detecting device having a transmitting and receiving device for performing synchronous communication in accordance with a common clock signal via a transmission line, wherein the plurality of devices are synchronized with the received common clock signal and are shifted in phase. A circuit for generating a clock signal, a circuit for switching between the clock signal output from the circuit for generating the clock signal and the received common clock signal for each signal transmitting and receiving circuit, and And a circuit for switching a clock signal to the transmitting / receiving circuit to either the common clock signal or the generated clock signal under the control of the switching circuit.