JP2001036027A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently reduce leakage current when using a noble metal electrode, especially the leakage current of a capacitor, which uses a functional material film and a nobel metal electrode. SOLUTION: A lower electrode 13, made of ruthenium, is formed into a thickness of about 50 nm on a thermal oxide film 12. Then, the lower electrode 13 is annealed in a mixed gas of argon and hydrogen at about 800 deg.C for about 2 min. Next, a capacitor insulation film 14 made of Ta2O5 is formed into a thickness of about 17 nm on the lower electrode 13. Thereafter, an upper electrode 15 made of ruthenium is selectively formed on the capacitive insulation film through sputtering method. Thereby, the surface of crystal grains of ruthenium, of which the lower electrode 13 is made, is formed stepwise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor capable of reliably suppressing a leakage current and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, it has become necessary to improve the performance by utilizing the characteristics of the materials constituting the semiconductor devices. In high integration of dynamic random access memory (DRAM) and ferroelectric random access memory (FeRAM) which store information by combining transistors and capacitors, not only miniaturization of transistors but also miniaturization of capacitors are essential. Become.

In particular, a capacitor needs to have a capacitance value equal to or greater than a predetermined value even if the area of the capacitor portion is reduced due to the problem of noise and soft errors, even if the size of the capacitor portion is reduced. For this reason, a conventional laminated film of a silicon oxide film and a silicon nitride film, so-called ON
Functional material films having a higher dielectric constant than the O film have been studied.

For example, a tantalum pentoxide (Ta ₂ O ₅ ) film, a strontium titanate (SrTiO ₃ , hereinafter abbreviated as STO), a barium titanate (hereinafter, abbreviated as STO), or the like is used as a functional material film as a high dielectric material. BaTiO ₃ , hereinafter B
Abbreviated as TO), barium strontium titanate film _{(Ba x Sr 1-x TiO} 3, hereinafter, an oxide dielectric thin film of the perovskite type, such as abbreviated as BST) has been studied.

However, when these functional material films are used for a capacitor insulating film of a capacitor, polycrystalline silicon cannot be used as a material of an electrode as in the conventional case. This is because the functional material film is often formed in an oxidizing atmosphere, and the surface of polycrystalline silicon is oxidized to form a silicon oxide film. Since the silicon oxide film has a low dielectric constant, even if a high dielectric is used for the capacitive insulating film, the silicon oxide film having a low dielectric constant will reduce the effective amount of accumulated charges.

Therefore, when a functional material film is used,
Platinum (Pt), ruthenium (Ru) or iridium (I
An electrode made of a noble metal such as r) is used.

Ta ₂ O ₅ as a functional material film for a capacitor
An example using a membrane is described in Japanese Journal of Applied Physics, 1998, No. 37, 1336.
Pp. 1339. An example using a BST film as a functional material film is described in Technical Digest of International Electron Device and Materials, 1998, pp. 253-2.
It is described on page 56.

Among these noble metal materials, Ru is particularly oxide whose conductive material is ruthenium dioxide (RuO ₂ ), and ruthenium tetroxide (RuO ₄ ) has a high vapor pressure at a low temperature and can be processed by dry etching. Therefore, it is very promising as an electrode material.

However, these functional material films having a high dielectric constant generally have a tendency that the higher the dielectric constant, the higher the leakage current density between the electrodes when a voltage is applied between the electrodes. The increase in the leak current density causes the amount of accumulated charge to decrease with the passage of time, so that there is a problem that the time during which the charge of the DRAM can be held is shortened.

Next, a brief description will be given of a conventional example described in the 54th Symposium on Semiconductors and Integrated Circuits (pages 12 to 17). According to this paper, on a thermal oxide film formed on a substrate made of silicon,
A lower electrode made of ruthenium with a thickness of nm is formed, and a heat treatment is performed on the formed lower electrode in a nitrogen atmosphere at a temperature of 700 ° C. for 30 seconds.

Then, using a chemical vapor deposition (CVD) method
With a film thickness of 24 nm on the lower electrode_TwoO_FiveForm a film
You. In this state, Ta_TwoO_FiveThe composition of the film is determined from the chemical quantitative value.
Apart from that Ta is excessive. Leakage current
Since the flow value is very large, as a remedy,
Annealing is performed in an oxygen atmosphere at a temperature of 1 ° C. for one hour. This
Annealing when the electric field strength is 1 MV / cm
Peak current density is 1 × 10 ^-8A / cm^Two At this time
Has a relative dielectric constant of 30.

As another method for supplementing oxygen, a temperature of 3
Oxygen plasma annealing is performed at 00 ° C. for 10 minutes. By this oxygen plasma annealing, the relative dielectric constant becomes 30
And the leak current density is 1.5 MV /
cm × 1 × 10 ⁻⁸ A / cm ² .

[0013]

However, the conventional capacitor has a small leakage current value after an annealing process in an oxygen atmosphere at a temperature of 550 ° C. for one hour or an oxygen plasma annealing process. The Ta ₂ O ₅ film is not crystallized and has a small dielectric constant of about 30. At this level of dielectric constant, there is not much improvement as compared with a capacitor using a conventional oxynitride film and a roughened polysilicon electrode, so that the advantage of using an electrode made of ruthenium and a Ta ₂ O ₅ film is superior. There is no sex.

To increase the dielectric constant, use Ta_TwoO_FiveFor membrane
And annealing at a temperature of about 700 ° C._Two
O_FiveNeed to be crystallized. According to the above lecture paper
And Ta _TwoO_FiveAs a method of crystallizing a film, a temperature of 750 is used.
Annealing is performed for 60 seconds in a nitrogen atmosphere at ℃.
Ta_TwoO_FiveElectrical properties after crystallizing the film supplement oxygen
The method is as follows.
In the case of the nealed sample, the dielectric constant is about 60,
The leak current density when the electric field strength is 1 MV / cm is 1 ×
10^-FiveA / cm^Two It is.

On the other hand, a sample using oxygen plasma annealing as another method of supplementing oxygen has a dielectric constant of about 60 and a leak current density of 1 × 10 ⁻⁸ A / cm when the electric field strength is 1 MV / cm. ² , the leakage current density is 1 × 10 ⁻⁶ A / cm ² when the electric field intensity is −1 MV / cm.
As described above, when the oxygen plasma annealing is used as a method of supplementing oxygen, the leak current is smaller than the annealing in the oxygen atmosphere, but it is still not sufficiently small.

The present invention has been made in view of such a problem, and an object of the present invention is to make it possible to sufficiently reduce a leak current when an electrode made of a noble metal is used. A leak current of a capacitor using a noble metal electrode can be sufficiently reduced.

[0017]

In order to achieve the above-mentioned object, the present invention provides a method of forming a conductive film constituting an electrode or a wiring, in particular, when crystallizing ruthenium, the surface shape of crystal grains is stepped. And

Specifically, the first semiconductor device according to the present invention includes an electrode or a wiring containing ruthenium formed on a substrate, and the crystal grains of ruthenium have a stepped surface shape.

According to the first semiconductor device, since the surface shape of the crystal grains (grains) of ruthenium constituting the electrodes or wirings is stepped, the surface area of each crystal grain is increased, and the apparent relative dielectric constant is reduced. It is larger than without the step-like surface shape. In addition, as will be described later, the angle formed between the crystal surface and the connection surface between adjacent crystal grains is an obtuse angle, so that the concentration of an electric field at the interface between the crystal grains is less likely to occur, thereby reducing the leakage current.

A second semiconductor device according to the present invention includes a lower electrode formed on a substrate, a capacitance insulating film formed on the lower electrode, and an upper electrode formed on the capacitance insulating film, The lower electrode includes crystal grains, and the crystal grains have a stepped surface shape.

According to the second semiconductor device, since the surface shape of the crystal grains of the electrode member constituting the lower electrode is step-like, the surface area of each crystal grain increases, and the crystal member does not have a step-like surface shape. The apparent relative permittivity is larger than that of. In addition, since the angle between the connecting surface of the crystal grains adjacent to each other and the crystal surface is an obtuse angle, the concentration of the electric field at the interface between the crystal grains is less likely to occur, so that the leak current is reduced.

In the second semiconductor device, the lower electrode preferably contains ruthenium. This makes it easier to obtain a step-like shape on the surface of the crystal grain.

According to a first method of manufacturing a semiconductor device according to the present invention, there is provided a conductive film forming step of forming a conductive film containing ruthenium on a substrate, and patterning the conductive film into a predetermined shape to form an electrode formed of the conductive film. Alternatively, there is provided an electrode wiring forming step of forming wiring, and an annealing step of performing annealing in a non-oxidizing atmosphere to make the surface shape of ruthenium crystal grains constituting the conductor film step-like.

According to the first method for manufacturing a semiconductor device, the surface shape of the crystal grains of ruthenium constituting the conductor film is made stepwise by annealing in a non-oxidizing atmosphere. A semiconductor device can be realized.

In the first method for manufacturing a semiconductor device, the non-oxidizing atmosphere preferably contains hydrogen. In this way, a fine step-like shape can be reliably obtained on the surface of the ruthenium crystal grain.

According to a second method of manufacturing a semiconductor device according to the present invention, there is provided a conductive film forming step of forming a conductive film containing ruthenium on a substrate, and patterning the conductive film into a predetermined shape, thereby forming a lower portion of the conductive film. A lower electrode forming step of forming an electrode, an annealing step of performing a step shape of the surface of ruthenium crystal grains constituting the conductor film by performing annealing in a non-oxidizing atmosphere, and a capacitive insulating film on the lower electrode Forming a capacitive insulating film.

According to the second method of manufacturing a semiconductor device, the surface shape of the ruthenium crystal grains constituting the lower electrode is made stepwise by annealing in a non-oxidizing atmosphere. A semiconductor device can be realized.

In the second method for manufacturing a semiconductor device, the non-oxidizing atmosphere preferably contains hydrogen.

In the second method for manufacturing a semiconductor device, the capacitance insulating film is preferably made of tantalum pentoxide, strontium titanate, barium titanate or barium strontium titanate. In this case, since the capacitance insulating film is made of a high dielectric material, a desired capacitance value (stored charge amount) can be obtained even if the semiconductor device including the capacitor is further downsized.
Can be secured.

In the second method for fabricating a semiconductor device, the annealing step is preferably performed before the capacitive insulating film forming step. With this configuration, the conductor film can be annealed in the film forming apparatus for forming the capacitor insulating film, and the process is simplified.

In the second method for manufacturing a semiconductor device, the annealing step is preferably performed after the lower electrode forming step. With this configuration, the patterning of the lower electrode is performed before the crystal grains of the conductive film grow due to the annealing and the processing becomes difficult, so that the patterning processing is facilitated.

In the second method for manufacturing a semiconductor device, the conductor film forming step preferably includes a step of forming the conductor film into a bottomed cylindrical shape. In this case, the surface area of the lower electrode increases, so that the capacitance value of the capacitor surely increases.

[0033]

(First Embodiment) A first embodiment of the present invention.
An embodiment will be described with reference to the drawings.

FIG. 1 shows a sectional structure of a capacitor which is a semiconductor device according to the first embodiment of the present invention. FIG.
As shown in FIG. 1, a thermal oxide film 12 made of silicon oxide, a lower electrode 13 made of ruthenium (Ru), and a capacitive insulating film 1 made of Ta ₂ O ₅ are formed on a substrate 11 made of silicon.
4. An upper electrode 15 made of Ru is sequentially formed.

Hereinafter, a method of manufacturing the capacitor having the above-described structure will be described.

First, heat treatment is performed on the substrate 11 to form a thermal oxide film 12 on the substrate 11. Next, a film thickness of about 50 n is formed on the thermal oxide film 12 by using a sputtering method.
m lower electrodes 13 are formed. Subsequently, the temperature was about 800
The lower electrode 13 is annealed for about 2 minutes in a mixed gas of argon (Ar) and hydrogen (H ₂ ) which is a non-oxidizing atmosphere at a temperature of ° C. Note that since a small amount of oxygen is contained in an argon gas used in a normal semiconductor process, it is preferable to use a high-purity argon gas.

Next, a capacitor insulating film 14 having a thickness of about 17 nm is formed on the lower electrode 13 by using the CVD method. At this time, in order to compensate for the lack of oxygen in the capacitance insulating film 14,
The lower electrode 13 is irradiated with ultraviolet ozone (UV-O ₃ treatment).

Next, the capacitor insulating film 1 is formed by sputtering.
The upper electrode 15 is selectively formed on the upper electrode 4.

The results of evaluating the electrical characteristics of the capacitor thus obtained are shown.

When the lower electrode 13 is annealed in a mixed gas of argon and hydrogen, the capacitance insulating film 1
If the relative dielectric constant of No. 4 is 35 and the upper electrode is positively biased and the potential is positive, the leakage current density when the electric field intensity is 1 MV / cm is 6.7 × 10 ⁻⁹ A / cm ² . is there. For comparison, when annealing was performed on the lower electrode 13 in an argon atmosphere, the relative dielectric constant of the capacitor insulating film 14 was 30, and the leak current density when the electric field strength was 1 MV / cm was 1.5 × 10 5 ^-8 A / cm ² .

As described above, when the lower electrode 13 is annealed with a mixed gas of argon and hydrogen, the relative dielectric constant of the capacitance insulating film 14 is higher than that of the comparative capacitor annealed only with the argon gas. Also increases. The capacitor according to the present embodiment has a smaller leak current density than the capacitor for comparison.

Next, annealing is performed for 60 seconds in a nitrogen atmosphere at a temperature of about 750.degree.
4 is crystallized. The relative dielectric constant of the capacitance insulating film 14 after crystallization is 70, and the leak current density when the electric field strength is 1 MV / cm is 1.8 × 10 ⁻⁸ A / cm ² . Incidentally, the relative dielectric constant of the capacitance insulating film 14 in the comparative capacitor is 60, and the leak current density when the electric field strength is 1 MV / cm is 2 × 10 ⁻⁸ A / cm ² . As described above, even when the capacitor insulating film 14 is crystallized, the relative dielectric constant of the capacitor insulating film 14 according to the present embodiment is higher than that of the comparative capacitor, and the leak current density is higher than that of the present embodiment. Is smaller than the capacitor for comparison.

Although all the measurements of the leak current density up to this point are performed at room temperature, when the capacitor according to the present embodiment is formed as a semiconductor device, it is necessary to consider the operation at a high temperature of about 100 ° C. is there. Normally, the leakage current of the capacitor increases as the temperature of the device or the ambient temperature increases.

Therefore, the leakage current characteristics of the capacitor according to the present embodiment were measured at a temperature of 125 ° C.

The capacitor for comparison subjected to annealing only with argon has a leak current density of 1 × 10 ⁻⁶ A / cm ² when the electric field intensity is 1 MV / cm, whereas the capacitor according to the present embodiment has The capacitor has an electric field strength of 1 MV / cm
In this case, the leakage current density is 2 × 10 ⁻⁷ A / cm ² , and a good result having a smaller leakage current value than the capacitor for comparison can be obtained.

The cause of the difference in the leak current density depending on the annealing conditions of the lower electrode 13 is that when annealing is performed with a mixed gas of argon and hydrogen, the surface shape of the ruthenium crystal grains becomes step-like.

FIG. 2A shows the lower electrode 1 according to this embodiment.
FIG. 3 is a schematic enlarged view showing crystal grains having a step-like surface shape in FIG. Here, reference numerals 1 to 5 represent respective crystal grains. The size of each crystal grain 1 to 5 is 50 nm to 100 n by annealing at a temperature of about 800 ° C.
m, which is 2 times smaller than the grain size before annealing.
About 5 times larger.

FIG. 2B shows a partial cross-sectional structure taken along the line IIb-IIb in FIG. 2A. As shown in FIG. 2B, the space between the crystal grains 1 and 2 has a stepped shape. In this case, both the upper surface of the crystal grain 1 and the upper surface of the crystal grain 2 have a (0001) plane orientation.
1) The planes are connected by a step-like slope which is an interface between crystal grains.

FIG. 2C shows an enlarged cross-sectional structure of the step-like one-stepped portion 10 shown in FIG. 2B. The inclined surface itself of the one-stepped portion 10 is made finer by a plurality of atomic steps. It has a shape.

As described above, since the surface of the lower electrode 13 has a double step shape in which the inclined surface of the step portion 10 has a finer step shape, the surface area of the lower electrode increases. In addition, the apparent relative dielectric constant becomes larger than that in the case where the surface of each crystal grain is not stepped. Further, as shown in FIG. 2B, the angle formed between the connection surface connecting crystal grains 1 and 2 and the upper surfaces of crystal grains 1 and 2 is an obtuse angle.
The number of interfaces that intersect at an acute angle is reduced. As a result, the concentration of the electric field hardly occurs at the interface between the crystal grains, so that the leak current is reduced.

FIGS. 3A and 3B show a lower electrode of a comparative capacitor, in which FIG. 3A shows the surface of ruthenium crystal grains, and FIG. 3B shows IIIb-IIIb of FIG. The partial cross-sectional configuration along the line is shown. Although the size of the crystal grains shown in FIG. 3A is substantially equal to that of the case shown in FIG. 2A, the surface shape of each crystal grain is not a step but a smooth one. This is because the surface of a crystal grain is oxidized to ruthenium oxide by a slight amount of oxygen contained in a normal argon gas, and a part of the surface is volatilized.
1) Because it stops at the surface. As a result, FIG.
As shown in (b), for example, a step portion in which a connection surface between adjacent crystal grains is substantially perpendicular to each crystal grain, such as a crystal grain 6 and a crystal grain 7, is formed. For this reason, an electric field is concentrated on the right-angled step portion, which causes an increase in leakage current.

As described above, if the conductor film forming the lower electrode 13 of the capacitor is formed so that the surface shape of the crystal grains is stepped, Ta ₂ O ₅ which is a high dielectric substance is formed.
The leakage current of a capacitor using such a metal oxide as the capacitor insulating film 14 can be reduced.

The functional material film made of a high dielectric material is not limited to the Ta ₂ O ₅ film, but may be an STO film or a BST film.

Although a mixed gas of argon and hydrogen is used as an atmosphere for annealing the lower electrode 13, the present invention is not limited to this, and a non-oxidizing gas may be used.

Further, the conductive film having a stepped crystal grain surface is
The present invention is not limited to the electrode of the capacitor, and may be used for other electrodes, for example, a contact, a via, or a pad electrode. Further, it may be used for a wiring to which a relatively high electric field is applied.

(Second Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

FIGS. 4A and 4B show a cross-sectional structure in the order of steps of a method for manufacturing a DRAM device according to the second embodiment.

First, as shown in FIG. 4A, an element isolation layer 22 made of silicon oxide is selectively formed on a substrate 21 made of p-type silicon. Subsequently, a gate insulating film 23 and a gate electrode 24 are formed in a device formation region surrounded by a device isolation layer 22 on the substrate 21, and thereafter, an n ⁺ -type first is formed by ion implantation using the gate electrode 24 as a mask. a second diffusion layer 26 of the diffusion layer 25 and n ⁺ -type self-aligned manner.

Subsequently, an interlayer insulating film 27 made of silicon oxide is formed on the entire surface including the gate electrode 24 on the substrate 21.
Is deposited, and the second diffusion layer 26 in the interlayer insulating film 27 is formed.
A contact 28 made of polysilicon in contact with the second diffusion layer 26 is formed in the upper region of FIG. Next, the gate electrode 24 on the interlayer insulating film 27 is formed by sputtering.
A lower electrode 29 made of ruthenium which is in contact with the contact 28 is selectively formed in a region above the lower electrode 29. Subsequently, the temperature of the substrate 21 on which the lower electrode 29 is formed is about 80 ° C.
Anneal for about 2 minutes in a mixed gas of hydrogen and argon at 0 ° C.

Next, as shown in FIG. 4B, a capacitance insulating film 30 made of Ta ₂ O ₅ is deposited on the interlayer insulating film 27 over the entire surface including the lower electrode 29 by using the CVD method.
Subsequently, oxygen is supplemented to the capacitive insulating film 30 by UV-O ₃ treatment, and annealing is performed at a temperature of about 750 ° C. for about 1 minute to remove Ta ₂ O ₅ constituting the capacitive insulating film. Crystallizes. Subsequently, by the CVD method,
An upper electrode 31 made of ruthenium is deposited on the crystallized capacitor insulating film 30 and subsequently annealed at a temperature of about 600 ° C. for about 1 minute to recover the processing damage to the entire capacitor section. .

In this embodiment, as shown in FIG. 4A, after the lower electrode 29 is patterned,
Annealing for growing crystal grains and forming a step-like surface shape is performed. This is because, during patterning by etching or the like, the smaller the grain size of the crystal grains, the easier the processing. In addition, after patterning, film-like ruthenium becomes an isolated pattern, so that stress generated in annealing in a direction parallel to the substrate surface can be reduced. Also,
Since the crystal grains grow in the ruthenium in the isolated pattern, the number of crystal grains is reduced.

In the present embodiment, a single layer of ruthenium is used for the lower electrode 29 of the capacitor section, but a laminated structure with another conductor film may be used.

Although Ta ₂ O ₅ is used for the capacitance insulating film 30, the present invention is not limited to this, and STO or BST may be used.

Although a mixed gas of argon and hydrogen is used as an atmosphere for annealing the lower electrode 29, the present invention is not limited to this, and a non-oxidizing gas may be used. The annealing temperature is 800 ° C., but may be any temperature at which the growth of ruthenium crystal grains occurs.

By utilizing this, for example, in the film forming apparatus for forming the capacitance insulating film 30, before forming the capacitance insulating film 30, the lower electrode 29 is annealed in a non-oxidizing gas atmosphere. You may do it. This way,
Since the lower electrode 29 can be annealed without using an annealing furnace, the manufacturing process can be simplified.

If the annealing temperature is too high, the implantation profile of the first diffusion layer 25 and the second diffusion layer 26 in the transistor portion is broken. Also, the gate electrode 2
In the case where a silicide film is formed on the contact 4 or the contact 28, a defect due to the silicide film may occur.

(Third Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings.

FIGS. 5 (a) to 5 (c) and 6 (a),
(B) shows a sectional configuration in a process order of the method for manufacturing the DRAM device according to the third embodiment.

First, as shown in FIG. 5A, an element isolation layer 42 made of silicon oxide is selectively formed on a substrate 41 made of p-type silicon. Subsequently, a gate insulating film 43 and a gate electrode 44 are formed in a device formation region surrounded by a device isolation layer 42 on the substrate 41, and thereafter, the n ⁺ -type first is formed by ion implantation using the gate electrode 44 as a mask. a second diffusion layer 46 of the diffusion layer 45 and n ⁺ -type self-aligned manner.

Subsequently, an interlayer insulating film 47 made of silicon oxide is formed on the entire surface including the gate electrode 44 on the substrate 41.
Is deposited, and a second diffusion layer 46 in the interlayer insulating film 47 is formed.
A contact 48 made of polysilicon contacting the second diffusion layer 46 is formed in the upper region of FIG. Thereafter, a first insulating film 49 made of silicon oxide and a second insulating film 50 made of silicon nitride, which determine the shape of the lower electrode, are sequentially deposited on the interlayer insulating film 47.

Next, as shown in FIG. 5B, the contacts 48 in the first insulating film 49 and the second insulating film 50 are formed.
By etching the upper region of
An opening 49a for exposing the contact 48 and the peripheral portion of the contact 48 in the interlayer insulating film 47 is formed.

Next, as shown in FIG. 5C, a lower electrode forming film 51A made of ruthenium is formed on the second insulating film 50 over the entire surface including the bottom surface and the wall surface of the opening 49a by sputtering. After that, a protective layer 52 made of silicon oxide is formed on the entire surface of the lower electrode forming film 51A by using a CVD method or the like. Subsequently, a resist film 53 is applied on the protective layer 52 so as to fill the opening 49a.

Next, as shown in FIG.
The resist film 53, the protective layer 52, and the lower electrode forming film 51A except 9a are etched back by anisotropic dry etching to expose the second insulating film 50. Thereby, the lower electrode 51B is formed on the bottom surface and the wall surface of the opening 49a from the lower electrode forming film 51A. After that, the protective layer 52 remaining in the opening 49a is removed with a chemical solution containing hydrofluoric acid (HF). Subsequently, annealing is performed on the substrate 41 on which the lower electrode 51B is formed in a mixed gas of hydrogen and argon at a temperature of about 800 ° C. for about 2 minutes.

As a result, the lower electrode 51B is
Ruthenium crystal grains as shown in FIG. Also in the present embodiment, annealing of the lower electrode 51B is performed after patterning of the lower electrode 51B, thereby facilitating the processing of the lower electrode forming film 51A. After patterning, the film-like ruthenium is processed into an isolated pattern, so that stress generated in the direction parallel to the substrate surface during annealing can be reduced. In addition, since crystal grains grow in ruthenium in an isolated pattern, the number of crystal grains decreases.

Next, as shown in FIG.
Second insulating film 5 made of hot phosphoric acid heated to about 50 ° C.
0 is removed, and then the first insulating film 49 is removed with hydrofluoric acid or the like.
Is removed to obtain a bottom electrode 51B having a bottomed cylindrical shape.

In this embodiment, the lower electrode forming film 51 is etched back using the resist film 53.
Although the area excluding the opening 49a in A is removed,
As another method, for example, a chemical mechanical polishing method may be used.

Even when using the chemical mechanical polishing method, it is desirable to form the protective layer 52 on the upper surface of the lower electrode forming film 51A. By doing so, the opening 4
The slurry deposited on 9a or the like can be easily removed by lifting off the protective layer 52 by washing after polishing.

The annealing for the lower electrode 51B may be performed after the first insulating film 49 and the second insulating film 50 are removed.

In each embodiment of the present invention, the annealing temperature of the electrode made of ruthenium is 450 ° C. to 90 ° C.
It is sufficient that the temperature is 0 ° C. In addition, the ratio of argon and hydrogen constituting the non-oxidizing atmosphere gas for annealing may be such that hydrogen can react with a trace amount of oxygen contained in the argon gas, and is usually 1% or more.

[0080]

According to the semiconductor device and the method of manufacturing the same according to the present invention, since the surface shape of the crystal grains of the members constituting the electrodes or wirings is stepped, the surface area of each crystal grain is increased. Is larger than the case without the surface shape. In addition, since the angle between the connecting surface of the crystal grains adjacent to each other and the crystal surface is an obtuse angle, the concentration of the electric field at the interface between the crystal grains is less likely to occur, so that the leak current is reduced. Accordingly, when the electrode of the present invention is used for the electrode of the capacitor in which the functional material film having a high dielectric constant is used as the capacitor insulating film, a semiconductor device with less leakage current can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are enlarged views showing the surface shapes of ruthenium crystal grains constituting an electrode of the semiconductor device according to the first embodiment of the present invention, and FIG. It is a figure, (b) is a sectional view taken on the line IIb-IIb of (a), and (c) is a sectional view in which a step portion in (b) is enlarged.

FIGS. 3A and 3B are enlarged views of the surface shape of ruthenium crystal grains constituting an electrode of a semiconductor device for comparison, FIG. 3A is a schematic plan view, and FIG. Is (a)
FIG. 3 is a sectional view taken along line IIIb-IIIb.

FIGS. 4A and 4B are sectional views in the order of steps showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 5A to 5C are sectional views in the order of steps showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 6A and 6B are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

 1-5 crystal grain 10 stepped portion 11 substrate 12 thermal oxide film 13 lower electrode 14 capacitance insulating film 15 upper electrode 21 substrate 22 element isolation layer 23 gate insulating film 24 gate electrode 25 first diffusion layer 26 second diffusion layer 27 Interlayer insulating film 28 Contact 29 Lower electrode 30 Capacitive insulating film 31 Upper electrode 41 Substrate 42 Element isolation layer 43 Gate insulating film 44 Gate electrode 45 First diffusion layer 46 Second diffusion layer 47 Interlayer insulation film 48 Contact 49 First Insulating film 49a Opening 50 Second insulating film 51A Lower electrode forming film 51B Lower electrode 52 Protective layer 53 Resist film

Claims (11)

[Claims] 1. A semiconductor device comprising an electrode or a wiring containing ruthenium formed on a substrate, wherein the ruthenium crystal grains have a stepped surface shape. 2. A semiconductor device comprising: a lower electrode formed on a substrate; a capacitor insulating film formed on the lower electrode; and an upper electrode formed on the capacitor insulating film. A semiconductor device, wherein the crystal grains have a stepped surface shape. 3. The semiconductor device according to claim 2, wherein said lower electrode contains ruthenium. 4. A conductive film forming step of forming a conductive film containing ruthenium on a substrate, and patterning the conductive film into a predetermined shape,
An electrode wiring forming step of forming an electrode or a wiring made of the conductive film; and an annealing step of performing annealing in a non-oxidizing atmosphere to make the surface shape of ruthenium crystal grains constituting the conductive film a step shape. A method for manufacturing a semiconductor device, comprising: 5. The method according to claim 4, wherein the non-oxidizing atmosphere contains hydrogen. 6. A conductive film forming step of forming a conductive film containing ruthenium on a substrate, and by patterning the conductive film into a predetermined shape,
A lower electrode forming step of forming a lower electrode made of the conductive film; and an annealing step of performing annealing in a non-oxidizing atmosphere to make a surface shape of ruthenium crystal grains constituting the conductive film a step-like shape. Forming a capacitive insulating film on the lower electrode. 7. The method according to claim 6, wherein the non-oxidizing atmosphere contains hydrogen. 8. The method according to claim 6, wherein the capacitance insulating film is made of tantalum pentoxide, strontium titanate, barium titanate, or barium strontium titanate. 9. The method according to claim 6, wherein the annealing step is performed before the capacitive insulating film forming step.
13. The method of manufacturing a semiconductor device according to claim 1. 10. The method according to claim 6, wherein the annealing step is performed after the lower electrode forming step.
13. The method of manufacturing a semiconductor device according to claim 1. 11. The manufacturing of a semiconductor device according to claim 6, wherein said conductor film forming step includes a step of forming said conductor film into a bottomed cylindrical shape. Method.