JP2001035706A - Varistor and manufacture thereof - Google Patents
Varistor and manufacture thereofInfo
- Publication number
- JP2001035706A JP2001035706A JP11204161A JP20416199A JP2001035706A JP 2001035706 A JP2001035706 A JP 2001035706A JP 11204161 A JP11204161 A JP 11204161A JP 20416199 A JP20416199 A JP 20416199A JP 2001035706 A JP2001035706 A JP 2001035706A
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- varistor element
- compound layer
- external electrodes
- sheath
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Thermistors And Varistors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はバリスタとその製造
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a varistor and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来よりセラミック電子部品は、回路基
板実装時の半田付け性を確保するために電極面にNiメ
ッキ及び半田メッキを施している。しかしながら、Zn
Oを主成分とするバリスタ素子は、セラミックスが半導
体であるため電解メッキを行う際に素子表面にもメッキ
膜が形成される。これを防ぐためにバリスタ素子の表面
にSi化合物等の高抵抗層を形成する方法が提案されて
いる。2. Description of the Related Art Conventionally, ceramic electronic parts have been subjected to Ni plating and solder plating on the electrode surface in order to secure solderability at the time of mounting on a circuit board. However, Zn
In a varistor element containing O as a main component, a plating film is also formed on the element surface when performing electrolytic plating because ceramic is a semiconductor. In order to prevent this, a method of forming a high-resistance layer such as a Si compound on the surface of a varistor element has been proposed.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、ZnO
を主成分とするバリスタ素子は僅かでも表面が露出して
いるとその部分にメッキ膜が形成される。従ってバリス
タ素子の表面の外部電極以外は完全に高抵抗層を成膜す
る必要がある。また膜厚が厚くなりすぎると、バリスタ
素子との膨脹率の差から剥がれ易くなるという問題があ
った。SUMMARY OF THE INVENTION However, ZnO
If the surface of a varistor element mainly composed of is slightly exposed, a plating film is formed on the exposed portion. Therefore, it is necessary to completely form the high-resistance layer except for the external electrodes on the surface of the varistor element. Further, when the film thickness is too large, there is a problem that the film is easily peeled off due to a difference in expansion coefficient from the varistor element.
【0004】本発明はバリスタ素子の表面にメッキが付
着しない高抵抗層を形成したバリスタとその製造方法を
提供することを目的としている。An object of the present invention is to provide a varistor in which a high resistance layer to which plating does not adhere is formed on the surface of a varistor element, and a method of manufacturing the varistor.
【0005】[0005]
【課題を解決するための手段】この目的を達成するため
に、本発明はバリスタ素子上の全面に化合物層の厚み
(T)が0.1<T<20μmのZn−Si−O系また
はBi−Si−O系の高抵抗を有する化合物層の均質な
膜を設けることによって所期の目的を達成するものであ
る。In order to achieve this object, the present invention provides a Zn-Si-O-based or Bi-based material having a compound layer thickness (T) of 0.1 <T <20 μm over the entire surface of a varistor element. The objective is achieved by providing a uniform film of a compound layer having a high resistance of -Si-O system.
【0006】[0006]
【発明の実施の形態】本発明の請求項1に記載の発明
は、ZnOを主成分とするバリスタ素子と、前記バリス
タ素子の表面の一部に形成した一対の外部電極と、前記
外部電極の形成部を除く全面に厚さ(T)が0.1<T
<20μmの高抵抗体のZn−Si−O系またはBi−
Si−O系からなる化合物層を形成したバリスタであ
り、バリスタ素子の外部電極を除く全表面に高抵抗を有
するZn−Si−O系またはBi−Si−O系の均質な
厚さの化合物層を形成することで、電解メッキの際にバ
リスタ素子の表面にメッキされるのを防止することが可
能となる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a varistor element containing ZnO as a main component, a pair of external electrodes formed on a part of the surface of the varistor element, The thickness (T) is 0.1 <T on the entire surface excluding the formation portion
<20 μm high-resistance Zn—Si—O-based or Bi—
A varistor having a Si-O-based compound layer formed thereon, the Zn-Si-O-based or Bi-Si-O-based compound layer having a high resistance on the entire surface of the varistor element excluding the external electrode, and having a uniform thickness. Is formed, it is possible to prevent plating on the surface of the varistor element during electrolytic plating.
【0007】本発明の請求項2に記載の発明は、バリス
タ素子が半導体セラミックス層と内部電極とを交互に複
数層積層した積層体である請求項1に記載のバリスタで
あり、これはバリスタ素子の表面に高抵抗を有する均質
の厚さの化合物層を形成することで、電解メッキの際に
バリスタ素子の表面にメッキされるのを防止することが
できるものである。According to a second aspect of the present invention, there is provided the varistor according to the first aspect, wherein the varistor element is a laminate in which a plurality of semiconductor ceramic layers and internal electrodes are alternately laminated. By forming a compound layer having a high resistance and a uniform thickness on the surface of the varistor element, it is possible to prevent the surface of the varistor element from being plated during electrolytic plating.
【0008】本発明の請求項3に記載の発明は、バリス
タ素子とSiO2粉末をサヤに収納し、前記サヤを可動
させながら所定温度で加熱処理を行い、請求項1に記載
の化合物層を形成するバリスタの製造方法であり、これ
はバリスタ素子の外部電極を除く全面に高抵抗を有する
Zn−Si−O系またはBi−Si−O系の均一に膜厚
の化合物層を形成することができる。According to a third aspect of the present invention, the varistor element and the SiO 2 powder are stored in a sheath, and a heat treatment is performed at a predetermined temperature while the sheath is being moved. This is a method for manufacturing a varistor to be formed, which is capable of forming a uniform-thickness compound layer of a Zn-Si-O-based or Bi-Si-O-based material having high resistance over the entire surface except for the external electrodes of the varistor element. it can.
【0009】本発明の請求項4に記載の発明は、サヤの
回転または揺動させる請求項3に記載のバリスタの製造
方法であり、これはバリスタ素子の外部電極を除く全面
に高抵抗を有するZn−Si−O系またはBi−Si−
O系の均一に膜厚の化合物層を形成することができるも
のである。According to a fourth aspect of the present invention, there is provided a method for manufacturing a varistor according to the third aspect, wherein the sheath is rotated or swung. The varistor has a high resistance over the entire surface except for the external electrodes of the varistor element. Zn-Si-O-based or Bi-Si-
An O-based compound layer having a uniform thickness can be formed.
【0010】本発明の請求項5に記載の発明は、サヤの
内面が多角形である請求項3または請求項4に記載のバ
リスタの製造方法であり、これは、バリスタ素子の外部
電極を除く全面に高抵抗を有するZn−Si−O系また
はBi−Si−O系の均一な膜厚の化合物層を形成する
ことができるものである。According to a fifth aspect of the present invention, there is provided the method for manufacturing a varistor according to the third or fourth aspect, wherein the inner surface of the sheath is polygonal, excluding the external electrodes of the varistor element. A compound layer of a uniform thickness of a Zn-Si-O-based or Bi-Si-O-based material having high resistance can be formed on the entire surface.
【0011】本発明の請求項6に記載の発明は、サヤの
内面に突起を形成した請求項3または請求項4に記載の
バリスタの製造方法であり、これは、バリスタ素子の外
部電極を除く全面に高抵抗を有するZn−Si−O系ま
たはBi−Si−O系の均一な膜厚の化合物層を形成す
ることができるものである。According to a sixth aspect of the present invention, there is provided a method for manufacturing a varistor according to the third or fourth aspect, wherein a projection is formed on an inner surface of the sheath, except for an external electrode of the varistor element. A compound layer of a uniform thickness of a Zn-Si-O-based or Bi-Si-O-based material having high resistance can be formed on the entire surface.
【0012】(実施の形態1)図1は本発明の積層体タ
イプのバリスタ素子11の断面図で、図において1はセ
ラミックス層、2は内部電極、3は外部電極、4はZn
−Si−O系またはBi−Si−O系の高抵抗を有する
化合物層、5はNi膜、6は半田膜を示す。図2,図
3,図4はサヤの断面図で、図において7,8,9はサ
ヤ、10はSiO 2粉末、11はバリスタ素子を示す。(Embodiment 1) FIG.
1 is a sectional view of a varistor element 11 of FIG.
Lamix layer, 2 is an internal electrode, 3 is an external electrode, 4 is Zn
-Si-O-based or Bi-Si-O-based high resistance
The compound layer, 5 indicates a Ni film, and 6 indicates a solder film. Figure 2, Figure
3 and 4 are cross-sectional views of the sheath.
Ya, 10 is SiO TwoPowder, 11 indicates a varistor element.
【0013】まず、主成分のZnOと、副成分のBi2
O3を1.0mol%、Co2O3を0.5mol%、M
nO2を0.5mol%、Sb2O3を0.5mol%、
Al2O 3を0.005mol%秤量し、これに有機溶剤
の酢酸ブチル、バインダーのポリビニルブチラールと可
塑剤を加えて24時間混合しスラリーを作製した。First, the main component ZnO and the sub-component BiTwo
OThree1.0 mol%, CoTwoOThree0.5 mol%, M
nOTwo0.5 mol%, SbTwoOThreeIs 0.5 mol%,
AlTwoO ThreeWeighed 0.005 mol%, and added
Butyl acetate and binder polyvinyl butyral
A plasticizer was added and mixed for 24 hours to prepare a slurry.
【0014】次に、スラリーを公知のドクターブレード
法を用いキャリアフィルム(図示せず)上に塗工し厚さ
100μmのセラミックス層1用のグリーンシート(図
示せず)を成形した。Next, the slurry was applied on a carrier film (not shown) using a known doctor blade method to form a green sheet (not shown) for the ceramic layer 1 having a thickness of 100 μm.
【0015】次いで、グリーンシート面にAg−Pdを
主成分とする電極ペーストを印刷して内部電極2を形成
する。Next, an internal electrode 2 is formed by printing an electrode paste containing Ag-Pd as a main component on the green sheet surface.
【0016】その後、内部電極2を形成したグリーンシ
ートを複数枚積層し積層体グリーンブロック(図示せ
ず)を作製した。グリーンシートの積層は、形成した内
部電極2の長手方向に一層ごと交互に所定寸法ずらして
行った。Thereafter, a plurality of green sheets on which the internal electrodes 2 were formed were laminated to form a laminated green block (not shown). The stacking of the green sheets was carried out alternately by a predetermined size in the longitudinal direction of the formed internal electrode 2 for each layer.
【0017】次に、積層体グリーンブロックを所定形状
に切断しグリーンチップ(図示せず)を得た。グリーン
チップはその長手方向の両端面には内部電極2の一方の
端部がグリーンシートを挟んで一層おき交互に相対向す
る異なる端面に露出した構造となっている。Next, the green block was cut into a predetermined shape to obtain a green chip (not shown). The green chip has a structure in which one end portion of the internal electrode 2 is disposed on both end surfaces in the longitudinal direction with a green sheet interposed therebetween and is exposed to different end surfaces which are alternately opposed to each other.
【0018】次いで、グリーンチップの両端面にAg−
Pdを主成分とする電極ペーストを内部電極2と電気的
に接続するように塗布した後、900〜960℃で1時
間焼成し外部電極3を形成したバリスタ素子11を得
た。Next, Ag-sides are applied to both end faces of the green chip.
An electrode paste containing Pd as a main component was applied so as to be electrically connected to the internal electrodes 2, and then baked at 900 to 960 ° C. for 1 hour to obtain a varistor element 11 in which the external electrodes 3 were formed.
【0019】その後、バリスタ素子11をSiO2粉末
10と共に、図2に示す内面が多角形の筒状のサヤ7に
入れ、サヤ7を回転速度0.3rpmで回転させながら
860℃で5時間熱処理を行いバリスタ素子11の外部
電極3を除く全面に高抵抗を有するZn−Si−O系、
Bi−Si−O系の均一に膜厚の化合物層4を形成し
た。Zn−Si−O系、Bi−Si−O系の高抵抗の化
合物層4はSiO2粉末がバリスタ素子11の表面のZ
nO,Bi2O3と860℃の温度で反応し形成すること
ができる。Thereafter, the varistor element 11 is put together with the SiO 2 powder 10 in a cylindrical sheath 7 shown in FIG. 2 and heat treated at 860 ° C. for 5 hours while rotating the sheath 7 at a rotation speed of 0.3 rpm. And a Zn-Si-O-based material having high resistance over the entire surface of the varistor element 11 except for the external electrodes 3.
A Bi-Si-O-based compound layer 4 having a uniform thickness was formed. The Zn—Si—O-based and Bi—Si—O-based high-resistance compound layer 4 is made of SiO 2 powder having a Z value on the surface of the varistor element 11.
It can be formed by reacting with nO, Bi 2 O 3 at a temperature of 860 ° C.
【0020】次に、バリスタ素子11とSiO2粉末1
0を取出し、フルイを用いてSiO2粉末10とバリス
タ素子11を分離した後、バリスタ素子11を純水で洗
浄し外部電極3の表面に付着したSiO2粉末10を取
り除いた。またSiO2粉末10の処理で化合物層4の
膜が不十分に形成されたものを目視検査で分類を行っ
た。Next, the varistor element 11 and the SiO 2 powder 1
Taken out 0, after separation of the SiO 2 powder 10 and the varistor element 11 by using a sieve to remove SiO 2 powder 10 adhering to the surface of the external electrodes 3 and washed with varistor element 11 with pure water. Further, those in which the film of the compound layer 4 was insufficiently formed by the treatment of the SiO 2 powder 10 were classified by visual inspection.
【0021】次いで、外部電極3上に電解メッキ法を用
いNi膜5、更にその表面に半田膜6を形成し積層体タ
イプのバリスタを完成させた。得られたバリスタについ
て、外部電極3以外の表面のメッキ流れを検査しその結
果を(表1)に示した。Next, a Ni film 5 was formed on the external electrodes 3 by electrolytic plating, and a solder film 6 was further formed on the surface of the Ni film 5 to complete a laminated varistor. With respect to the obtained varistor, plating flow on the surface other than the external electrode 3 was inspected, and the results are shown in (Table 1).
【0022】[0022]
【表1】 [Table 1]
【0023】(表1)から明らかなように、本発明の製
造方法で化合物層4が完全にバリスタ素子11の表面を
被覆したものは、化合物層4が高抵抗体であるためメッ
キ流れが発生していないのに対し、化合物層4が不完全
なものは部分的にメッキ流れが発生している。またバリ
スタ素子11の焼成後にSiO2粉末10を用いた熱処
理を行わず電解メッキを行ったものはバリスタ素子11
の全面にメッキ流れが発生していることが分かる。これ
はバリスタ素子11自体が半導体であるため、バリスタ
素子11のセラミック層1の表面において電子の授受が
行われ、その結果バリスタ素子11の表面抵抗値が低い
部分にメッキ膜が形成されるものと考えられる。これは
化合物層4が形成不十分とメッキ流れが発生している箇
所が一致していることからも明らかである。このことか
ら、バリスタ素子11のメッキ流れは外部電極3部分か
ら成長してくるのではなく、抵抗値の低い部分にメッキ
膜がされるものと思われる。As is clear from Table 1, in the case where the compound layer 4 completely covers the surface of the varistor element 11 in the manufacturing method of the present invention, plating flow occurs because the compound layer 4 is a high-resistance body. On the other hand, when the compound layer 4 is incomplete, plating flow is partially generated. In addition, after the varistor element 11 was fired, the heat treatment using the SiO 2 powder 10 was not performed and the electrolytic plating was performed.
It can be seen that plating flow has occurred over the entire surface of the substrate. This is because, since the varistor element 11 itself is a semiconductor, electrons are exchanged on the surface of the ceramic layer 1 of the varistor element 11, and as a result, a plating film is formed on a portion of the varistor element 11 where the surface resistance is low. Conceivable. This is also apparent from the fact that the formation of the compound layer 4 is insufficient and the place where the plating flow is generated coincides. From this, it is considered that the plating flow of the varistor element 11 does not grow from the external electrode 3 portion, but a plating film is formed on a portion having a low resistance value.
【0024】(実施の形態2)先ず、外部電極3と一体
焼成を行ったバリスタ素子11をSiO2粉末10と共
に、図2に示す内面が多角形の筒状のサヤ7に入れ、サ
ヤ7を回転速度0.3rpmで回転させながら860℃
で3から8時間熱処理を行いバリスタ素子11の外部電
極3を除く全面に高抵抗を有するZn−Si−O系、B
i−Si−O系の化合物層4を形成した。(Embodiment 2) First, the varistor element 11 integrally fired with the external electrode 3 is put together with the SiO 2 powder 10 into a cylindrical sheath 7 shown in FIG. 860 ° C while rotating at a rotation speed of 0.3 rpm
And a heat treatment for 3 to 8 hours, and a Zn—Si—O based material having high resistance on the entire surface of the varistor element 11 except for the external electrodes 3, B
An i-Si-O-based compound layer 4 was formed.
【0025】次に、バリスタ素子11の外部電極3の表
面に付着したSiO2粉末10を除去した後、外部電極
3上に電解メッキ法を用いNi膜5、更にその表面に半
田膜6を形成し積層体タイプのバリスタを完成させた。
得られたバリスタの化合物層4の厚さと、外部電極3以
外の表面のメッキ流れを検査しその結果を(表2)に示
した。尚、化合物層4の厚さはバリスタを研磨し形成さ
れた化合物層4の厚さを顕微鏡観察によって求めた。Next, after removing the SiO 2 powder 10 adhered to the surface of the external electrode 3 of the varistor element 11, a Ni film 5 is formed on the external electrode 3 by electrolytic plating, and a solder film 6 is further formed on the surface. Then, a laminated body type varistor was completed.
The thickness of the compound layer 4 of the obtained varistor and the plating flow on the surface other than the external electrode 3 were inspected, and the results are shown in (Table 2). The thickness of the compound layer 4 was determined by polishing a varistor and measuring the thickness of the compound layer 4 by microscopic observation.
【0026】[0026]
【表2】 [Table 2]
【0027】(表2)に示すように、本発明の化合物層
4の厚さが0.1から20μmの範囲ではメッキ流れが
発生していないのに対し、化合物層4が25μmより厚
くなると、バリスタの表面に部分的にメッキ膜が形成さ
れている。これは化合物層4とバリスタ素子11の膨脹
率の差から化合物層4が厚くなるとバリスタ素子11と
の間で歪みによりチッピングが発生しバリスタ素子11
の表面が部分的に露出した結果、その部分にメッキ膜が
形成されたものと思われる。As shown in Table 2, no plating flow occurs when the thickness of the compound layer 4 of the present invention is in the range of 0.1 to 20 μm, whereas when the thickness of the compound layer 4 is larger than 25 μm, A plating film is partially formed on the surface of the varistor. This is because, when the thickness of the compound layer 4 is increased, chipping occurs due to distortion between the varistor element 11 and the varistor element 11 due to a difference in expansion coefficient between the compound layer 4 and the varistor element 11.
It is presumed that the plating film was formed on the surface as a result of partially exposing the surface.
【0028】(実施の形態3)先ず、外部電極3と一体
焼成を行ったバリスタ素子11をSiO2粉末10と共
に、図2から図4に示す筒状のサヤ7,8,9に入れ、
サヤ7,8,9の可動方法を変えて860℃の温度で5
時間熱処理を行いバリスタ素子11の外部電極3を除く
全面に高抵抗を有するZn−Si−O系、Bi−Si−
O系の化合物層4を形成した。(Embodiment 3) First, the varistor element 11 integrally fired with the external electrode 3 is put together with the SiO 2 powder 10 into cylindrical sheaths 7, 8, 9 shown in FIGS.
Change the moving method of sheaths 7, 8, 9 to 5 at 860 ° C.
Zn-Si-O-based, Bi-Si-
An O-based compound layer 4 was formed.
【0029】次に、バリスタ素子11の外部電極3の表
面に付着したSiO2粉末10を除去した後、外部電極
3上に電解メッキ法を用いNi膜5、更にその表面に半
田膜6を形成し積層体タイプのバリスタを完成させた。
得られたバリスタの外部電極3以外の表面のメッキ流れ
を検査しその結果を(表3)に示した。Next, after removing the SiO 2 powder 10 adhered to the surface of the external electrode 3 of the varistor element 11, a Ni film 5 is formed on the external electrode 3 by electrolytic plating, and a solder film 6 is further formed on the surface. Then, a laminated body type varistor was completed.
The plating flow on the surface of the obtained varistor other than the external electrodes 3 was inspected, and the results are shown in (Table 3).
【0030】[0030]
【表3】 [Table 3]
【0031】(表3)に示すように、本発明の製造方法
によるサヤ7,8(図2,図3)の場合、回転(回転速
度0.3rpm)揺動(振り幅100mm、50サイク
ル/min)の何れともメッキ流れが発生していないの
に対し、図4の内面が平滑な円筒形のサヤ9ではバリス
タ素子11の表面に部分的なメッキ流れが発生してい
る。これは熱処理中のバリスタ素子11とSiO2粉末
10がサヤ9内で滑り十分に攪拌されないため化合物層
4がバリスタ素子11の表面に均質に形成されなかった
ものと思われる。従ってサヤ9の内面を多角形にする
か、または突起を形成することが化合物層4の形成に必
要となることを示している。As shown in Table 3, in the case of the sheaths 7 and 8 (FIGS. 2 and 3) according to the manufacturing method of the present invention, the rotation (rotation speed: 0.3 rpm) and the oscillation (oscillation width: 100 mm, 50 cycles / 4), a partial plating flow is generated on the surface of the varistor element 11 in the cylindrical sheath 9 of FIG. This is probably because the compound layer 4 was not uniformly formed on the surface of the varistor element 11 because the varistor element 11 and the SiO 2 powder 10 during the heat treatment slid in the sheath 9 and were not sufficiently stirred. This indicates that it is necessary to form the compound layer 4 by making the inner surface of the sheath 9 polygonal or forming protrusions.
【0032】尚、実施の形態1から3において、使用す
るSiO2粉末10は結晶性のものはバリスタ素子11
の表面との反応性が大きく、非晶質のものは反応性が小
さいので均質な膜厚の化合物層4を形成するには非晶質
のSiO2粉末10を用い比較的長い時間熱処理するの
が望ましい。また、本実施の形態では積層体タイプのバ
リスタについての結果を示したが、ディスク形バリスタ
等のセラミックス層1が外表面に現れているものについ
ては同様の効果が得られ有効である。In the first to third embodiments, the SiO 2 powder 10 used is of a crystalline type and the varistor element 11
Since the reactivity with the surface is large and the amorphous one has low reactivity, it is necessary to use an amorphous SiO 2 powder 10 and heat-treat for a relatively long time to form a compound layer 4 having a uniform thickness. Is desirable. Further, in this embodiment, the results for the laminated varistor are shown, but the same effect can be obtained and effective when the ceramic layer 1 such as a disk varistor appears on the outer surface.
【0033】[0033]
【発明の効果】以上のように本発明のバリスタでは、バ
リスタ素子の外部電極を除く全面に均質な膜厚の高抵抗
を有するZn−Si−O系またはBi−Si−O系の化
合物層を形成することによって、外部電極の半田付け性
を確保するためのNi、半田等の膜を電解メッキを用い
形成する際に、素子表面にメッキ流れが生じるのを防止
することができ、工業的に有効である。As described above, in the varistor of the present invention, a Zn-Si-O-based or Bi-Si-O-based compound layer having a uniform thickness and a high resistance is formed on the entire surface of the varistor element except for the external electrodes. By forming, by using electrolytic plating, a film of Ni, solder or the like for securing the solderability of the external electrodes can be prevented from causing plating flow on the element surface, and industrially It is valid.
【図1】本発明の積層体タイプのバリスタの断面図FIG. 1 is a sectional view of a laminate type varistor of the present invention.
【図2】同サヤの断面図FIG. 2 is a sectional view of the sheath.
【図3】同サヤの断面図FIG. 3 is a sectional view of the sheath.
【図4】内面が平滑なサヤの断面図FIG. 4 is a sectional view of a sheath having a smooth inner surface.
1 セラミックス層 2 内部電極 3 外部電極 4 化合物層 5 Ni膜 6 半田膜 7,8,9 サヤ 10 SiO2粉末 11 バリスタ素子1 ceramic layer 2 internal electrode 3 external electrodes 4 compound layer 5 Ni film 6 solder film 7,8,9 sheath 10 SiO 2 powder 11 varistor
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐々木 保彦 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 加藤 篤 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5E034 CC05 DA02 DB15 DC01 DC03 DC05 DC06 DC09 DE16 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiko Sasaki 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Atsushi Kato 1006 Odaka Kadoma Kadoma City, Osaka Prefecture Matsushita Electric Industrial F Term (reference) 5E034 CC05 DA02 DB15 DC01 DC03 DC05 DC06 DC09 DE16
Claims (6)
前記バリスタ素子の表面の一部に形成した一対の外部電
極と、前記外部電極の形成部を除く全面に厚さ(T)が
0.1<T<20μmの高抵抗体のZn−Si−O系ま
たはBi−Si−O系からなる化合物層を形成したバリ
スタ。A varistor element containing ZnO as a main component;
A pair of external electrodes formed on a part of the surface of the varistor element; and a high-resistance Zn—Si—O having a thickness (T) of 0.1 <T <20 μm on the entire surface except for a portion where the external electrodes are formed. A varistor on which a compound layer composed of a system or a Bi-Si-O system is formed.
内部電極とを交互に複数層積層した積層体である請求項
1に記載のバリスタ。2. The varistor according to claim 1, wherein the varistor element is a laminate in which a plurality of semiconductor ceramic layers and internal electrodes are alternately laminated.
納し、前記サヤを可動させながら所定温度で加熱処理を
行い、請求項1に記載の化合物層を形成するバリスタの
製造方法。3. The method for manufacturing a varistor according to claim 1, wherein the varistor element and the SiO 2 powder are housed in a sheath, and a heat treatment is performed at a predetermined temperature while moving the sheath.
記載のバリスタの製造方法。4. The method for manufacturing a varistor according to claim 3, wherein the sheath is rotated or rocked.
は請求項4に記載のバリスタの製造方法。5. The method for manufacturing a varistor according to claim 3, wherein the inner surface of the sheath is polygonal.
たは請求項4に記載のバリスタの製造方法。6. The method for manufacturing a varistor according to claim 3, wherein a projection is formed on an inner surface of the sheath.
Priority Applications (1)
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JP11204161A JP2001035706A (en) | 1999-07-19 | 1999-07-19 | Varistor and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP11204161A JP2001035706A (en) | 1999-07-19 | 1999-07-19 | Varistor and manufacture thereof |
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Publication Number | Publication Date |
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JP2001035706A true JP2001035706A (en) | 2001-02-09 |
Family
ID=16485855
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006287031A (en) * | 2005-04-01 | 2006-10-19 | Tdk Corp | Varistor and its production process |
US7705708B2 (en) | 2005-04-01 | 2010-04-27 | Tdk Corporation | Varistor and method of producing the same |
US11908599B2 (en) | 2021-08-31 | 2024-02-20 | Panasonic Intellectual Property Management Co., Ltd. | Varistor and method for manufacturing the same |
-
1999
- 1999-07-19 JP JP11204161A patent/JP2001035706A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006287031A (en) * | 2005-04-01 | 2006-10-19 | Tdk Corp | Varistor and its production process |
US7705708B2 (en) | 2005-04-01 | 2010-04-27 | Tdk Corporation | Varistor and method of producing the same |
US11908599B2 (en) | 2021-08-31 | 2024-02-20 | Panasonic Intellectual Property Management Co., Ltd. | Varistor and method for manufacturing the same |
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