JP2001035706A - Varistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a plating solution from flowing at electroplating by forming a Zn-Si-O or Bi-Si-O compound layer, having a uniform thickness and high resistance on the whole surface of a varistor element, excepting the external electrodes. SOLUTION: A varistor element 11 is manufactured, in such a way that a plurality of green sheets for ceramic layers 1 is formed by using slurry containing ZnO as a main ingredient, and internal electrodes 2 are formed on the surfaces of the green sheets by using Ag-Pd electrode paste. After the electrodes 2 are formed, a laminated green block is formed by laminating the green sheets upon another and cut into green chips having a prescribed shape. Then external electrodes 3, which are electrically connected to the internal electrodes 2, are formed on both end faces of each green chip, by applying electrode paste containing Ag-P as a main ingredient to the end faces. Thereafter, a Zn-Si-O or Bi-Si-O compound layer 4 is formed into a uniform thickness over the whole surface of the ceramic chip, except the external electrodes 3 by heat-treating the chip in SiO2 powder. Finally, Ni films 5 and solder films 6 are formed on the external electrodes 3 by electroplating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a varistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, ceramic electronic parts have been subjected to Ni plating and solder plating on the electrode surface in order to secure solderability at the time of mounting on a circuit board. However, Zn
In a varistor element containing O as a main component, a plating film is also formed on the element surface when performing electrolytic plating because ceramic is a semiconductor. In order to prevent this, a method of forming a high-resistance layer such as a Si compound on the surface of a varistor element has been proposed.

[0003]

SUMMARY OF THE INVENTION However, ZnO
If the surface of a varistor element mainly composed of is slightly exposed, a plating film is formed on the exposed portion. Therefore, it is necessary to completely form the high-resistance layer except for the external electrodes on the surface of the varistor element. Further, when the film thickness is too large, there is a problem that the film is easily peeled off due to a difference in expansion coefficient from the varistor element.

An object of the present invention is to provide a varistor in which a high resistance layer to which plating does not adhere is formed on the surface of a varistor element, and a method of manufacturing the varistor.

[0005]

In order to achieve this object, the present invention provides a Zn-Si-O-based or Bi-based material having a compound layer thickness (T) of 0.1 <T <20 μm over the entire surface of a varistor element. The objective is achieved by providing a uniform film of a compound layer having a high resistance of -Si-O system.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a varistor element containing ZnO as a main component, a pair of external electrodes formed on a part of the surface of the varistor element, The thickness (T) is 0.1 <T on the entire surface excluding the formation portion
<20 μm high-resistance Zn—Si—O-based or Bi—
A varistor having a Si-O-based compound layer formed thereon, the Zn-Si-O-based or Bi-Si-O-based compound layer having a high resistance on the entire surface of the varistor element excluding the external electrode, and having a uniform thickness. Is formed, it is possible to prevent plating on the surface of the varistor element during electrolytic plating.

According to a second aspect of the present invention, there is provided the varistor according to the first aspect, wherein the varistor element is a laminate in which a plurality of semiconductor ceramic layers and internal electrodes are alternately laminated. By forming a compound layer having a high resistance and a uniform thickness on the surface of the varistor element, it is possible to prevent the surface of the varistor element from being plated during electrolytic plating.

According to a third aspect of the present invention, the varistor element and the SiO ₂ powder are stored in a sheath, and a heat treatment is performed at a predetermined temperature while the sheath is being moved. This is a method for manufacturing a varistor to be formed, which is capable of forming a uniform-thickness compound layer of a Zn-Si-O-based or Bi-Si-O-based material having high resistance over the entire surface except for the external electrodes of the varistor element. it can.

According to a fourth aspect of the present invention, there is provided a method for manufacturing a varistor according to the third aspect, wherein the sheath is rotated or swung. The varistor has a high resistance over the entire surface except for the external electrodes of the varistor element. Zn-Si-O-based or Bi-Si-
An O-based compound layer having a uniform thickness can be formed.

According to a fifth aspect of the present invention, there is provided the method for manufacturing a varistor according to the third or fourth aspect, wherein the inner surface of the sheath is polygonal, excluding the external electrodes of the varistor element. A compound layer of a uniform thickness of a Zn-Si-O-based or Bi-Si-O-based material having high resistance can be formed on the entire surface.

According to a sixth aspect of the present invention, there is provided a method for manufacturing a varistor according to the third or fourth aspect, wherein a projection is formed on an inner surface of the sheath, except for an external electrode of the varistor element. A compound layer of a uniform thickness of a Zn-Si-O-based or Bi-Si-O-based material having high resistance can be formed on the entire surface.

(Embodiment 1) FIG.
1 is a sectional view of a varistor element 11 of FIG.
Lamix layer, 2 is an internal electrode, 3 is an external electrode, 4 is Zn
-Si-O-based or Bi-Si-O-based high resistance
The compound layer, 5 indicates a Ni film, and 6 indicates a solder film. Figure 2, Figure
3 and 4 are cross-sectional views of the sheath.
Ya, 10 is SiO _TwoPowder, 11 indicates a varistor element.

First, the main component ZnO and the sub-component Bi_Two
O_Three1.0 mol%, Co_TwoO_Three0.5 mol%, M
nO_Two0.5 mol%, Sb_TwoO_ThreeIs 0.5 mol%,
Al_TwoO _ThreeWeighed 0.005 mol%, and added
Butyl acetate and binder polyvinyl butyral
A plasticizer was added and mixed for 24 hours to prepare a slurry.

Next, the slurry was applied on a carrier film (not shown) using a known doctor blade method to form a green sheet (not shown) for the ceramic layer 1 having a thickness of 100 μm.

Next, an internal electrode 2 is formed by printing an electrode paste containing Ag-Pd as a main component on the green sheet surface.

Thereafter, a plurality of green sheets on which the internal electrodes 2 were formed were laminated to form a laminated green block (not shown). The stacking of the green sheets was carried out alternately by a predetermined size in the longitudinal direction of the formed internal electrode 2 for each layer.

Next, the green block was cut into a predetermined shape to obtain a green chip (not shown). The green chip has a structure in which one end portion of the internal electrode 2 is disposed on both end surfaces in the longitudinal direction with a green sheet interposed therebetween and is exposed to different end surfaces which are alternately opposed to each other.

Next, Ag-sides are applied to both end faces of the green chip.
An electrode paste containing Pd as a main component was applied so as to be electrically connected to the internal electrodes 2, and then baked at 900 to 960 ° C. for 1 hour to obtain a varistor element 11 in which the external electrodes 3 were formed.

Thereafter, the varistor element 11 is put together with the SiO ₂ powder 10 in a cylindrical sheath 7 shown in FIG. 2 and heat treated at 860 ° C. for 5 hours while rotating the sheath 7 at a rotation speed of 0.3 rpm. And a Zn-Si-O-based material having high resistance over the entire surface of the varistor element 11 except for the external electrodes 3.
A Bi-Si-O-based compound layer 4 having a uniform thickness was formed. The Zn—Si—O-based and Bi—Si—O-based high-resistance compound layer 4 is made of SiO ₂ powder having a Z value on the surface of the varistor element 11.
It can be formed by reacting with nO, Bi ₂ O ₃ at a temperature of 860 ° C.

Next, the varistor element 11 and the SiO ₂ powder 1
Taken out 0, after separation of the SiO ₂ powder 10 and the varistor element 11 by using a sieve to remove SiO ₂ powder 10 adhering to the surface of the external electrodes 3 and washed with varistor element 11 with pure water. Further, those in which the film of the compound layer 4 was insufficiently formed by the treatment of the SiO ₂ powder 10 were classified by visual inspection.

Next, a Ni film 5 was formed on the external electrodes 3 by electrolytic plating, and a solder film 6 was further formed on the surface of the Ni film 5 to complete a laminated varistor. With respect to the obtained varistor, plating flow on the surface other than the external electrode 3 was inspected, and the results are shown in (Table 1).

[0022]

[Table 1]

As is clear from Table 1, in the case where the compound layer 4 completely covers the surface of the varistor element 11 in the manufacturing method of the present invention, plating flow occurs because the compound layer 4 is a high-resistance body. On the other hand, when the compound layer 4 is incomplete, plating flow is partially generated. In addition, after the varistor element 11 was fired, the heat treatment using the SiO ₂ powder 10 was not performed and the electrolytic plating was performed.
It can be seen that plating flow has occurred over the entire surface of the substrate. This is because, since the varistor element 11 itself is a semiconductor, electrons are exchanged on the surface of the ceramic layer 1 of the varistor element 11, and as a result, a plating film is formed on a portion of the varistor element 11 where the surface resistance is low. Conceivable. This is also apparent from the fact that the formation of the compound layer 4 is insufficient and the place where the plating flow is generated coincides. From this, it is considered that the plating flow of the varistor element 11 does not grow from the external electrode 3 portion, but a plating film is formed on a portion having a low resistance value.

(Embodiment 2) First, the varistor element 11 integrally fired with the external electrode 3 is put together with the SiO ₂ powder 10 into a cylindrical sheath 7 shown in FIG. 860 ° C while rotating at a rotation speed of 0.3 rpm
And a heat treatment for 3 to 8 hours, and a Zn—Si—O based material having high resistance on the entire surface of the varistor element 11 except for the external electrodes 3, B
An i-Si-O-based compound layer 4 was formed.

Next, after removing the SiO ₂ powder 10 adhered to the surface of the external electrode 3 of the varistor element 11, a Ni film 5 is formed on the external electrode 3 by electrolytic plating, and a solder film 6 is further formed on the surface. Then, a laminated body type varistor was completed.
The thickness of the compound layer 4 of the obtained varistor and the plating flow on the surface other than the external electrode 3 were inspected, and the results are shown in (Table 2). The thickness of the compound layer 4 was determined by polishing a varistor and measuring the thickness of the compound layer 4 by microscopic observation.

[0026]

[Table 2]

As shown in Table 2, no plating flow occurs when the thickness of the compound layer 4 of the present invention is in the range of 0.1 to 20 μm, whereas when the thickness of the compound layer 4 is larger than 25 μm, A plating film is partially formed on the surface of the varistor. This is because, when the thickness of the compound layer 4 is increased, chipping occurs due to distortion between the varistor element 11 and the varistor element 11 due to a difference in expansion coefficient between the compound layer 4 and the varistor element 11.
It is presumed that the plating film was formed on the surface as a result of partially exposing the surface.

(Embodiment 3) First, the varistor element 11 integrally fired with the external electrode 3 is put together with the SiO ₂ powder 10 into cylindrical sheaths 7, 8, 9 shown in FIGS.
Change the moving method of sheaths 7, 8, 9 to 5 at 860 ° C.
Zn-Si-O-based, Bi-Si-
An O-based compound layer 4 was formed.

Next, after removing the SiO ₂ powder 10 adhered to the surface of the external electrode 3 of the varistor element 11, a Ni film 5 is formed on the external electrode 3 by electrolytic plating, and a solder film 6 is further formed on the surface. Then, a laminated body type varistor was completed.
The plating flow on the surface of the obtained varistor other than the external electrodes 3 was inspected, and the results are shown in (Table 3).

[0030]

[Table 3]

As shown in Table 3, in the case of the sheaths 7 and 8 (FIGS. 2 and 3) according to the manufacturing method of the present invention, the rotation (rotation speed: 0.3 rpm) and the oscillation (oscillation width: 100 mm, 50 cycles / 4), a partial plating flow is generated on the surface of the varistor element 11 in the cylindrical sheath 9 of FIG. This is probably because the compound layer 4 was not uniformly formed on the surface of the varistor element 11 because the varistor element 11 and the SiO ₂ powder 10 during the heat treatment slid in the sheath 9 and were not sufficiently stirred. This indicates that it is necessary to form the compound layer 4 by making the inner surface of the sheath 9 polygonal or forming protrusions.

In the first to third embodiments, the SiO ₂ powder 10 used is of a crystalline type and the varistor element 11
Since the reactivity with the surface is large and the amorphous one has low reactivity, it is necessary to use an amorphous SiO ₂ powder 10 and heat-treat for a relatively long time to form a compound layer 4 having a uniform thickness. Is desirable. Further, in this embodiment, the results for the laminated varistor are shown, but the same effect can be obtained and effective when the ceramic layer 1 such as a disk varistor appears on the outer surface.

[0033]

As described above, in the varistor of the present invention, a Zn-Si-O-based or Bi-Si-O-based compound layer having a uniform thickness and a high resistance is formed on the entire surface of the varistor element except for the external electrodes. By forming, by using electrolytic plating, a film of Ni, solder or the like for securing the solderability of the external electrodes can be prevented from causing plating flow on the element surface, and industrially It is valid.

[Brief description of the drawings]

FIG. 1 is a sectional view of a laminate type varistor of the present invention.

FIG. 2 is a sectional view of the sheath.

FIG. 3 is a sectional view of the sheath.

FIG. 4 is a sectional view of a sheath having a smooth inner surface.

[Explanation of symbols]

1 ceramic layer 2 internal electrode 3 external electrodes 4 compound layer 5 Ni film 6 solder film 7,8,9 sheath 10 SiO ₂ powder 11 varistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiko Sasaki 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Atsushi Kato 1006 Odaka Kadoma Kadoma City, Osaka Prefecture Matsushita Electric Industrial F Term (reference) 5E034 CC05 DA02 DB15 DC01 DC03 DC05 DC06 DC09 DE16

Claims (6)

[Claims] A varistor element containing ZnO as a main component;
A pair of external electrodes formed on a part of the surface of the varistor element; and a high-resistance Zn—Si—O having a thickness (T) of 0.1 <T <20 μm on the entire surface except for a portion where the external electrodes are formed. A varistor on which a compound layer composed of a system or a Bi-Si-O system is formed. 2. The varistor according to claim 1, wherein the varistor element is a laminate in which a plurality of semiconductor ceramic layers and internal electrodes are alternately laminated. 3. The method for manufacturing a varistor according to claim 1, wherein the varistor element and the SiO ₂ powder are housed in a sheath, and a heat treatment is performed at a predetermined temperature while moving the sheath. 4. The method for manufacturing a varistor according to claim 3, wherein the sheath is rotated or rocked. 5. The method for manufacturing a varistor according to claim 3, wherein the inner surface of the sheath is polygonal. 6. The method for manufacturing a varistor according to claim 3, wherein a projection is formed on an inner surface of the sheath.