JP2001028730A - Image pickup device, recording device, reproducing device and signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate unnaturalness at the time of recording or processing corresponding image signals and sound signals by recording the obtained image signals and delayed sound signals in a recording medium and controlling delay time in accordance with shutter speed. SOLUTION: Image signals obtained by an image pickup circuit 101 are outputted to a video memory 105. Sound signals obtained by a microphone 117 are outputted to a track memory 121. Parity data for correcting errors are added to the image signals and the sound signals by an error correction encoding circuit 127 and they are outputted to a formatter 129. At a slow shutter mode for example, the address of a track memory for sound signals 121 is controlled and the delay time of the sound signals is set to be longer than that at a regular mode. Thus, the timing of corresponding image and sound can be adjusted at the slow shutter mode and a sense of incongruity of the image and sound can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus, a recording apparatus, a reproducing apparatus, and a signal processing apparatus, and more particularly, to processing of an image signal and an audio signal.

[0002]

2. Description of the Related Art A camera-integrated VTR has been known as a device for recording and reproducing an audio signal and an image signal.
One of the functions of the camera-integrated VTR is a slow shutter mode. In this slow shutter mode, the reading rate of the image signal from the CCD, which is normally read at a rate of one field every 1/60 second, is made slower than usual, and the charge accumulation time in the CCD is made longer, so This makes it possible to shoot in dark conditions.

[0003]

However, in the normal shooting mode, the image signal from the CCD is updated as a field image every 1/60 second. / 8
When set to seconds, electric charges are accumulated on the CCD for four frame periods, so that the image is updated every four frames.

On the other hand, when an audio signal input from a microphone is recorded together with an image signal, the audio signal is input in real time from the microphone even in the slow shutter mode. Update timing is delayed. As a result, the timing of the image and the sound do not match during reproduction, and the user may feel uncomfortable.

An object of the present invention is to solve the above-mentioned problems.

Still another object of the present invention is to eliminate unnaturalness when recording or processing the corresponding image signal and audio signal.

[0007]

In order to solve the above-mentioned problems, according to the present invention, there is provided an image pickup means, a microphone means, a delay means for delaying an audio signal obtained by the microphone means, and an image pickup means provided by the image pickup means. Recording means for recording the received image signal and the audio signal delayed by the delay means on a recording medium, and control means for controlling a delay time of the delay means in accordance with a shutter speed of the imaging means. did.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the present embodiment,
A case where the present invention is applied to a camera-integrated VTR will be described.

FIG. 1 is a diagram showing a configuration of a VTR according to the present embodiment.

In FIG. 1, an image signal obtained by an image pickup circuit 101 is subjected to a known process by a camera signal processing circuit 103 and output to a video memory 105 of a memory unit M.

The image pickup circuit 101 has a CCD. In a normal recording mode, an image signal of one field interlaced is read out every 1/60 second and output to the camera signal processing circuit 103. The accumulation period of the CCD is changed according to the shutter speed specified by the control circuit 113. The camera signal processing circuit 103 has a memory capable of storing image signals for two frames therein, and the image signal output from the imaging circuit 101 is stored in the memory in the camera signal processing circuit 103, The readout of the image signal from this memory is controlled by 113.

The video memory 105 can store image signals for two frames, and the image signals read from the video memory 105 are output to the encoding circuit 107. The encoding circuit 107 encodes the image signal from the video memory 105 by well-known high-efficiency encoding such as DCT or variable length encoding, and stores the image signal track memory 1 in the memory unit M.
09 is output. The track memory 109 can store encoded image signals for three frames.

On the other hand, the audio signal obtained by the microphone 117 is subjected to high-efficiency encoding by the audio encoding circuit 119 and output to the audio signal track memory 121 of the memory M. The audio encoding circuit 119 has a memory capable of storing audio signals for two frames, and encodes the audio signals using this memory. The track memory 121 can store audio signals for a maximum of six frame periods as described later.

The sub-code generation circuit 123 generates sub-code data and outputs it to the sub-code track memory 125 in the memory M. The track memory 125 can store three frames of subcode data.

In the present embodiment, the memory section M is composed of one synchronous DRAM (SDRAM), and this one SD
By dividing and using the storage area of the RAM, the above-described video memory and track memory for each signal are realized. Then, the memory M
Of each memory is controlled.

The image signal stored in the track memory 109 and the audio signal stored in the track memory 121 are each added with parity data for error correction by an error correction coding circuit 127, and the formatter 129
Is output to Also, regarding the subcode, since the data amount of the subcode data is smaller than the image signal and the audio signal, and the configuration of the sync block is different from that of the image signal and the audio signal, the parity data is internally stored in the subcode generation circuit 123. Is generated and added, so that the subcode stored in the track memory 125 is output to the formatter 129 as it is.

The formatter 129 adds a sync signal and ID data to the image signal, the audio signal, and the subcode, rearranges the image signal, the audio signal, and the subcode according to the configuration of the tracks on the tape. And sub-codes in the order of output.

FIG. 2 shows the format on each track of the tape 133.

In FIG. 2, the head traces in the direction of arrow H, and the audio signal area 2
01, image signal area 203, subcode area 205
Is formed.

Each signal output from the formatter 129 is output to the recording circuit 131. The recording circuit 131 performs processing such as digital modulation on the signal from the formatter 129, and forms and records a large number of tracks on the tape 133 by a rotating head.

Reference numeral 111 denotes a recording / reproducing switch, a switch for setting various program AE modes, a switch for setting a shutter speed, and the like.
Imaging circuit 101, camera signal processing circuit 1
03 and the operation of the address control circuit 115.

Next, control of each memory of the memory section M by the imaging circuit 101, the camera signal processing circuit 103 and the address control circuit 115 in the normal recording mode and the slow shutter mode will be described.

FIG. 3 is a diagram showing the read timing of the image signal from the CCD of the image pickup circuit 101 at each shutter speed.

FIG. 3A shows a read timing in a normal recording mode.
The electric charges for one field stored in D are read out as electric signals.

FIG. 3B shows a shutter speed of 1/1.
The timing of reading the image signal when the time is set to 5 seconds is shown. As shown in the figure, 1/15 second (4
An image signal for one field is output for each (field period).

FIG. 3C shows a shutter speed of 1/8.
The timing of reading the image signal when set to seconds is shown. As shown in the figure, an image signal for one field is output from the CCD every 1/8 second (8 field periods).

FIG. 4 is a diagram showing how image signals are written to and read from a memory in the camera signal processing circuit 103 at each shutter speed.

As described above, the camera signal processing circuit 103
The memory in each of them can store image signals for two frames, and selectively writes and reads image signals to and from two memory banks each capable of storing one frame of image signals.

FIG. 4A shows the state of the write and read banks in the normal recording mode.
10 to n + 9 are shown. In the figure, 0 indicates that bank 0 is being accessed, and 1 indicates that bank 1 is being accessed. In (a), the write / read bank is switched and output for each frame.

(B) shows a case where the shutter speed is 1/1.
The case where it is set to 5 seconds is shown. In the figure,-indicates a state where no bank is accessed. That is,
In the case of the shutter speed 1/15 second shown in (b),
Since an image signal for one field is output from the CCD every four field periods (two frame periods), the frame n
After writing an image signal for one field in bank 0, an image signal for one field is written in the remaining one field area of bank 0 in frame n + 2 two frames later. Thereafter, an image signal for one field is written every two frames. On the other hand, for reading, an image signal is output by switching the reading bank every four frames.

FIG. 3C shows a shutter speed of 1/8.
It shows the case where it is set to seconds. Shutter speed 1 /
In the case of 8 seconds, an image signal for one field is output from the CCD every eight fields (four frame periods). Subsequent frame n
At +4, an image signal of one field is written to the remaining one field area of bank 0. Thereafter, an image signal for one field is written every four frames. On the other hand, for reading, an image signal is output by switching the reading bank every eight frames.

The control of the read timing shown in FIG. 3 and the control of writing and reading of the image signal to and from the memory shown in FIG. 4 are all controlled by the control circuit 113.

Next, control of the memory section M by the address control circuit 115 in each mode will be described.

FIG. 5 is a diagram showing how the address control circuit 115 controls each memory of the memory section M, and shows the state during eight frame periods from frame n to frame n + 7. The numbers 0 to 5 in FIG. 5 indicate the banks accessed in each memory. FIG. 5A shows an access state of each memory in the normal recording mode, FIG. 5B shows an access state of the audio signal track memory 121 when the shutter speed is 1/15 second, and FIG. This shows how the track memory 121 is accessed when the shutter speed is 1/8 second.

First, regarding the video memory 105,
As shown in (a) and (b), in frame n,
The image signal from the camera signal processing circuit 103 is written to the bank 0, and the image signal is read from the bank 1. Then, the writing bank and the reading bank are alternately switched every frame period, and writing and reading of the image signal are performed. A write bank for the video memory 105,
The read banks are determined by n mod 2 and (n-1) mod 2, respectively. The writing of the image signal to the video memory 105 is performed in the order of raster scan. When the image signal is read from the video memory 105, the image signal is shuffled in an order suitable for the encoding process in the encoding circuit 107, and the vertical The data is read in units of a DCT block of 8 pixels × 8 pixels.

Next, a track memory 109 for image signals is used.
As shown in (f) to (h), in the frame n, the bank 0 is written, the bank 2 is set to access the error correction coding circuit 127 (hereinafter, ECC), and the bank 1 is set to read. . In the next n + 1 frame, bank 1 is written, bank 0 is set to ECC, and bank 2 is set to read.
The ECC and the read bank are sequentially switched. Here, the error correction coding circuit 127 adds a parity of a product code configuration to the image signal for one track in the vertical and horizontal directions. In addition, reading is performed from the track memory 109 in order on the screen in units of image signals for one sync block. Writing to the track memory 109, E
CC and read banks are n mod 3, (n-2) mod
3, and (n-1) mod 3, respectively.

Next, the track memory 12 for the sub-code
For 5, as shown in (i) and (j), in frame n, write bank 0 and set bank 2 to read, and in frame n + 1, write bank 1 and set bank 0 to read. . Thereafter, the sub-codes are written and read by sequentially switching the three banks for each frame. The write and read banks for the track memory 125 are n mod 3 and (n−2) mod 3
Respectively.

Next, a track memory 121 for audio signals
Will be described. In the normal recording mode, four of the six banks of the track memory 121 are used. In the normal mode, as shown in (c) to (e), the audio signal written in bank 0 in frame n is
Error correction coding is performed on frame n + 2, and frame n
It is read at +3.

The reason why the audio signal is delayed by four frames as a whole is that the image signal output from the camera signal processing circuit 103 is delayed by one frame in the video memory 105 and is delayed by three frames in the track memory 109. The output is delayed by a total of four frames, so that the so-called lip sync is performed, which adjusts the timing of the image and the sound. Track memory 1 in normal mode
The write, ECC, and read banks for 21 are n
mod 4, (n-2) mod 4, and (n-1) mod 4.

As described above, in the normal recording mode, the audio signal can be synchronized with the image signal by delaying the audio signal by four frame periods by the track memory 121.

Next, a description will be given of the case of the slow shutter mode of 1/15 second.

FIG. 5B is a diagram showing how the address control of the track memory 121 for the audio signal is performed in the 1/15 second slow shutter mode. In the 1/15 second mode, five of the six banks of the track memory 121 are used. In 1/15 second mode, frame n
The audio signal written in the bank 0 in step (1) is subjected to error correction encoding processing in frame n + 3, and is read out in frame n + 4.

Therefore, in the 1/15 second mode, the audio signal is further delayed by one frame in the track memory 121 as compared with the normal mode, and is output after being delayed by five frames in total. Assuming that the average of the time difference between the image and the sound in the 1/15 second slow shutter mode is 1/30 second, in the case of the NTSC signal, the timing of the image and the sound is substantially synchronized by delaying one frame as compared with the normal mode. be able to.

The write, ECC, and read banks for the track memory 121 in the 1/15 second slow shutter mode are obtained by n mod 5, (n-2) mod 5, and (n-1) mod 5, respectively.

Next, the slow shutter mode of 1/8 second will be described.

FIG. 5C is a diagram showing the address control of the track memory 121 for the audio signal in the 1/8 second slow shutter mode. In the 1/8 second mode, all six banks of the track memory 121 are used. 1
In the / 8 second mode, the audio signal written to bank 0 at frame n is subjected to error correction encoding processing at frame n + 4, and is read at frame n + 5.

Therefore, in the 1/8 second mode, the audio signal is further delayed by two frames in the track memory 121 as compared with the normal mode, and is output after being delayed by a total of six frames.
By delaying two frames as compared with the normal mode, the timing of the image and the sound can be substantially synchronized.

The writing, ECC, and reading banks for the track memory 121 in the 1/8 second slow shutter mode are obtained by n mod 6, (n-2) mod 6, and (n-1) mod 6, respectively.

In both the 1/15 second mode and the 1/8 second mode, the address control for the video memory 105, the track memory 109, and the track memory 125 is the same as in the normal mode.

As described above, in this embodiment, in the slow shutter mode, the track memory 12 for the audio signal is used.
By controlling the address 1 to make the delay time of the audio signal longer than in the normal mode, the timing of the corresponding image and audio can be matched in the slow shutter mode, and the discomfort between the image and the audio is eliminated. be able to.

In the present embodiment, a slow shutter of 1/15 second or 1/8 second has been realized by the user's manual setting. However, the present invention is not limited to this, and the shutter speed and shutter speed are automatically adjusted according to the subject light. In automatic exposure control for controlling the iris, that is, in a so-called program AE mode, the delay time of the audio signal may be automatically controlled when it is determined that the subject is dark and a slow shutter is set.

That is, the program AE is operated by the operation unit 111.
When the mode is set, the control circuit 113
1 is output to the control signal. Imaging circuit 10
Reference numeral 1 sets a shutter speed and an iris so as to obtain an optimum exposure according to the state of the subject detected by an exposure detection circuit (not shown). Therefore, if the subject is very dark,
Although the shutter speed is set to be slow, the control circuit 1
A monitor 13 monitors shutter speed information from the image pickup circuit 101. If the shutter speed in the image pickup circuit 101 becomes a slow shutter, such as 1/15 second or 1/8 second, the address 13 is used as described above. A control signal is output to the control circuit 115 to control access to the memory unit M.

Next, a second embodiment of the present invention will be described.

FIG. 6 shows a digital VTR to which the present invention is applied.
FIG. 2 is a diagram showing a configuration of a reproduction system of FIG.

In FIG. 6, the reproducing circuit 303 is a tape 3
From 01, the audio signal, the image signal, and the subcode recorded in the format according to FIG. 2 are reproduced, restored to the original digital data, and output to the deformatter 305.
The deformatter 305 detects an image signal, an audio signal, and a subcode from the reproduction signal output from the reproduction circuit 303. Then, the image signal is output to the image signal track memory 307 of the memory unit M ′, the audio signal is output to the audio signal track memory 309, and the subcode is output to the subcode track memory 311. In FIG. 6, FIG.
The track memory 307 can store encoded image signals for three frames, and the track memory 309 can store audio signals for up to six frames. Further, the traffic memory 311 can store sub-codes for three frames.

The image signal and the audio signal written in the track memories 307 and 309 are respectively sent to the error correction circuit 31.
3, error correction processing is performed using the parity data added at the time of recording, and the track memories 307, 3
09 is written. The image signal subjected to the error correction processing is read from the track memory 307 in an order suitable for the processing by the decoding circuit 317, and output to the decoding circuit 317.

The decoding circuit 317 decodes the image signal from the track memory 307 in accordance with the encoding process performed at the time of recording, expands the amount of information, and outputs it to the video memory 315. The video memory 315 can store image signals for two frames, and stores the image signals output from the decoding circuit 317. The image signals stored in the video memory 315 are read in the order of raster scan and output to the output processing circuit 325.

On the other hand, the audio signal that has been subjected to the error correction processing is read out from the track memory 309 and is output from the audio decoding circuit 3.
19 is output. The audio decoding circuit 319 performs a decoding process on the audio signal read from the track memory 309 according to the time of recording, and outputs the result to the output processing circuit 325.

The output processing circuit 325 includes a video memory 315
The image signal and the audio signal from the audio decoding circuit 319 are converted into a signal of a format suitable for an external monitor or the like and output.

The subcode stored in the track memory 311 is output to the subcode detection circuit 321.
The subcode detection circuit 321 performs error correction processing on the subcode from the track memory 311 using the parity added at the time of recording, and further indicates the shutter speed at the time of recording the image signal reproduced from the subcode. The address control circuit 323 detects the shutter speed information.
Output to The address control circuit 323 controls writing and reading operations of each memory of the memory section M ′ based on shutter speed information from the subcode detection circuit 321 as described later.

Also in this embodiment, the memory section M 'is formed of a one-chip SDRAM, and the storage area of the SDRAM is divided and used for each memory.

Next, control of the memory section M 'in the present embodiment will be described. In the VTR of this embodiment, information indicating the shutter speed at the time of recording an image signal is recorded in a subcode, and the operation of the memory unit M 'is controlled using the shutter speed information at the time of reproduction.

FIG. 7 is a diagram showing how the address control circuit 323 controls each memory of the memory section M '.
The state of eight frame periods from the frame to the (n + 7) th frame is shown. The numbers 0 to 5 in FIG. 7 indicate the banks accessed in each memory.
FIG. 7A shows that the shutter speed at the time of recording the reproduced image is 1
3B shows an access state of each memory when recording is performed in the normal recording mode faster than / 60 seconds, and FIG. 4B shows an access state of the track memory 309 for an audio signal when the shutter speed is 1/15 seconds. (C) shows how the track memory 309 is accessed when the shutter speed is 1/8 second.

First, a track memory 307 for image signals
As shown in (a) to (c), in frame n, bank 0 is written, bank 2 is set to access the error correction circuit 313 (hereinafter ECC), and bank 1 is set to read. In the next n + 1 frame,
Bank 1 is written, bank 0 is set to ECC, and bank 2 is set to read.
C and the read bank are sequentially switched. Here, reading is performed from the track memory 307 in order on the screen in units of image signals for one sync block. Write, ECC, and read banks for the track memory 307 are n mod 3, (n-2) mod 3, and (n-1) mod 3
Respectively.

Next, the track memory 31 for sub-codes
As for (1), as shown in (g) and (h), in frame n, write bank 0 and set bank 2 to read, and in frame n + 1, write bank 1 and set bank 0 to read. . Thereafter, the sub-codes are written and read by sequentially switching the three banks for each frame. The write and read banks for the track memory 311 are n mod 3 and (n−2) mod 3
Respectively.

Further, regarding the video memory 317,
As shown in (i) and (j), in frame n,
The image signal from the decoding circuit 317 is written to the bank 0, and the image signal is read from the bank 1. Then, the writing bank and the reading bank are alternately switched every frame period, and writing and reading of the image signal are performed. The write bank and read bank for the video memory 315 are obtained by n mod2 and (n-1) mod 2, respectively. Writing of image signals to the video memory 315 is performed in the order of raster scan.
When the image signal is read from 07, the image signal is shuffled and read in an order suitable for the decoding process in the decoding circuit 317.

Next, a track memory 309 for audio signals is used.
Will be described. In the normal reproduction mode, four of the six banks of the track memory 309 are used. When recorded in the normal shooting mode, (d)-
As shown in (f), the audio signal written in bank 0 in frame n is subjected to error correction coding processing in frame n + 2, and is read out in frame n + 3. The reason why the audio signal is delayed by four frames as a whole is that the reproduced image signal is delayed by three frames in the track memory 307 and further delayed by one frame in the video memory 315, and is delayed by four frames in total. This is because the so-called lip-sync is performed to match the timing of the image and the sound. Write to track memory 309 when playback image signal is in normal shooting mode, EC
C, the read bank is n mod 4, (n-2) mod 4, (n-1) m
od 4 respectively.

As described above, in the normal recording mode, the audio signal can be synchronized with the image signal by delaying the audio signal by the track memory 309 for four frame periods.

Next, the case where the shutter speed in photographing the reproduced image signal is the slow shutter mode of 1/15 second will be described.

FIG. 7B is a diagram showing how the address control of the audio signal track memory 309 is performed in the 1/15 second slow shutter mode. In the 1/15 second mode, five of the six banks of the track memory 309 are used. In 1/15 second mode, frame n
The audio signal written in bank 0 is subjected to error correction processing in frame n + 3, and is read out in frame n + 4.

Therefore, in the 1/15 second mode, the audio signal is further delayed by one frame in the track memory 309 than in the normal mode, and is output after being delayed by five frames in total. Assuming that the average of the time difference between the image and the sound in the 1/15 second slow shutter mode is 1/30 second, in the case of the NTSC signal, the timing of the image and the sound is substantially synchronized by delaying one frame as compared with the normal mode. be able to.

The write, ECC, and read banks for the track memory 309 in the 1/15 second slow shutter mode are obtained by n mod 5, (n−2) mod 5, and (n−1) mod 5, respectively.

Next, the case where the shutter speed in recording the reproduced image signal is the slow shutter mode of 1/8 second will be described.

FIG. 7C is a diagram showing how the address control of the track memory 309 for the audio signal is performed in the 1/8 second slow shutter mode. In the 1/8 second mode, all six banks of the track memory 309 are used. 1
In the / 8 second mode, the audio signal written to bank 0 at frame n is subjected to error correction processing at frame n + 4 and read at frame n + 5.

Therefore, in the 1/8 second mode, the audio signal is further delayed by two frames in the track memory 309 than in the normal mode, and is output after being delayed by a total of six frames.
By delaying two frames as compared with the normal mode, the timing of the image and the sound can be substantially synchronized.

The write, ECC, and read banks for the track memory 309 in the 1/8 second slow shutter mode are obtained by n mod 6, (n-2) mod 6, and (n-1) mod 6, respectively.

In both the 1/15 second mode and the 1/8 second mode, the address control for the video memory 315, the track memory 307, and the track memory 311 is the same as in the normal mode.

As described above, in the present embodiment, when the image signal and the audio signal are reproduced from the tape, when the slow shutter mode is used when the reproduced image signal is photographed, the address of the track memory 309 for the audio signal is used. And the delay time of the audio signal is increased to adjust the timing of the image captured by the slow shutter and the corresponding audio at the time of reproduction, and it is possible to eliminate a sense of discomfort between the image and the audio.

In the above embodiment, the present invention is applied to a digital V
The case where the present invention is applied to the TR has been described. However, the present invention is also applicable to a case where an image signal and a corresponding audio signal are processed, and has the same effect.

[0080]

As described above, according to the present invention,
It is possible to control the difference in timing between the image and the audio, and to eliminate unnaturalness.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a digital VTR to which the present invention is applied.

FIG. 2 is a diagram showing a recording format by the VTR of FIG.

FIG. 3 is a diagram illustrating operation timings of an image pickup circuit of the device in FIG. 1;

FIG. 4 is a diagram for explaining an operation of the image pickup circuit of the device in FIG. 1;

FIG. 5 is a diagram for explaining a control operation of a memory in the device of FIG. 1;

FIG. 6 is a diagram showing another configuration of a digital VTR to which the present invention is applied.

FIG. 7 is a diagram for explaining a control operation of a memory in the device of FIG. 6;

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Claims (20)

[Claims] 1. An image pickup means, a microphone means, a delay means for delaying an audio signal obtained by the microphone means, and an image signal obtained by the image pickup means and an audio signal delayed by the delay means An imaging apparatus comprising: recording means for recording on a recording medium; and control means for controlling a delay time of the delay means according to a shutter speed of the imaging means. 2. The apparatus according to claim 1, wherein said delay means has an audio memory for storing said audio signal, and said control means controls said delay time by controlling an operation of said audio memory. Imaging device. 3. The audio memory has a plurality of banks each capable of storing the audio signal for a predetermined period, and the control means changes the number of banks for storing the audio signal according to the shutter speed. 3. The method according to claim 2, wherein
An imaging device according to any one of the preceding claims. 4. An encoding device for encoding the image signal, and an image memory for storing the image signal encoded by the encoding device, wherein the audio memory and the image memory are the same memory chip. The imaging device according to claim 2, wherein the imaging device is configured by: 5. An image processing apparatus comprising: an error correction encoding unit that performs an error correction encoding process on an image signal stored in the image memory and an audio signal stored in the audio memory; 5. The imaging apparatus according to claim 4, wherein access timing of the image signal and the audio signal to an encoding unit is controlled. 6. The image processing apparatus according to claim 4, further comprising a video memory for storing an image signal from said imaging unit, wherein said encoding unit encodes the image signal read from said video memory. Imaging device. 7. The imaging device according to claim 6, wherein the video memory is configured by the same memory chip as the audio memory and the image memory. 8. The imaging apparatus according to claim 1, wherein the control unit controls the delay time of the delay unit so that the delay time increases as the shutter speed decreases. 9. An image forming apparatus comprising: a setting unit for manually setting a shutter speed of the imaging unit; the imaging unit performs an imaging operation in accordance with the shutter speed set by the setting unit; The imaging apparatus according to claim 1, wherein the delay time is controlled according to a set shutter speed. 10. The imaging apparatus according to claim 9, wherein said imaging means has a CCD, and changes a charge accumulation time of said CCD according to a shutter speed set by said setting means. 11. The image pickup means has an exposure control means for controlling a shutter speed and an iris of the image pickup means, and the control means controls the delay time according to exposure information from the exposure control means. The imaging device according to claim 1, wherein: 12. An input unit for inputting an image signal obtained by an image pickup unit and an audio signal corresponding to the image signal, a delay unit for delaying the audio signal, and a delay unit for delaying the image signal and the delay unit. A recording device comprising: a recording unit that records the sound signal on a recording medium; and a control unit that controls a delay time of the delay unit according to a shutter speed of the imaging unit. 13. A reproducing means for reproducing, from a recording medium, an image signal, an audio signal, and control information indicating a shutter speed at the time of capturing the image signal, a delay means for delaying the audio signal, A reproducing apparatus comprising: processing means for processing an audio signal delayed by a delay means; and control means for controlling a delay time of the delay means according to the control information. 14. The apparatus according to claim 13, wherein said delay means has an audio memory for storing said audio signal, and said control means controls said delay time by controlling an operation of said audio memory. Playback device. 15. The audio memory has a plurality of banks each capable of storing the audio signal for a predetermined period, and the control means changes the number of banks for storing the audio signal according to the shutter speed. The playback device according to claim 14, wherein: 16. The image signal is encoded and recorded, and comprises: an image memory for storing the reproduced image signal; and decoding means for decoding the image signal read from the image memory. 15. The reproducing device according to claim 14, wherein the audio memory and the image memory are configured by the same memory chip. 17. An image processing apparatus comprising: an error correction unit configured to perform an error correction process on an image signal stored in the image memory and an audio signal stored in the audio memory. 17. The access timing of a signal and a voice signal is controlled.
The playback device according to any one of the preceding claims. 18. The apparatus according to claim 16, further comprising a video memory for storing an image signal from said decoding means, wherein said video memory comprises the same memory chip as said audio memory and image memory. Playback device. 19. The reproducing apparatus according to claim 13, wherein said control means controls a delay time of said delay means so as to increase said delay time as said shutter speed decreases. 20. An input unit for inputting an image signal and an audio signal corresponding to the image signal; a delay unit for delaying the audio signal; and processing the image signal and the audio signal delayed by the delay unit. A signal processing apparatus comprising: a processing unit that performs a delay time of the delay unit in accordance with a shutter speed at the time of capturing the image signal.