JP2001028550A - Flexible viterbi decoder for radio application - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain high flexibility with increased decoding performance and low power requirement. SOLUTION: A decoder 110 system is provided with a state metric update unit 120, including a state metric memory 126 and a cascade-type addition/ comparison/selection(ACS) unit 122. The unit 122 includes a plurality of serial connection ACS stages, in which a plurality of ACS processing, is executed together with the memory 126. One ACS state identifies a plurality of path decisions and operates, so as to transmit the identified path decision to the next ACS stage connected to the ACS stage. A trace back unit 130 is provided, a trace back memory 132 related to the unit 130 stores a set of cumulative path decisions, and the unit 130 carries out trace back of the memory 132. Path decisions relating to the ACS stage and the next ACS stage are accumulated as a set during ACS processing before being written to the trace back memory, and thus, an access to the trace back memory is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to Viterbi decoding systems and, more particularly, to a Viterbi algorithm for convolutional codes for wireless and other types of communication applications. System) that provides flexible, fast and low power decoding.

[0002]

2. Description of the Related Art Recent years have seen a dramatic increase in wireless communications. Wireless technology (eg satellite, microwave)
Provides a system in which the need for cellular and other communications is constantly increasing. To meet the demand for increased and reliable communication capabilities, more flexible, power and efficient systems are needed. In particular, in order to meet the increasing needs of society for wireless communication, forward error correction is needed.
on) The system must be improved.

[0003] Forward error correction systems are a necessary component in many of today's communication systems. These systems generally add robustness to a communication system by substantially correcting errors that may occur during transmission and reception of wireless data. This is especially true for systems with limited power and / or bandwidth.
Often, in such forward error correction systems,
Convolution coding is a key part. In general, convolutional coding systems introduce redundant data into the wireless data transmission so that random errors that occur in the transmission have a high probability of being corrected. As a result, by providing a decoding system (eg, a Viterbi decoder) in place, the convolution coded data is decoded when the transmitted data is received, thereby reconstructing the actual data transmission. I need to be able to do it.

Referring to the prior art FIG. 1, a wireless communication system 10 illustrates certain problems that have been presented in conventional wireless systems. Transmitter 20 directs communication signal 24 to satellite system 30. The satellite system 30
Upon receiving the communication signal 24, it directs the communication signal 24a to a terrestrial base station 32, where it is processed for its intended destination. Communication signal 24 and communication signal 24a
At any time during transmission, the noise 34 can disrupt parts of the transmission (causing errors), which can cause improper signal reception at the base station 32. If no error correction system is provided, the signal will likely have to be retransmitted in order to be properly received at base station 32. Therefore, there is a high possibility that inefficiency and cost increase will occur.

FIG. 2 shows a prior art error correction system 40 that uses convolutional encoding and Viterbi decoding to increase the probability that a transmitted signal will be properly communicated in the presence of noise. I have. Input data 42 (eg, audio, video, computer data) is input to a convolution encoder 44. The encoded data is provided as a sequence of data bits 46 (also referred to as an encoding code), which consists of the actual data and redundantly appended data,
To send over. Communication link 48 may introduce noise into its data transmission, so that transmitted data bits 46 may be corrupted by the time they reach their destination. Each received (possibly corrupted) data bit 46a is processed by a Viterbi decoder 50 to provide decoded output data 52.
The Viterbi decoder 50 (based on the Viterbi algorithm first proposed by Andrew Viterbi in 1967) is transmitted even if noise affects some of the transmitted (convoluted) data 46. A decoding system capable of determining the input data 42 with high probability. In general, the input data 42 can be determined by calculating a maximum likelihood sequence for the input data 42 obtained from the convolved encoded data 46a.

[0006] Convolutional encoding is
It is performed by convolving (redundantly adding) input data bits 42 with one or more previous input bits 42 via an encoder. An example of a convolution encoder 44 with a convolution rate of 1/2 and a suppression length of 9 is shown in FIG. 3 of the prior art. The input bits 42 correspond to the outputs X ⁰ to
The X ⁸ is input to a series of delay elements 60, such as a shift register 44a supplies. These outputs X ^{0 to} X ⁸ are XO
Combined by the R functions 62a, 62b to generate the encoded code sets G ₀ , G ₁ . XOR function 62
The outputs X ⁰ -X ⁸ connected (tapped) to a, 62b are G ₀ and G ₁ for a given input data sequence 42.
Determine the output code sequence of. This input-output relationship can be described by a code polynomial for encoder outputs G ₀ and G ₁ . For example, for the encoder 44 shown in FIG. 3, the code polynomial is given as follows:

G ₀ = X ⁰ + X ¹ + X ³ + X ⁶ + X ⁸ = 1 + X ¹ + X ³ + X ⁶ +
^{_{X 8 G 1 = X 0 +}} X 2 + X 3 + X 7 + X 8 = 1 + X 2 + X 3 + X 7 +
X ⁸ Note) TMS320C54x family Viterbi decoding technology, in 1996, Texas Instruments application report SPRA071 shows further details related to the convolution encoder and its code polynomial, also, in the body by this reference Incorporated.

As shown, the encoder 44 of FIG.
Generate encoding code sets G ₀ and G ₁ for all input bits 42. In this way, the encoder
It has a rate of 1/2 (1 input / 2 output). The suppression length (K) represents the total span of the combination used by the encoder, which is a function of the number of delay elements 60. Suppression length K
= 9 means that there are 2 ^(9-1) = 256 encoder states (the ninth bit is an input bit). These states are represented by state S0 (binary “00000000”) to state S255 (binary “11111111”).

[0009] The convolutional encoded data can be decoded according to the Viterbi algorithm. The basis of the Viterbi algorithm is a possible encoder 4 from one given state to the next based on the dependence of a given data state on past input data 42.
By using knowledge of the four output state transitions (eg, simulating an encoder), the convolution
Decoding the encoded data. Acceptable state transitions are typically represented in a trellis diagram (similar to a convolution state diagram) that provides a possible state path for a received data sequence based on the encoding process of the input data 42. The trellis structure is determined by the overall structure of the convolution encoder 44 and the code polynomial configuration described above. The Viterbi algorithm uses the transmit encoder 44
A method is provided that minimizes the number of state paths through the trellis by limiting the output sequence to the one with the highest probability of matching the received data sequence at the decoder.

FIG. 4 is an illustration of a portion of a trellis 66, illustrating the basic Viterbi algorithm butterfly computation. Four possible encoder transitions 70a-70d from the current state nodes 68a, 68b to the next state nodes 68c, 68d are shown. As shown, the two transition paths (branches) correspond to each current state node 68a, 6
8b to each next state node 68c, 68d.
The Viterbi algorithm "survives" after the most probable of the two possible transition paths has been determined.
Provide a process that is selected as part of the path. For example, the branches 70a and 70b are connected to the next state node 68c.
Provides two possible transition paths. Similarly, branches 70c, 70d provide two possible transition paths to next state node 68d. The transition paths 70a to 70d are:
It provides a possible direction to the next maximum likelihood state generated by convolution encoder 44 as indicated by input bit 42. Once (multiple butterflies
Once the survivor path of one sequence has been determined (through the stages), the most likely data input sequence 42 to the convolution encoder 44 can be reconstructed, so that the convolution encoding data is Decoded.

The decoder operation generally includes a branch metric calculation, an add / compare / select (ACS) process, and a traceback process. The branch metric calculation provides a measure of the likelihood that a given transition path from the current state to the next state is correct. In the branch metric calculation, a received data value, typically an 8-bit or 16-bit digital value representing the magnitude of the voltage or current of the input signal, is processed, resulting from a state transition from the current state to the next state. The Euclidean or equivalent distance between the received data value and all possible actual data values not corrupted by noise (see T.
I).

For this reason, decoding the data signal from the rate 1 / R convolution decoder having the suppression length K means that a total of 2 ^R branch metric values for each encoding code input to the decoder are obtained. It is necessary to judge. As described, the set of 2 ^R branch metric values is defined as the complete branch metric set for one particular received input code.

In the next decoder step, the previously calculated branch metric values for all possible state transitions are processed to determine the "cumulative distance" for each of the paths to the next state. The path with the minimum or maximum distance (ie, maximum probability) depending on the implementation is selected as the survivor path. This is known as an add / compare / select or ACS process. The ACS process can be broken down into two basic processes. The addition process, ie, the route metric calculation, and the comparison / selection process. The path metric addition process is the accumulation of the current state value with the branch metric value for the received data input sequence (initialized by the user at the start of the Viterbi process and carried forward from state to state). The comparison / selection process calculates and compares the two values from the addition process to determine its minimum (or maximum, depending on the implementation) and determines one or more "traceback bits". Memorize and indicate the selected survivor path.

The last decoding step is a traceback process. This step traces the maximum likelihood path through the trellis of the state transition, as determined by the first two steps, and reconstructs the most likely path through the trellis and is input to the encoder 44. Extract the original data.

[0015]

Conventionally, various Viterbi decoding applications have been addressed by using a digital signal processor (DSP). Many DS
P has special instructions specifically designed for the Viterbi decoding algorithm. For example, many of today's cellular telephone applications include DSP solutions. However, when using a code like the one described above (K = 9) with high data rates (384 kbits / sec to 2 Mbits / sec), high computation rates are generally required. This may require 49 × 10 ⁶ to 256 × 10 ⁶ Viterbi ACS processing per second. These computations are multiplied, for example, if multiple voice / data channels are processed by the DSP of the cellular base station. For this reason, Viterbi decoding may consume a large part of the computation bandwidth of the DSP. As a result, higher performance systems are needed to meet the increasing computational demands.

Another problem faced by conventional decoding systems is the need to decode various forms of convolutional codes. Many decoding
The system is hardwired or hardcoded to handle certain types of convolutional codes. For example, the suppression length K described above
May change from one encoding system to the next (eg, K = 9, 8, 7, 6, 5, etc.). Also, the above code polynomial may change from system to system, even if the suppression length remains unchanged. Hard-wired or hard-coded decoding systems need to be redesigned to meet these different encoding requirements. Various other parameters may also need to be changed in the encoding / decoding process. Accordingly, it is desirable for a decoding system to provide a high degree of flexibility in processing various forms of encoded data.

[0017] Yet another problem faced by conventional decoding systems is the increased power requirements. As data is decoded at higher rates, the computational requirements of the decoding system often increase the power requirements of the decoder (eg, DSP, processing system). Many conventional systems require extensive register and memory access during the decoding process. This generally increases the power consumed by the decoder and generally reduces decoder performance (eg, speed, reliability).

Accordingly, in view of the above-mentioned problems associated with conventional decoding systems, it would be desirable to have a Viterbi decoding system and method that provides increased flexibility in increased decoding performance and lower power requirements. desirable.

[0019]

SUMMARY OF THE INVENTION The present invention is operable in a programmable DSP system and provides flexibility, low power and high data throughput.
It is directed to a VLSI architecture for a Viterbi decoder for wireless or other types of applications that provides rates. This architecture is intended to provide a cost-effective solution for a number of application areas, including cellular base stations and mobile handsets.

The decoder preferably has a rate 1 / n
Operates on a plurality of common linear convolutional codes with a suppression length of K = 9 (256 states) or less, with K = 9 allowing a substantially higher throughput rate of 2.5 Mbps. In particular, high data throughput rates are achieved with cascaded ACS systems operating simultaneously over several trellis stages. In addition, the cascaded ACS performs partial pre-traceback processing during the ACS processing over multiple trellis stages. This increases system throughput by reducing the complexity of the final traceback process of retrieving decoded output bits, and by substantially reducing the number of memory accesses associated therewith. Let it.

This high data throughput rate allows the decoder to handle virtually hundreds of voice channels for next generation cellular base stations. This promises to greatly reduce the number of DSP processors required by the system and to reduce the system cost of a pure DSP based system. These types of data rates and codes are widely used in various wireless applications, from satellite communications to cellular telephones.

Variations between specific encoding applications and within some decoding applications regarding the exact structure of the Viterbi decoding problem provide flexibility in the decoding architecture. In particular, the cascaded ACS system described above
By operating over multiple stages of the trellis for K = 9, it can be configured to operate on variable suppression length codes. This is achieved by operating on a sub-trellis architecture with state metric memory. For K <9, certain ACS stages are selectively bypassed.

The present invention allows the decoder to be used in many changing situations by incorporating a high degree of flexibility. Decoder flexibility includes variable suppression length, user-supplied polynomial code coefficients, code rate, and traceback settings such as convergence distance and frame structure.

A DSP interface is provided which is memory mapped to allow high data rate transfers between the decoder of the present invention and the DSP. This greatly reduces the processing burden on the DSP and provides a more powerful overall system. Considerable buffering is also provided within the decoder. The present invention also supports intelligent data transfer and synchronization mechanisms, including various trigger signals, such as execution complete, input buffer low and transmit / receive block transfer completion.

Furthermore, the present invention is designed to operate at high data rates and to be energy efficient (ie, low power). Low power operation is achieved by minimizing register operations and memory accesses, and by parallelizing and streamlining certain aspects of the decoding process. For example, the above-described ACS process executes a pre-traceback process during the ACS process. In addition, by operating simultaneously across many stages of the trellis, memory
Access is reduced. In order to achieve the above object and related objects, the present invention has the following features. The following description and the annexed drawings set forth in detail certain embodiments of the invention. But,
While these embodiments are representative, they are merely some of the various ways in which the principles of the present invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.

[0026]

Next, the present invention will be described with reference to the drawings. In the drawings, the same reference numerals are used to refer to the same elements. According to the present invention, the Viterbi decoder 110 (FIG. 6)
2 (FIG. 7) through multiple trellis stages (FIG. 5)
Are decoded simultaneously. This substantially reduces memory access cycles, thereby lowering power requirements and increasing system throughput.
During cascaded ACS processing, partial traceback of the trellis occurs simultaneously during ACS operation via a unique register exchange architecture (FIG. 8). This also reduces power requirements and increases system throughput. In addition, variable suppression length codes can be resolved via a bypass system implemented in the cascaded ACS 122, and multiple user-supplied code polynomials can be used to decode various encoding structures. (Figure 9). This provides the decoder 110 with a significant degree of flexibility.

Referring first to FIG. 5, the trellis diagram is:
Shown in accordance with one embodiment of the present invention. The trellis corresponds to a convolutional encoder from one shift register code with 16 states (K = 5). These 16 states have state indices 0 to 15
(For example, 100a, 100b, and 100c), and the state indexes 0 to 15 are stored in the column C1.
C5 to C5 and correspond to a particular point in time (e.g., transition from one encoder state to the next encoder state). Transitions between columns may also be referred to as stages (eg, stage 1, stage 2, etc.). Each stage is from the previous state (left) to the current or next state (right)
To provide a left-to-right input-output bit mapping to a set of branches (eg, 102a, 102a).
b) represents possible bit transitions between stages.
This input-output (stage-to-stage) bit mapping is provided by a set of code polynomials that describe the encoder configuration and are supplied by the user.

The state index is generated as a pointer to a memory location that holds the accumulated state metrics from the previous stage (described in more detail below). Note that each state index in each column can only transition (giving output) to two other defined state indexes in the next stage to the right of the figure. Similarly, each state index in one column to the right of one column only receives two inputs from the defined state index to the left. For example, state 8 in column C1 can only transition to state 0 or state 1 in each of columns C2, C3, C4, etc.
Similarly, state 12 in any column is determined by columns C1, C
2, C3 etc. only receive input from state 6 or state 14.

As will be explained in detail below, one possible path in the trellis that ultimately determines the original input data to the encoder is, in the present invention, for each set of branches entering each state. The determination is made by performing an ACS (addition / comparison / selection) operation. A set of branch metrics (described in more detail below) is the cumulative state metric from the preceding stage (initially, the cumulative state metric in column C1 has a desired predetermined value (eg, a value of 0 or a very large number). ) Can be reset)) (the addition part of the ACS). Next, select one branch from each ACS operation based on which branch generates the lowest or preferably the highest cumulative state metric for the next stage (AC
S comparison and selection part). After resolving a number of stages via the ACS operation, the selected branches will begin to converge on one overall path. By tracing back one path through each stage from the selected branch (described in more detail below), the decoded data can be determined.

FIG. 6 shows a top-level schematic block diagram of a Viterbi decoding system 110 according to the present invention, which generally comprises two main units, a state metric update unit 120 and a trace. And a back unit 130. The state metric updating unit 120 includes a cascaded ACS.
122, the state metric memory 126, and the branch metric 13 from the traceback unit 130.
4 and the branch metric 134 is set to A
And a branch metric selection unit 138 for synchronizing with the CS 122.

Cascaded ACS 122, along with state metric memory 126, provides a set of cumulative state metrics (SM) 125 for each stage in the trellis as the decoding process moves forward in time.
(Also called a route metric). Cascaded ACS 122 has a set of incoming branch metrics 13
4 to perform addition, subtraction, and comparison, and the route judgment value 1
Select a new state metric that determines 24. This is done by evaluating the metric in each state to determine which of the two incoming branches provides the smallest or preferably the largest next state metric 125 depending on the particular algorithm implementation desired. Is achieved. The evaluation is performed by ACS 122 by adding branch metric 134 to state metric memory 126, which is addressed by the state index at which the branch left. As described in detail below, (preferably, the peripheral DSP 140
Branch metric 134)
Multiple sets of numbers (one per trellis stage) obtained from the convolved input data to the decoder and typically a measure of the distance between the receiver (input) soft decisions and the known modulation points. Pair). However, other forms of branch metric data may be used, and such data forms are contemplated to be within the scope of the present invention.

Preferably, SRAM memory 126 stores the set of state metrics 125 that are continuously read, updated and written back. Route decision value 124 is provided by cascaded ACS 122 to traceback unit 130 and its associated memory 132,
Here, the route determination value 124 is, as described in detail below,
Used for traceback determination of decoded data.

An address / control block 136 supervises the data passing through the trellis and stores the state metric memory 12
6 provides memory addressing. The address / control block 136, described in detail below, is responsible for generating a state index based on the user supplied suppression length. The address / control block 136 converts the branch metric 134 received at the branch metric selection unit 138.
In synchronization with the ACS 122.

Traceback unit 130 is another primary unit according to the present invention and performs a number of functions. The traceback unit 130 stores the path decision 124 received from the cascaded ACS 122 and then performs a traceback. The traceback process creates an output (decoded) bit, and outputs the decoded output and incoming branch metric 1
Provide storage for. Traceback unit 130 preferably includes one or more memories 132 for storing such data.

The unique features of decoding system 110 are that decoding system 110 and system 1
10 lies in the division of the entire decoding process with the DSP 140, which preferably provides support. All of the branch metric calculations are preferably performed outside system 110, preferably in DSP 140. Similarly, a depuncture operation may be performed by the DSP 140 (eg, inserting a null or other compensation value into the input stream). This provides more user control over these functions (eg, branch metric calculation, depuncturing, etc.).

The operation of the decoder system 110 is flexible. That is, it can operate for suppression lengths of 5 to 9 and can operate on 25
Up to 6 states can be processed simultaneously. System 11
0 is rate 1 with any set of user-supplied code coefficients
/ 2 and rate 1/3. Also, the bit rate can be variable (eg, the decoder can operate by detecting a fixed size received data frame regardless of the bit rate). The system 110 has a framing input in which the tail of the data (input bits inserted to force a particular state) forces a return to state zero or the system runs in a continuous decode mode without a forced state. Process the data. Certain options are also available for effectively presetting the state metric at the beginning of a frame. For example, the user may set the initial metric of state zero to the highest value and set all other states to the lowest value to return all traceback paths to state zero at the beginning of the frame. Sometimes you want to force. The convergence distance utilized by the traceback process before generating the output bits is also an adjustable parameter, supplied by the user.

The DSP interface circuit 144 includes a memory mapping function for the decoder system 110.
Provide an interface. The DSP interface 144 provides incoming branch metrics and outgoing (outg)
oing) Operates using block bit transfer of decode bits (shown as bus 146). These transfers may be performed using DMA (or other) peripheral DSP support. Thus, the bus is used efficiently and minimal interaction is required from DSP 140.

Next, referring to FIG.
A more detailed block diagram of CS 122 is shown in accordance with the present invention. ACS unit 122 converts a set of state metrics 125 (from state metric memory 126 in FIG. 6) to a corresponding set of state metrics (received from traceback memory 132, collectively labeled 134). Process with branch metrics 134a-134d. This is achieved by processing the set of state metrics 125 carried through the trellis shown in FIG. 5 as a cumulative state metric forward from stage to stage in time. In each of the trellis stages corresponding to the ACS stages 150b to 156b, the accumulated state metric is the branch metric data 13
4 is updated. State metric updates are achieved by determining the best branch (identified path decision) from the two possible trellis branches from the previous trellis state. Note that one ACS process is provided for each node in one column per trellis stage. For example, in FIG.
ACS operations are provided for columns C2, C3, C4, and C5, so each column includes 16 ACS operations per ACS stage 150b, 152b, 154b, 156b of FIG.

The optimal branch refers to the branch (identified path) that yields the smallest or preferably the largest next state metric, which is the cumulative state metric 125 of the trellis state from which the trellis branch came out.
By adding the branch metric 134 to the Each trellis branch corresponds to a set of possible output bits, and the branch metric corresponds to a distance measurement from the output bits to the received input data. The output bits are preferably mapped to a constellation point to be transmitted, and the branch metric is the Euclidean distance between the received data and the satellite point. Branch metric calculations are well known in the art, and further description thereof will be omitted for brevity.

When the ACS process is performed, the selected branch (eg, path decision) for each state at each stage of the trellis is recorded. For this reason, the optimal route (for example, the identified route) to each state is known. Next, the output of the decoder system 110 is determined by traversing the trellis in the reverse direction along the branch selected above. After a certain distance (known as the convergence distance), all identified paths from other trellis states are likely to converge on a single path. At this point, valid decode output bits are obtained from the traceback process described in detail below.

As shown in FIG. 7, the ACS unit 122 of the present invention forms a cascade, and includes delay registers 160a to 160f and a cross switch 16 between blocks.
It consists of four ACS blocks 150b-156b with a grouping of 2-164. Each ACS block performs a plurality of radix 2 or butterfly addition / comparison / selection processes for one stage of the trellis. The ACS cascade 122 is a trellis 4
A radix-16 ACS process is executed for one stage. The radix N indicates the size of the sub-trellis to be processed. N refers to the number of states and must be a power of two. As will be described in detail below, the trellis shown in FIG. 5 can be applied to multiple states up to 256 per stage for K = 9 by using the trellis shown in FIG. 5 as sub-trellis for multiple states. can do. For more information on basic cascade structure processing, see Algorithms and Architectures for Fast Viterbi Decoding.
for high speed Viterbi decoding ”, Ph. D. Dissert
ation, Dept. of Electrical Engineering. Stanford U
niversity, 1993, by Peter Black), which is hereby incorporated by reference in its entirety.

The radix-16 ACS operates on a 16 state trellis and computes a new state metric for one forward step of the four stages of the trellis. This cascade implementation accomplishes this by calculating a state metric for each intermediate stage (two states per radix-2 ACS unit in ACS blocks 150b-156b) and passing the accumulated state metrics. With appropriate reordering to the next cascade stage (routing the output of the current stage to the correct input of the next stage). Registers 160a-16 between ACS blocks 150b-156b
0f and cross switches 162-166 perform the reordering defined by the particular trellis stage. The cross switch passes data through or exchanges the data on two buses (shown as bus A and bus B), depending on which part of the trellis is being processed. The cross switch setting may change at a set rate during operation of the decoder 110.

For processing on a convolutional code having 256 states, the trellis can be considered to consist of an interleave of 16 sub-trellis of size 16. For this reason, these sub-trellis are organized in a cascaded ACS data path 12 in a sequential manner.
2 are supplied one by one. The correct node for each sub-trellis is read from SM memory 126 and ACS
The data is supplied to the data path 122, and the result is stored back in the SM memory 126. For all suppression length cases (K = 9 to 5), "in-place scheduling" is used, and therefore only one copy of the state metric is stored. "In-Place Scheduling" uses ACS
Refers to overwriting the previous state metric with the new state metric result after the calculation is completed.

The method of dividing the trellis where "in-place scheduling" takes place into sub-trellis has two phases, phase A and phase B, which are used when moving forward through the trellis. Repeated. For example, the 16 state trellis of FIG.
One stage can be divided into size 4 sub-trellis. Phase A covers stage 1 and stage 2, where the sub-trellis is interlaced. Phase B covers stage 3 and stage 4, where the sub-trellis are separated and each one appears on another. This results in two distinct phases for generating the memory address and state index.

[0045] Compared to the more traditional approach, which can operate on only one stage of the trellis at a time, the radix-16 cascade approach of the present invention is more energy efficient. Whereas the traditional approach requires reading and writing all state metrics once per stage, the present invention reduces this to once per four stages. Therefore, memory I / O transactions consume large amounts of power,
Power can be saved.

More efficient traceback processing (described later)
To provide a partial traceback of length 4 (part
A new method of implementing ial traceback) is implemented during the cascaded ACS process. Pre-traceback means that a partial traceback is performed for each trellis state before storing path decision information for later traceback completion. In accordance with the present invention, the system used to perform pre-traceback is a unique register exchange (170a, 170b in FIG. 8) and reordering hardware 160a-160f, 162 located between the ACS blocks 150b-156b. , 163, and 164.

FIG. 8 shows a pre-traceback system according to the present invention. ACS of reordered structure
Registers 166, which are part of the data path, are wider as (n) to allow them to hold an accumulating pre-traceback path. Register 166 also provides the 10-bit accumulated state metric value from the previous stage. Here, it should be noted that n is equal to 0 bits before stage 150b in FIG. 7, since no trellis has been resolved (ACS path determination) at this time. In the stage 152b, since one stage is determined (path selection), n is equal to 1 bit. In the stage 154b, n = 2 bits.
In the stage 156b, n = 3 bits. After each ACS block 168a, 168b (the upper half 168a of the ACS block determines the path to the upper butterfly node and the lower half 168b of the ACS block
Determine the route to the node), and the additional 1 bit is A
It is supplied to the next stage as a result of the CS processing.

This additional bit indicates which path has been selected from the preceding stage as a result of the ACS processing. Bits 172a and 172b are set in ACS block 16
8a, 168b, which are supplied as additional bits and are carried forward (forwarding) from the preceding stage to be attached to the selected route from the current stage.
4a to 174d (multiplexers 170a and 170b
Select via). The selected pretrace back bit from the previous stage (multiplexer 170a,
The function of appending these additional bits from the current stage to the (output of 170b) is indicated by reference numerals 176a, 176b. Next, the register path to the next stage is n
Represented as +1 to indicate the accumulation of partial pretraceback bits sent out to the next successive stage.

The register exchange described above for partial pretraceback, combined with the cascaded ACS 122, provides a unique decoding architecture for reducing memory access and power consumption. The register exchange associated with the cascaded ACS of the present invention updates the traceback memory (described below) after determining the path to the four stages of the trellis. This reduces memory access by a factor of four. This substantially reduces power consumption and also reduces decoder 11
0 performance is substantially increased.

The cascaded ACS structure 122 is
It is also used to determine codes with suppression lengths less than 9 (less than 256 states). There are two embodiments that implement this feature providing flexibility to operate with various constrained length convolutional encoders.

The preferred embodiment provides a state consistent with the trellis geometry, as in the in-place scheduling method (continuously overwriting past state metric decisions with state metric decisions from the current stage). stay. The trellis geometry shown in FIG. 5 repeats after a distance equal to the memory length (K-1).
The suppression length code is split into two phases,
Although it is not symmetrical, the sum of the lengths of the two phases (number of stages) is always equal to the memory length. In particular, for 128 states with K = 8, the radix-16 phase I calculation is determined in four trellis stages and the radix-8 phase II calculation is determined in three trellis stages. Similarly, for K = 7, phase I is calculated in four radix-16 stages and phase II is determined in two radix-4 stages. For K = 6, Phase I is calculated in four radix-16 stages and Phase II is determined in one radix-2 stage. For K = 5, Phase I is calculated in four radix-16 stages, and Phase II is unnecessary.

For example, to operate the cascaded ACS structure for a three stage situation in radix 8, the first ACS stage 150b is bypassed and the metric is
It flows through the data path circuits 160a, 160b, 162 and is effectively fed into the second ACS block 152b.
Similarly, for a radix-4, two-stage operation, data is effectively provided to the third ACS block 154b. For radix-2 operation, data is effectively provided to the last ACS block 156b. The bypass mechanism can be used within the ACS block, and any well-known method for digitally routing accumulated state metric data through the ACS block and reordering the hardware without any computational changes. It can be a switching system (eg, a multiplexer selected for bypass). In an alternative embodiment, the ACS block and the data path may be completely bypassed before the first ACS block required for computation. For example, in the case of radix 8, it is necessary to bypass the circuits 150b, 160a, 160b, and 162 shown in FIG.

An advantage of the preferred embodiment is that generating the state index or memory address is relatively linear. It should be understood that the ordering required for each constraint length case can also be expressed as for a more general ordering algorithm.
For example, a unique address generator can be designed for this embodiment. An alternative embodiment operates by always performing a radix-16 operation over the four stages of the trellis, assuming K> 4. However, address generation is more complicated.

Each ACS block 150b-156b in the cascade data path operates on a single trellis stage until all states have been processed. This means that the set of branch metrics 134 for a given stage is provided to the state metric update unit 120 for use in the associated ACS block. However, each butterfly operation of the ACS block requires a specific branch metric from the current data set, and the specific branch metric should be determined and selected. This branch metric selection depends on the trellis state index and the user-supplied code polynomial.

The preferred embodiment of the present invention uses the appropriate branch metrics in the ACS blocks 150b-156b.
To provide two equivalent hardware blocks of equal size and substantially identical construction. One branch metric (BM) selection unit 138 has the first two
And the other BM selection unit 138 operates the last two AC blocks 150b and 152b.
It acts on the S blocks 154b and 156b.

FIG. 9 shows the general structure of one such branch metric selection unit 138. Each BM selection unit 138 includes a state index generator 20 that provides a state index for the trellis.
2 and a branch metric index block 204. It should be understood that the state index generator 202 can be considered as part of the address / control block 136 shown in FIG. Branch metric index block 204 includes a first
BM indexes 206 and a second set of BM indexes 208 are generated, one for each ACS block 210,212. The second set of indexes 208 is
These indexes are stored in the BM selection multiplexer 216.
a is provided through a chain of delay registers 214 that arrive at a precise time (synchronized with the ACS calculation).
Delay 214 follows the delay through ACS cascades 210, 212 and the associated reordering hardware.

BM selection multiplexers 216a, 216
b uses the index from the branch metric index logic 204, and from the branch metric holding registers 218a, 218b, the correct BM from the set of branch metrics for the ACS stage.
Select One bit 220a, 2 of the index
20b is also supplied to the ACS blocks 210 and 212,
Indicates the sign of a particular branch metric. As a result, only half of the branch metrics are stored and forwarded. It should be understood that other convolutional coding techniques that require more branch metrics to be stored can also be used and are therefore also taken into account in the present invention.

The state index generator (one generator not shown from the remaining half-branch metric selection unit) is the same sequence representing the sequence of state indexes for the trellis states provided in the ACS cascade data path. Generate A second state index generator (not shown) provides a delayed start relative to first state index generator 202 to ensure proper time alignment with cascade stages 3,4. I do. The BM index block 204 generates each branch metric index by using each state index with a code polynomial (in a manner similar to how a convolution encoder generates output bits).

It should be understood that the state sequence order is different at each ACS cascade stage, so that additional operations must be performed at cascade stages 2, 3, and 4. Effectively each ACS
The correct state index for the stage is obtained from the incoming index. The incoming index is the first
Cascade stage sequence, but is directly related to the required index due to the reordering of the cascade structure following the trellis geometry. Therefore, the required next stage index is:
It can be obtained by shifting the incoming index with the appropriate attachment of 0 and 1 to fill the new empty slot (state metric column address). 0 and 1
Is determined by the known trellis connection between the state and the state index position in the trellis. By using the counting mechanism 222, an additional bit can be provided to determine when to use a different set of indices for any particular cascade stage. For example, 1 for cascade stage 2
Bits are attached, 2 bits are attached to stage 3, and 3 bits are attached to stage 4.

To further illustrate the state index generation of the present invention, referring back to the trellis of FIG. 5, the state index from stage 1 to stage 2 will be described in more detail. In connection with the properties of the trellis butterfly structure, only one state index per butterfly is needed. Also note that when referring to an index or node for a particular stage, that index or node references the left side of that stage.

The lower butterfly index of column C1 is initially generated for stage 1 which generates a sequence of eight indices: 8, 9, 10, 11, 12, 13, 14, 15. Generating a state index for stage 2 in the exact order of the butterfly observes the first four butterflies of stage 2 starting at the top of column C2. Here, column C2
The top node of each of these indices connects to the lower node of stage 1 which is that of the first four butterflies of stage 1. In detail, it is a butterfly having indices 8, 9, 10, and 11. By manipulating these indices directly, the first four indices for stage 2 are generated as follows. That is, those indexes are interpreted as 4-bit numbers, each index is shifted to the left, the most significant bit is dropped, and the least significant bit is set to “0”. This mimics the action of the convolutional encoder when at any of these nodes and given a "0" for the input bit. The resulting four indices are 0, 2, 4, and 6 in column C2. Therefore, an index for the first four butterflies of stage 2 is generated for the top node.

Referring now to the last four butterflies of stage 2 of FIG.
To the bottom nodes of the last four butterflies. For this reason, the index 12 from the stage 1,
13, 14, and 15 are shifted to the left, the most significant bit is dropped, and the least significant bit is set to "1". This generates the indices 9, 11, 13, 15 of column C2 by imitating a convolutional encoder and assuming that the input bits are equal to "1". The same process can be repeated for stage 3 and stage 4. The appended bits (least significant bits above) can indicate that they follow the set pattern. Specifically, it is a counting pattern from top to bottom. In the above example, the pattern is "0" for each of four consecutive butterflies.
Then, it is "1". For the next stage, this pattern will be "00", "01", "10", "11" for each of two consecutive butterflies.

Generating a branch metric state index is similar to generating a set of output bits for a given state of the convolutional encoder 44, for example, shown in FIG. However, for each branch metric index, some choice is required for the hypothetical input bits in addition to either the upper or lower state index of the butterfly. The input bit may simply be set to "0" when the state index is for the top butterfly node and "1" otherwise. Also, as can be seen from the above description, "0" is appended to reach the top node of the next stage, and "1" is appended to reach the bottom node of the next stage,
The input bits are the same as the least significant bits of the state index generated from the previous stage index.

Referring back to FIG. 4, if node 68a is the index with the most significant bit of "0" and node 68c is the index with the least significant bit of "0", then branches 70a and 70b are Branches 70c, 70d
Can be traversed with an input bit of "1". Further, as is well known, the output bits from branch 70a will be the same as those of branch 70d. Utilizing this property above, the butterfly's top index 68, provided that the hypothetical input bit is set to select the horizontal branch in each case.
Make either a or the bottom index 68b available to generate each branch metric index.

Referring again to FIG. 9, there are various embodiments that can perform the state sequence ordering operation described above. In the preferred embodiment, an optional code polynomial is provided, in which case the code polynomial register 224a
２224c can hold a polynomial. For each bit, each polynomial is logically ANDed with the state index obtained from above, and the resulting bits are exclusive ORed with each other to produce a one-bit branch metric
Form an index (similar to convolutional encoding). Alternatively, if only a certain number of different codes are implemented, hardware may be dedicated to those codes. This can be done by writing a logical expression for each code polynomial for each branch metric index (per bit) for the state index, counting index and fixed code polynomial. At this time, a compact expression can be generated by using logic synthesis. In either case, the same piece of hardware can handle codes with different suppression lengths by logically cutting off (eg, shifting, rotating) the unwanted upper address bits. It should be understood that the number of code polynomials can vary depending on the code rate. The embodiment shown in FIG.
Operating at a code rate of It should be further understood that the invention disclosed herein can be applied to multiple other code rates (eg, １ ／, ５, etc.).

Also, a single state index generator 20
2 can be fed into one branch metric index block that computes all four branch metric indices, each index passing through the required delay chain to each branch metric selection multiplexer. Sent. In addition, each ACS
A generator for the block can be used with an appropriate delay start time, thereby eliminating the delay register.

Referring back to FIG.
The unit 130 will be described in detail. The main function of the traceback unit 130 is to perform a traceback process for the partial pre-traceback determination stored in the traceback memory 132 during the ACS process described above. Traceback unit 130 also performs the function of accumulating and storing the decoded output data and acts as a buffer store for branch metrics on their route from DSP 140 to state metric update unit 120.

The traceback processing is performed for each new data
It consists of traversing backwards through path decision data following the path that helps the item to compose. Once sufficient steps of the traceback process have been achieved (convergence distance), the decoded output bits can be accumulated, derived from the same data. Basic traceback processing is well known. The heart of the traceback unit 130 is configured as a direct implementation of the Viterbi algorithm dictated in such a way that the path decision is stored in the memory 132. The traceback process of the present invention is unique in that it operates on different suppressed length codes and with different lengths of pretraceback. Also, the traceback unit 130 simultaneously provides decision storage, traceback, storage of decoded output and storage of branch metrics. What is needed for this various storage can be provided by one or more memory circuits.

For example, for traceback processing in a pretraceback of length 4 which is the most common situation, a 32-bit word, which will be described in detail below, is read from the traceback memory 132 and the state index shift register (non- 32) using the lower bit (least significant) of
Select 4 bits from the bit word. The four bits are
Because these items have already been traced backwards, they are the next pre-traceback items needed for and immediately part of the next state index. The MSB portion of this state index is used in conjunction with the variable cycle count to form a memory address.

When performing a traceback with a code having a pretraceback length of less than 4 or less, the hardware is configured to select only the required length from the memory words. State index
The number and position of the bits from the registers are adjusted accordingly. In this way, a number of codes are enabled.

Once the convergence length (survival path distance) has been passed through in the traceback process, the decoded output bits can be accumulated. The decoded output bits come directly from a selected portion of the memory word supplied to the state index. These bits come in groups of the same size as the pretraceback length, are accumulated in 32-bit registers, and are stored in traceback memory 132 as needed.

The pre-traceback decision bits coming from the SM update unit 120 are also accumulated in a 32-bit register before being written to the traceback memory 132. This information is stored in registers and in memory 132
, So that the parts of the constructed state index are available as pointers to the above information.

Traceback unit 130 controls all I / O operations and buffer management for traceback memory 132. Storing decoded output, storing branch metrics, and storing decision data all require circular buffers.

Referring to FIG. 10, a more detailed circuit block diagram of the traceback unit 130 is shown. In particular, FIG. 10 shows how traceback
FIG. 9 shows whether the unit stores the judgment data 124 (ie, the partial traceback data) received from the cascaded ACS 122 shown in FIG. I
/ O memory 132a outputs decoded output word 30
0 is stored, and the output word 300a is stored in the external D shown in FIG.
Included to supply to SP140. I / O memory 132a also stores incoming branch metric words 310 from DSP 140 and stores appropriate branch metric words 134 in state metric unit 120.
To supply. The traceback unit 130 also performs traceback processing, as well as fully control all of it, and provides address generation and FIFO management, as described in more detail below.

FIG. 10 shows the trace back unit 1
Multiplexers for 30 operations are shown.
Some of these are standard multiplexers that only select one of the illustrated input bit vectors as an output. However, other multiplexers are generalized multiplexers. These have a complex description and select an output from an input by following a custom selection of the input depending on the control bits to the multiplexer. That is, the multiplexers can treat all input vectors as each bit grouped together, and can select any of these bits in any order as the selected output bit. These are built by providing specific definitions for bit selection that depend on control bits within the VHDL process. This is then combined into a layered structure, usually a traditional multiplexer.

Traceback memory multiplexer 312 is a standard multiplexer, which determines the decision storage address 3 for presentation to traceback memory 132.
14 or the traceback address 316. The decision multiplexer 318 is a generalized multiplexer, and the decision multiplexers 318a and 318b
Select the decision input vector and some feedback bits so that the bits are placed in non-overlapping locations in the 32-bit register 320. As a result, the vectors are stacked in the order of arrival in the register 320 and stored in the memory 132 after the arrival of the 32-bit or four-vector set. I / O memory data multiplexer 322 is a standard multiplexer that selects output word 300 or branch metric word 310 for storage in I / O memory 132a.

Traceback multiplexer 324
Is a standard multiplexer that considers the 32-bit input vector 324a as eight vectors, each consisting of four bits, all in linear order. Multiplexer 324
Selects one of the 4-bit vectors (318a or 318b previously stored in a word) as output 324b. Each of the four bits 324b is a partial pretrace back path segment (i.e., one of the four bit decisions previously stored, but sometimes only one, two or three bits are used in the bypass operation described above). May be invalidated). Thereafter, the 4-bit partial pretraceback decision 324b is routed through standard multiplexers 326a, 326b, 326c.

Generalization multiplexer 328 has six input bits 328a, 328b for use in the next cycle to select the correct part of the traceback word.
Select the correct 3 bits from These six input bits 328a, 328b represent a portion of the current state index in the traceback process. The choice of multiplexer 328 depends on the suppression length of the convolutional code and how many stages of the trellis are being processed.

The generalized multiplexer 330 selects from the eight bits of the current state index 330a or 330b and selects a set of four bits that will be the decoded output bits. However, sometimes there are only three, two or one bits that are valid depending on the suppression length.

The generalized multiplexer 332 effectively stacks the decoded output bits 336 in the accumulation register 338. 32 valid bits are accumulated register 3
Once stored at 38, they are sent to I / O memory 132a via generalized multiplexer 340. Multiplexer 340 provides a valid decoded output bit from 35 bits of accumulation register
Select a bit. This choice depends on the suppression length and the number of trellis stages.

The generalized traceback address multiplexer 342 provides the next traceback word 324
Form the lower part of traceback address 342d for a. Multiplexer 342 selects the correct address bit from the 9-bit input from three different vectors 342a, 342b, 342c. Again, this choice depends on the suppression length and the number of stages. The complete traceback address is indicated by arrows 342a, 342
traceback pointer 342 shown as e
upper bit 342e and lower address bit 342 of f
Constructed by concatenating d. Pointer 324
f comes from a counter (not shown) in traceback controller 334 and provides backward movement in traceback memory 132 to implement traceback. A portion of traceback pointer bits 342a may also be used to form lower address bits 342d via multiplexer 342, as needed, for various suppressed length codes.

The traceback controller 334
It contains all the logic for controlling the traceback unit 130, and includes many counters, registers and the like needed to control the processing described above and to control address generation and memory data management. A multiplexer is provided.

Referring to FIG. 11, there is illustrated a method for a Viterbi decoding system according to the present invention.
In step 400, the plurality of ACS processes are performed via the cascaded ACS unit 122 as described above.
It is executed through the CS stage (for example, see FIG. 7).
Proceeding to step 410, the route judgment is
Are determined for all branches that enter one stage of the ACS 122 as a result of the ACS processing (see, for example, FIGS. 7 and 8). Proceeding to step 420, the path determination determines that the ACS
Accumulated during processing (for example, the
Attach to data path. For example, see FIG.

In step 430, the accumulated route judgment is sent to the subsequent ACS stage (see, for example, FIG. 8). This may include, for example, following the accumulated path decision based on the identified path decision of the subsequent ACS stage with A
This can be done by routing to the CS stage (e.g., the path decision bits of the following stage select the accumulated path from the preceding stage via a multiplexer circuit). This accumulated path decision is then combined with a subsequent ACS stage path decision via a multiplexer circuit (see, for example, FIG. 8).

At step 440, a set of cumulative path decisions across multiple ACS stages are provided to the traceback memory. For example, the cumulative path determination is based on the following ACS
Attached to the stage route judgment. The attached path decision is then stored in the widened ACS data path (see, for example, FIG. 8). After completing step 440, the process returns to step 400 so that the decoding process can be performed further.

While the present invention has been illustrated and described with reference to certain preferred embodiments or embodiments, it will be apparent to those skilled in the art that equivalent changes and modifications can be made by reading and understanding this specification and the accompanying drawings. . In particular, with respect to various functions performed by the aforementioned components (assemblies, devices, circuits, etc.), the terminology used to describe such components ("means")
), Unless specifically indicated to be otherwise structurally equivalent to the disclosed structure performing the functions in the illustrated exemplary embodiment of the invention, unless otherwise indicated. It is intended to correspond to any component that performs (ie, an equivalent function). Also, while certain features of the invention have been disclosed in only one of the embodiments, such features may be incorporated in other embodiments as desired.
It can also be combined with one or more other features as well as advantages for any given or specific application.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional wireless communication system.

FIG. 2 is a block diagram of a prior art convolution encoder and Viterbi decoder.

FIG. 3 is a schematic block diagram of a prior art convolution encoder.

FIG. 4 is a prior art Viterbi algorithm butterfly structure showing possible encoder transitions from a current state node to the next state node.

FIG. 5 is a 4 stage, 16 state trellis diagram for Viterbi decoding according to the present invention.

FIG. 6 is a schematic block diagram of a Viterbi decoder according to the present invention.

FIG. 7 is a schematic block diagram of a cascaded ACS unit for a Viterbi decoder according to the present invention.

FIG. 8 is an ACS for a Viterbi decoder according to the present invention.
FIG. 3 is a more detailed schematic block diagram of a unit.

FIG. 9 is a schematic block diagram of a branch metric selection unit for a Viterbi decoder according to the present invention.

FIG. 10 is a schematic block diagram of a traceback unit according to the present invention.

FIG. 11 is a flowchart illustrating a method for Viterbi decoding according to the present invention.

[Explanation of symbols]

 110 Viterbi decoder 120 State metric update unit 122 Cascaded ACS 124 Path decision value 125 Cumulative state metric (SM) 126 State metric memory 130 Traceback unit 132 Traceback memory 134 Branch metric 136 Address / control block 138 Branch・ Metric selection unit

Claims (14)

[Claims] 1. A decoder system, comprising: a state metric update unit including a state metric memory and a cascaded add / compare / select (ACS) unit, wherein said cascaded ACS unit comprises: A plurality of series-coupled ACS stages that perform a plurality of ACS operations with the memory, wherein one ACS stage identifies the plurality of path decisions and transfers the identified path decisions to a next ACS stage coupled thereto. A state metric update unit operable to communicate, and a traceback unit, storing a set of cumulative path decisions in a traceback memory associated therewith;
A traceback unit for performing a traceback on the set of cumulative path decisions, wherein the path decisions associated with the ACS stage and the next ACS stage are written to the traceback memory. A decoder system that accumulates as a set during the ACS processing before being accessed, thereby minimizing access to the traceback memory. 2. The method of claim 1, wherein the identified path decisions are accumulated as a set by sending the identified path decisions from the ACS stage to the next ACS stage during ACS processing. Decoder system. 3. The state metric updating unit comprises: A
The decoder system of claim 1, further comprising a branch metric selection unit operable to select a set of branch metric values and synchronize with the set of state metric values during CS processing. 4. The branch metric selection unit according to claim 3, further comprising a delay circuit for synchronizing said set of branch metrics with respect to a plurality of ACS stages. 5. The system of claim 3, further comprising a state index generator providing state metric memory addressing identifying state metric values for the stages of the cascaded ACS unit and a state index for branch metric selection. The described branch metric selection unit. 6. The branch metric selection unit according to claim 3, further comprising a set of code polynomial registers for storing a user-supplied code polynomial and enabling flexible processing for the plurality of convolution codes. 7. A branch metric index logic circuit receiving the user-supplied code polynomial, the branch metric index logic receiving a state index and a state counter to branch to a number of ACS stages. 7. The branch metric selection unit of claim 6, further comprising: a branch metric index logic circuit for generating a metric index and selecting a correct branch metric. 8. The system further comprising a DSP interface circuit operatively coupled to both the state metric update unit and the traceback unit, the DSP interface circuit operable to trace the branch metric from a DSP to the traceback unit. The decoding system of claim 1, wherein the decoding system communicates to the unit and sends decoded output bits from the traceback unit to the DSP. 9. The decoding system of claim 8, wherein said DSP performs branch metric calculations and depuncturing, thereby facilitating flexible operation of said decoding system. 10. The traceback unit according to claim 1, wherein the traceback processing is performed on a plurality of suppressed length codes. 11. A method for Viterbi decoding, comprising: performing an add / compare / select (ACS) process across a plurality of ACS stages; and determining a path decision during the ACS process. Accumulating the path judgment based on the ACS processing; sending the accumulated path judgment to an ACS stage subsequent to the plurality of ACS stages;
Providing trace back memory access to the memory. 12. The step of accumulating the route judgment,
The method according to claim 11, further comprising a step of expanding an ACS data path subjected to a path determination based on the ACS processing. 13. The step of sending the accumulated path decision comprises: routing the accumulated path decision of a subsequent ACS stage based on the identified path decision of a current ACS stage; Combining the determined path with the determined path of the subsequent ACS stage. 14. The method of providing the accumulated path decisions as a set to a traceback memory further comprising: attaching the accumulated path decisions to a set of path decisions associated with the subsequent ACS stage. The method of claim 11, comprising: