JP2001028534A - Semiconductor device drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce losses generated in a switch for an on gate by reducing a gate current value by an on gate signal, while current flowing to a GTO(gate turn-off thyristor) circuit flows in a negative direction. SOLUTION: A 1st bypass resistance 43 is connected in parallel with the switch 12a for an on gate of a wide on gate signal generation circuit 10. When an inter-gate-cathode voltage level discrimination circuit 41 discriminating the inter-gate-cathode voltage level of a GTO 7 discriminates that current flows to a diode 8 connected in opposite parallel manner to the GTP with a wide on gate command signal on, a 1st AND circuit 42 having an AND function, whose output becomes a signal making the wide on gate signal generation circuit off controls a switch for an on gate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element drive circuit for controlling on / off of a power semiconductor element such as a gate turn-off thyristor (hereinafter abbreviated as GTO).

[0002]

2. Description of the Related Art Generally, in an inverter device using a GTO as a main switching element, a load current flowing through a GTO circuit composed of the GTO and a diode connected in anti-parallel to the GTO is negative during a half cycle of the inverter output. It is necessary to supply an on-gate signal to the GTO at the point when the direction changes from the direction to the positive direction. In such a case, it is troublesome to discriminate the positive and negative directions of the load current flowing through the GTO at an arbitrary time. Therefore, in a conventional on-gate control device using a pulse transformer for the gate circuit, the high-frequency And one of the pulse transformers
The secondary side excitation circuit is driven to generate a continuous AC square wave on the secondary side of the pulse transformer, rectify it to form a DC on-gate signal, and apply it between the gate and cathode of the GTO. Was. Such a method of performing on-gate control by a continuous DC signal during a half cycle is called a wide pulse signal control method.

As a conventional semiconductor element driving circuit for performing such a wide pulse signal control method, for example, Japanese Patent Application Laid-Open No.
No. 137126 discloses a pulse transformer type on-gate control device. FIG. 15 is a circuit diagram showing an example of the above-mentioned conventional gate control device. A GTO is used as a main switching semiconductor element, and a wide pulse signal control method of a drive circuit (gate circuit) of the GTO is performed using a pulse transformer. Things.

In FIG. 1, reference numeral 10 denotes a wide on-gate signal generating circuit, and reference numeral 20 denotes a single pulse gate signal generating circuit for generating a single-pulse overdrive signal and an off-gate signal. 7 is a GTO used as a main switching element of the inverter device, 8 is a diode connected in parallel to the GTO 7 with a reverse polarity, 9a is a capacitor, and 9b is a resistor. The output terminals of the capacitor 9a, the resistor 9b, the wide on-gate signal generation circuit 10, and the single pulse gate signal generation circuit 20 are connected in parallel between the gate and cathode of the GTO 7, respectively. E is a DC power supply for supplying DC power to the pulse transformer type on-gate control device.

In the wide on-gate signal generating circuit 10, reference numeral 11 denotes a pulse transformer, and 12 and 13
Are transistors, 14 and 15 are rectifier diodes, 1
6 is a resistor. In the single pulse gate signal generation circuit 20, reference numeral 21 denotes a pulse transformer, reference numerals 22 and 23 denote transistors, reference numeral 24 denotes an off-gate thyristor, and reference numeral 25 denotes an overdrive thyristor.

Next, the operation will be described. The transistors 12 and 13 in the wide on-gate signal generating circuit 10 are alternately turned on and off at a high frequency for a required time to induce an AC rectangular wave voltage in the secondary winding of the pulse transformer 11. DC voltage obtained by the rectification is applied between the gate and cathode of the GTO 7 via the resistor 16. Since this DC voltage is a wide on-gate signal and is continuous for a half cycle of the inverter output, the direction of the load current flowing through the GTO arm may be either positive or negative, and it is not necessary to determine the direction of the load current.

Further, a single pulse gate signal generation circuit 20
In the above, the transistor 22 is turned on to generate an induced voltage in the secondary winding of the pulse transformer 21 with the polarity indicated by the symbol “図 示”, and this voltage is applied to the overdrive thyristor 2.
5 and applied as a single on-gate pulse (an over-drive on-gate signal) between the gate and cathode of the GTO 7. This on-gate pulse is a signal for overdriving GTO7. Next, the transistor 23 is turned on to generate an induced voltage in the secondary winding of the pulse transformer 21 with a polarity opposite to the above, and this voltage is applied to a single off-gate pulse (off-gate signal) via the off-gate thyristor 24. Is applied between the gate and the cathode of the GTO 7. This off-gate pulse is a signal for turning off GTO7.

FIG. 16 shows the GTO as described above.
7 shows a waveform of a gate signal applied to the reference numeral 7.
"A" in FIG. 16 is the wide on-gate signal. In addition, b is a signal input to the gate of the GTO 7, and FIG. 16B shows waveforms of the above-described on-gate signal for overdrive, and FIG. Further, FIG. 16C shows the output signal waveform of the pulse transformer type on-gate control device shown in FIG. 15 in which the signal waveforms a and b are combined.

As an on-gate control device (semiconductor element drive circuit), a circuit system as shown in FIG. 17 has been conventionally used. In the figure, 10 is a wide on-gate signal generating circuit, 20 is a single pulse gate signal generating circuit, 7 is a GTO used as a main switching element of an inverter device, and 8 is a diode connected in parallel to the GTO 7 with the opposite polarity. The output terminals of the wide-width on-gate signal generation circuit 10 and the single-pulse gate signal generation circuit 20 are GTO7
Are connected in parallel between the gate and the cathode.
The capacitor 9a and the resistor 9b used in the on-gate control device using the pulse transformer shown in FIG. 15 prevent voltage instability of the gate generation circuit due to the wiring inductance of the gate lead. Is not shown.

In the wide on-gate signal generating circuit 10, 12a is an on-gate switch, 16 is a resistor, 17 is a wide on-gate voltage source, and 18 is its smoothing capacitor. Further, in the single pulse gate signal generation circuit 20, 22a is an overdrive switch, 23a is an off-gate switch, 26 is a resistor, 27 is an overdrive voltage source, 28 is its smoothing capacitor, and 29 is off-gate. The voltage source 30, 30 is its smoothing capacitor. Reference numeral 3a denotes a command signal generation circuit that generates a command signal for controlling the on-gate switch 12a, the overdrive switch 22a, and the off-gate switch 23a in accordance with the GTO 7 on / off command.

Next, the operation will be described. Based on the command signal from the command signal generating circuit 3a, the on-gate switch 12a in the wide on-gate signal generating circuit 10 is turned on for a required time, and the DC voltage from the wide on-gate voltage source 17 is applied between the gate and cathode of the GTO7. Add to Since this DC voltage is a wide on-gate signal and is continuous for a half cycle of the inverter output, the direction of the load current flowing through the GTO arm may be either positive or negative, and it is not necessary to determine the direction of the load current.

The single pulse gate signal generation circuit 20
, The overdrive switch 22a is turned on, and the voltage of the overdrive voltage source 27 is applied between the gate and cathode of the GTO 7 as a single on-gate pulse. This on-gate pulse is an over-drive on-gate signal for over-driving GTO7. Next, the off-gate switch 23a is turned on,
The voltage of the off-gate voltage source 29 is applied between the gate and cathode of the GTO 7 as a single off-gate pulse. This off-gate pulse is an off-gate signal for turning off GTO7. Note that the signal waveform at this time is the same as when the pulse transformer shown in FIG. 16 is used.

Here, in such a wide pulse signal control method, a wide on-gate signal that is continuous for a half cycle of the inverter output is applied to the GTO 7, so that the power consumption of the gate circuit is large, and the gate control device is used. There was a disadvantage that it was large and expensive. FIG. 18 is a circuit diagram showing an improved example of an on-gate control device of such a conventional wide-width pulse signal control method using a pulse transformer disclosed in JP-A-60-137126.

In the figure, 7 is a GTO, 8 is a diode, 1 is a voltage level discriminating circuit for discriminating the voltage level between the anode and cathode of the GTO 7, 2 is a signal delay circuit, 3 is a gate control signal, 4 is an AND gate. The circuit 5 is a gate circuit. In the voltage level discriminating circuit 1, 1a is a constant voltage diode, 1b, 1c, 1f is a resistor, 1d is a transistor, 1e is its bias power supply, and 1g is a diode. In the signal delay circuit 2, 2a is an integrated circuit having an AND function, 2b and 2c are resistors, 2d is a capacitor, 2e, 2f, 2g, and 2h are diodes. Further, 5a and 5b in the gate circuit 5 are transistors,
c is a pulse transformer, and 5d is a gate power supply.

The voltage level determining circuit 1 determines whether the voltage level between the anode and the cathode of the GTO 7 is higher or lower than a predetermined level, and outputs a high (H) or low (L) level determination signal. That is, when the GTO 7 is in the off state and is higher than the anode-cathode voltage or the Zener voltage of the constant voltage diode 1a, the bias power supply 1e of the transistor 1d passes through the resistor 1b, the constant voltage diode 1a and the resistor 1c. A current flows, the transistor 1d is turned on, and an H-level output signal is obtained from both ends of the resistor 1f. Further, the GTO 7 is in the off state and the voltage between the anode and the cathode thereof is constant voltage diode 1a.
Is lower than the Zener voltage of the bias power supply 1e.
Thus, current flows through GTO7-diode 1g-resistor 1c, and no current flows through resistor 1b. Therefore, the transistor 1d is turned off, and an L-level output signal is obtained from both ends of the resistor 1f.

The signal delay circuit 2 receives the output signal of the voltage level discrimination circuit 1 and outputs the discrimination signal of each level with a predetermined delay different from each other. That is, the integrated circuit 2a having the AND function outputs an H or L level signal according to the level of the output signal level of the voltage level determination circuit 1 with respect to the threshold voltage set therein. When the signal input changes from the H level to the L level, the input signal at the H level is delayed by a predetermined time determined by the time constant of the resistor 2c and the capacitor 2d and output from the signal output terminal. When the signal input level changes from L level to H level, the resistance 2b
The input signal of L level is delayed by a predetermined time determined by the time constant of the capacitor 2d and output from the signal output terminal.

The gate control signal 3 is a signal for commanding the ON / OFF operation period of the GTO 7 provided from a command circuit (not shown). The AND circuit 4 controls the gate control signal 3 and the signal delay circuit 2. With the output signal as an input signal, the logical product of them is calculated. The gate circuit 5 includes a pulse transformer 5c in which the current of the primary winding is intermittent, and the GTO7 is supplied from the secondary winding of the pulse transformer 5c.
Is supplied with an on-gate signal. This gate circuit 5 corresponds to FIG.
5 is obtained by removing the off-gate thyristor 24 and the overdrive thyristor 25 from the gate signal generation circuit 20 shown in FIG. When a signal from the AND circuit 4 is received at the illustrated on-gate signal input terminal, the transistor 5a is turned on, an on-gate signal is output from the secondary side of the pulse transformer 5c, and is applied to the GTO 7 at the gate. When a signal from the AND circuit 4 is received at the off-gate signal input terminal, the transistor 5b is turned on, and an off-gate signal is output from the secondary side of the pulse transformer 5c and applied to the gate of the GTO 7.

Next, the operation will be described with reference to FIG. Here, FIG. 19 is a waveform diagram for explaining the operation of the on-gate control device of the narrow pulse signal control system using the pulse transformer shown in FIG. This V in FIG.
Shows an example of the anode-cathode voltage of the GTO 7, which is at the H level when the GTO 7 is off and at the L level when the GTO 7 is on.

FIG. 19 shows a signal output from the voltage level discriminating circuit 1 in response to the anode-cathode voltage V. This signal is also at the H level when the GTO 7 is off and at the L level when the GTO 7 is on. When the signal level changes from H to L, the signal delay circuit 2 receiving this signal outputs the H level signal for a predetermined time (in this example, approximately 1 signal).
0 μs), and when the signal changes from L to H, the L level signal is output with a delay of a predetermined time t (approximately 30 μs). By such a delay action, a signal having a waveform as shown in FIG. 19 is output from the signal delay circuit 2 and becomes one input of the AND circuit 4.

FIG. 19 shows a wide gate control signal which is given from a command circuit (not shown) to the other input terminal of the AND circuit 4 in correspondence with the cycle of the inverter output, and which is indicated by reference numeral 3 in FIG. . The H level of this signal is GTO7
The L level instructs the GTO 7 off period. When the H-level signal of this signal is applied to the AND circuit 4, the AND circuit 4 receiving the H-level signal from the signal delay circuit 2 at one input terminal outputs the signal shown in FIG. Is output to drive the gate circuit 5. The gate circuit 5 driven by the first pulse of this signal outputs the first pulse of the on-gate signal shown in FIG.
TO7 is turned on by the first pulse of this signal. As a result, the output signal of the voltage level discriminating circuit 1 goes low, and the output signal of the signal delay circuit 2 goes low approximately 10 μs later. Accordingly, the output signal of the AND circuit 4 also becomes L level. As a result, the H level signal of the signal becomes a narrow signal having a time width of about 10 μs, and the on-gate signal output from the gate circuit 5 to the GTO 7 is the same narrow signal. Becomes

Here, when the current flowing through the GTO 7 becomes equal to or less than the holding current of the GTO 7, the GTO 7
Turns off. The second H level in the signal of FIG. 19 shows an example generated by turning off the GTO7. When the signal level changes from L to H, the signal level changes from L to H with a delay of approximately 30 μs from the signal.
Changes to Therefore, the AND circuit 4 outputs the second signal
The second H-level signal is output, whereby the second on-gate signal of the signal is output from the gate circuit 5 to turn on the GTO 7. As a result, approximately 10μ
The signal becomes L level after s delay. Therefore, the signal and the signal of the second H level of the signal are also narrow signals having a time width of about 10 μs, similarly to the first H level.
The GTO 7 driven by this signal and turned on is turned off again if the anode current is equal to or less than the holding current of the GTO 7 when the on-gate signal is removed.

Thereafter, a third H-level on-gate signal is obtained by the same operation as when the second H-level signal of the above-described signal is obtained. Then, even if the anode current of the GTO 7 becomes equal to or smaller than the holding current, the GTO 7 continues the on operation as long as the on-gate signal is applied.

Next, in order to make it easier to understand the relationship between the above-mentioned signals and the on / off operation of the GTO 7, an example of a current flowing through the GTO circuit in the inverter device in relation to each of the above-mentioned signals is shown. 19 will be described. Among these currents, a current flowing in the positive direction is a current flowing through the GTO 7, and a current flowing in the negative direction is a current flowing through the diode 8 connected in anti-parallel to the GTO 7. The horizontal broken line h in the figure indicates the holding current level of GTO7.
Below this level, GTO 7 is turned off unless an on-gate signal is applied.

The off-gate control of the GTO 7 is performed by the same means as in the case of the conventional gate control device of a wide pulse signal control method using a pulse transformer. That is, this is performed by adding an off-gate signal such as the signal b in FIG. 16 to the base of the transistor 5b in FIG.

As can be understood from the above description of the operation, in the on-gate control apparatus according to the narrow pulse signal control method, the narrow on-gate signal of the signal shown in FIG. It is set so as to occur at intervals corresponding to a signal delay time t (here, 30 μs). That is, as compared with the conventional on-gate control device of a wide pulse signal control method using a pulse transformer, the power consumption for control is reduced to several times and the device is downsized.

[0026]

Since the conventional semiconductor element drive circuit (on-gate control device) is configured as described above, the on-gate control device of the wide pulse signal control system using the pulse transformer shown in FIG. Since a continuous wide on-gate signal is applied to the GTO 7 during a half cycle of the inverter output, the power consumption of the gate circuit is large, and the on-gate control device is large and expensive.

Similarly, the wide pulse signal control type on-gate control device shown in FIG. 17 also applies the continuous wide on-gate signal to the GTO during the half cycle of the inverter output.
7, the power consumption of the gate circuit is large, and the on-gate control device is large and expensive.

In the on-gate control device of the narrow pulse signal control method using the pulse transformer shown in FIG. 18, when the current flowing through the GTO circuit is in the negative direction, that is, when the current flows through the diode 8 connected in anti-parallel to the GTO 7, During the period during which the power supply flows, the on-gate signal is not output, so that the power consumption is reduced and the efficiency is increased.
Since it is necessary to monitor the anode-cathode voltage of the TO7, a withstand voltage against the DC voltage of the inverter is required during the OFF period of the GTO7.
Since the diode 1g in the inside needs a sufficient withstand voltage, the diode 1g becomes large. As a result, the voltage level discrimination circuit 1 itself becomes large and expensive, and the GTO7 is used to make the on-gate signal pulse-like. Therefore, there is a problem that the circuit is not suitable for a high withstand voltage circuit or a highly reliable circuit because the circuit system is expected to be used for the gate latch.

The present invention has been made to solve the above-mentioned problem, and is a simple circuit, in which a current flowing through a GTO circuit using an anode-emitter short type GTO is in a negative direction, that is, a GTO circuit is used. During the period when the current flows through the anti-parallel connected diode, the on-gate signal is not output, or the gate current value due to the on-gate signal is reduced to reduce the loss generated in the on-gate switch, thereby reducing the power consumption of the gate circuit. It is small and can be used for circuits where on-gate control devices (semiconductor element drive circuits) can be miniaturized and inexpensive, and high reliability is expected.
It is an object to obtain a semiconductor element drive circuit.

[0030]

A semiconductor device driving circuit according to the present invention has a wide on-gate signal generating circuit and a single pulse gate signal generating circuit, and a gate-to-cathode voltage level discriminating circuit detects a GTO signal. By determining whether the gate-cathode voltage level is higher or lower than a predetermined level,
Alternatively, a first AND circuit which outputs an L-level determination signal and receives an on-GTO wide on-gate command signal and an output of a gate-cathode voltage level determination circuit as input, and a wide on-gate command signal from a command signal generation circuit. Is turned on, and when the gate-cathode voltage level discriminating circuit determines that a current flows through the diode connected in anti-parallel to the GTO of the GTO circuit, the wide on-gate signal generating circuit is turned off, and the gate-cathode of the GTO circuit is turned off. When a negative direction period of a current flowing through a GTO circuit using an anode-emitter short type GTO is completed, a pull-up resistor for eliminating a voltage difference between a gate and a cathode is provided.
When the current flowing through the TO circuit is in the negative direction, that is, during the period when the current flows through the diode connected in anti-parallel to the GTO, the loss generated in the wide on-gate signal generating circuit can be reduced.

A semiconductor element driving circuit according to the present invention has a wide on-gate signal generation circuit and a single pulse gate signal generation circuit, and a gate-cathode voltage level discrimination circuit uses a GTO gate-cathode voltage level. Is determined to be higher or lower than a predetermined level, an H or L level determination signal is output, and a first ON GTO wide on-gate command signal and an output of a gate-cathode voltage level determination circuit are input. In the AND circuit, when the wide on-gate command signal from the command signal generation circuit is on and the gate-cathode voltage level discrimination circuit determines that a current flows through the diode connected in anti-parallel to the GTO of the GTO circuit, The on-gate signal generating circuit is turned off, and the first bypass is connected to the on-gate switch of the wide on-gate signal generating circuit. Connect anti in parallel, by bypassing the current flowing through the on-gate switch, GTO
When the current flowing through the circuit is in the negative direction, that is, during the period when the current flows through the diode connected in anti-parallel to the GTO, the loss generated in the wide on-gate signal generation circuit can be reduced.

The semiconductor element driving circuit according to the present invention comprises a wide on-gate signal generating circuit in which a first bypass resistor is connected in parallel to an on-gate switch, and a GTO circuit G circuit.
A gate current cutoff switch that is turned on / off in synchronization with the wide on-gate command signal from the command signal generation circuit is connected in series with the gate of the TO, so that the current flowing through the GTO circuit is in the negative direction, The period during which a current flows through the diode connected in anti-parallel to the GTO can reduce the loss generated in the wide on-gate signal generation circuit.

The semiconductor device driving circuit according to the present invention is connected in parallel to the on-gate switch of the wide on-gate signal generating circuit, and bypasses the current flowing therethrough.
A first bypass switch that is turned on and off in synchronization with the wide on-gate command signal from the command signal generation circuit is connected in series to the bypass resistor of the GTO circuit. The period during which the current flows through the diodes connected in anti-parallel is to reduce the loss generated in the wide on-gate signal generation circuit.

The semiconductor element driving circuit according to the present invention is characterized in that the first element is connected in parallel to the on-gate switch of the wide on-gate signal generation circuit and is connected in series to the first bypass resistor.
Of the bypass switch is turned on when the wide on-gate command signal, which is one input, is turned on and the first input, which is the other input, is turned on.
When the output of the AND circuit is an output for turning off the wide on-gate signal generation circuit, the GTO circuit is controlled by a second AND circuit having an AND function of outputting an ON signal to the first bypass switch. In the case where the current flowing in the negative direction, that is, the period in which the current flows in the diode connected in anti-parallel to the GTO, the loss generated in the wide on-gate signal generation circuit can be reduced.

The semiconductor element driving circuit according to the present invention has a wide on-gate signal generating circuit and a single pulse gate signal generating circuit, and the gate-cathode voltage level discriminating circuit determines the gate-cathode voltage level of the GTO. Is determined to be higher or lower than a predetermined level, an H or L level determination signal is output, and a first ON GTO wide on-gate command signal and an output of a gate-cathode voltage level determination circuit are input. In the AND circuit, when the wide on-gate command signal from the command signal generating circuit is on and the gate-cathode voltage level discriminating circuit determines that a current flows through the diode connected in anti-parallel to the GTO of the GTO circuit, The on-gate signal generation circuit is turned off, and the series connection of the second bypass resistor and the second bypass switch is connected to G The second bypass switch is connected in parallel between the gate and the cathode of O. When the wide ON gate command signal as one input is ON and the output of the first AND circuit as the other input is wide, If the signal turns off the on-gate signal generation circuit, the signal is controlled by a second AND circuit having an AND function for outputting an ON signal to the second bypass switch, thereby realizing the GT.
When the current flowing in the O circuit is in the negative direction, that is, during the period when the current flows in the diode connected in anti-parallel to the GTO, the loss generated in the wide on-gate signal generation circuit can be reduced.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a semiconductor element drive circuit according to Embodiment 1 of the present invention. In the figure, reference numeral 7 denotes a semiconductor element that is driven and controlled by the semiconductor element drive circuit. Here, a GTO used as a main switching element of an inverter device is illustrated. 8 is this G
A diode connected in parallel with the reverse polarity to TO7,
The GTO 7 and the diode 8 constitute a GTO circuit. Reference numeral 10 denotes a wide on-gate signal generating circuit for generating a wide on-gate signal applied between the gate and cathode of the GTO 7. Reference numeral 20 denotes a single pulse gate signal generation circuit that generates an overdrive signal applied between the gate and the cathode of the GTO 7 and an off gate signal.

In the wide on-gate signal generating circuit 10, reference numeral 17 denotes a wide on-gate voltage source for generating a DC voltage for a wide on-gate signal. It is a smoothing capacitor. Reference numeral 12a denotes an on-gate switch which is turned on for a required time to generate a wide on-gate signal from the DC voltage from the wide on-gate voltage source 17, and 16 denotes this on-gate switch 12a, the wide on-gate voltage source 17, 18 is a resistor connected between the resistor 18.

The single pulse gate signal generation circuit 20
In the figure, 27 is an overdrive voltage source for generating a DC voltage for an overdrive signal by a single pulse, 28 is a smoothing capacitor for smoothing the DC voltage from the overdrive voltage source 27, and 22a is an overdrive capacitor. An overdrive switch 26 for turning on / off the DC voltage from the drive voltage source 27 to generate a single-pulse overdrive signal. The overdrive switch 26a includes the overdrive switch 22a, the overdrive voltage source 27, and a smoothing capacitor. 28. Reference numeral 29 denotes an off-gate voltage source for generating a DC voltage for an off-gate signal by a single pulse, reference numeral 30 denotes a smoothing capacitor for smoothing the DC voltage from the off-gate voltage source 29, and reference numeral 23a denotes a signal from the off-gate voltage source 29. An off-gate switch that turns on and off a DC voltage and generates a single-pulse off-gate signal. Reference numeral 50 denotes an overdrive signal generation circuit including the overdrive switch 22a, the resistor 26, the overdrive voltage source 27, and the smoothing capacitor 28. Reference numeral 60 denotes the off-gate switch 23a, the off-gate voltage source 29,
This is an off-gate signal generation circuit including a smoothing capacitor 30.

Reference numeral 3a denotes a command signal generation circuit for generating a command signal for controlling the on-gate switch 12a, the overdrive switch 22a, and the off-gate switch 23a in accordance with the GTO 7 on / off command. Reference numeral 41 denotes a gate-cathode voltage level discriminating circuit which monitors the voltage between the gate and cathode of the GTO 7 and discriminates whether the voltage is higher or lower than a predetermined level and outputs an H or L level discrimination signal. Reference numeral 42 designates an input of a wide ON gate command signal of ON GTO from the command signal generating circuit 3a and an output of the gate-cathode voltage level discriminating circuit 41, and when the wide ON gate command signal is ON and the GTO circuit GTO 7 When the gate-cathode voltage level discriminating circuit 41 determines that a current flows through the diode 8 connected in anti-parallel, it has an AND function of outputting a signal for turning off the on-gate switch 12a of the wide on-gate signal generating circuit 10. First AND circuit 4
2. Reference numeral 9c denotes a pull-up resistor connected in parallel between the gate and the cathode to eliminate the voltage difference between the gate and the cathode when the negative period of the current flowing through the GTO circuit ends.

Next, the operation will be described. Here, FIG. 2 is a waveform diagram for explaining the operation of the semiconductor element drive circuit according to the first embodiment. FIG. 2A shows an example of a current waveform of the GTO circuit. A broken line portion in the current waveform a is a current flowing through another GTO circuit of the inverter not shown in the figure. The current on the positive side of the current waveform a indicates that GTO7 of the GTO circuit is passing an inverter current from the anode to the cathode, and the negative side is GTO7.
This indicates that the diode 8 of the TO circuit is passing an inverter current from the anode to the cathode. Also, b, c, and d in FIG. 2 are on / off command signals for the gate signal generation circuits corresponding to the command signals output from the command signal generation circuit 3a in FIG. The command signal b is a wide on-gate command signal that controls the on-gate switch 12a via the first AND circuit 42 and operates the wide on-gate signal generation circuit 10. The command signal c controls the overdrive switch 22a to generate a single pulse of the overdrive signal generation circuit 50 of the GTO 7.
Is an overdrive command signal for operating the. The command signal d is an off-gate command signal that controls the off-gate switch 23a to operate the off-gate signal generation circuit 60. The on-gate switch 12 shown in FIG.
a, the overdrive switch 22a, and the off-gate switch 23a all operate low active.

At time t0 shown in FIG. 2, wide on-gate command signal b for operating the GTO circuit is at the H level. At that time, the overdrive command signal c is also H
Therefore, the overdrive signal generation circuit 50 is turned off, and the off gate signal d is at the L level, so that the off gate signal generation circuit 60 is turned on.
Therefore, the gate-cathode voltage e of the GTO 7 shown in FIG. 2 is reverse-biased by the DC voltage from the off-gate voltage source 29, and becomes lower than the threshold voltage h. Therefore, the output f of the gate-cathode voltage level discriminating circuit 41 becomes H level, so that the first AND circuit 42
Becomes the H level. This first AND circuit 42
Switch 12 for the on-gate by the H level of the output g of
is controlled, and the wide on-gate signal generation circuit 10 is turned off.

At time t1, wide on-gate signal b for operating the GTO circuit and overdrive command signal c attain L level. Overdrive command signal c
Goes low, the overdrive signal generation circuit 5
0 is turned on, and at that time, the off-gate command signal d becomes H level, so that the off-gate signal generation circuit 60 is turned off. In the GTO circuit, as shown in FIG.
, The gate-cathode voltage e of the GTO 7 is forward-biased in the forward direction by the forward ON voltage of the PN junction between the gate and the cathode, and is higher than the threshold voltage h. Become. Therefore, the gate
The output f of the inter-cathode voltage level discriminating circuit 41 becomes L level, and the output g of the first AND circuit 42 becomes L level. The on-gate switch 12a is controlled by the L level of the output g of the first AND circuit 42, and the wide on-gate signal generation circuit 10 is turned on.

At time t2, the wide on-gate command signal b for operating the GTO circuit is at L level, but the overdrive command signal c is at H level. When the overdrive command signal c goes high, the overdrive signal generation circuit 50 turns off. Since the off-gate command signal d is at the H level, the off-gate signal generation circuit 60
Turns off. At this time, in the GTO circuit, since a current flows to the GTO 7 side, the gate-cathode voltage e of the GTO 7 is also forward-biased in the forward direction by the forward ON voltage of the gate-cathode PN junction. Therefore, the voltage is higher than the threshold voltage h. Therefore, the output f of the gate-cathode voltage level determination circuit 41 becomes L level, and the output g of the first AND circuit 42 becomes L level. The wide on-gate signal generation circuit 10 is turned on by the L level of the output g of the first AND circuit 42, and the gate current I that keeps the GTO 7 on is maintained.
g is supplied to the gate of GTO7.

At time t3, wide on-gate command signal b for operating the GTO circuit attains H level, and overdrive command signal c maintains H level. The overdrive signal generating circuit 50 is turned off by the H level of the overdrive command signal c. Also,
Since the off-gate command signal d is at L level, the off-gate signal generation circuit 60 is turned on. Therefore, since the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29, it becomes lower than the threshold voltage h, and the GTO 7 enters an off operation. As a result, the output f of the gate-cathode voltage level determination circuit 41 is at the H level, and the output g of the first AND circuit 42 is at the H level.
Level, the wide on-gate signal generation circuit 10 turns off.

The period from time t3 to time t4 is GTO
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the gate electrode 7. At the time t4, the turning off operation of the GTO 7 is completed.
Flows only a small current enough to maintain the off state of the GTO 7.

At time t5, the current a of the GTO circuit is in the positive direction. Therefore, before time t7 when the direction of this current a changes in the negative direction, the current a is again changed from time t1 to time t3.
The same operation is repeated. Near time t7, the output f of the gate-cathode voltage level determination circuit 41 becomes H level at time t7 with a slight time difference after the current starts flowing through the diode 8. The reason for this is that the voltage near the crossing of the current on the GTO 7 side and the current on the diode 8 side of the GTO circuit may become unstable. This is because it is better to set the voltage to a minus voltage at which the forward ON voltage of the diode 8 is established after the current starts flowing. In practice, it is better to provide the threshold voltage h with hysteresis. Therefore, at this time t7, the output g of the first AND circuit 42 becomes H
Level, and the wide on-gate signal generation circuit 10 turns off.

GTO 7 gate until time t8
Regarding the voltage e between the cathodes, the off-gate switch 2
If 3a is an ideal switch, the on-gate switch 1
Since the gate 2a is disconnected, the voltage between the gate and the cathode of the GTO 7 is pulled up to the cathode potential by the pull-up resistor 9c. However, when the voltage is pulled up to the cathode potential and the wide on-gate signal generation circuit 10 is turned on again, The current flowing in the anode short section of the GTO 7 causes the forward ON voltage of the anode short section to increase, and the operation of turning off the wide ON gate signal generation circuit 10 is repeated again. The gate-cathode voltage e of the GTO 7 becomes equal to the time t8. During this period, the threshold voltage h is fixed.

During the period from time t8 to time t9, GT
This is a period during which the carrier between the gate and the cathode is removed to turn off O7. At time t9, the off operation of GTO7 is completed, and thereafter, until time t10, the gate current Ig only maintains the off state of GTO7. Only a very small current is flowing.

At time t10, the current a of the GTO circuit
Is in the negative direction, but from time t10 to time t1
At 1, the same operation is repeated again from time t1 to time t2. At time t10, the overdrive command signal c of the GTO 7 is set to the L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e is fixed to the threshold voltage h. During this period, the time t at which the wide on-gate command signal b becomes H level
Continue up to 12. The reason why the gate-cathode voltage e is fixed to the threshold voltage h is that the gate-cathode voltage level discriminating circuit 41 determines the voltage by, for example, using an FET or the like for the off-gate switch 23a. This is to prevent an operation delay corresponding to a time constant with the pull-up resistor 9c generated by the parasitic capacitance at both ends.

During the period from time t12 to time t13,
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the GTO 7. At time t13, the off operation of the GTO 7 is completed. Until the time t14, the gate current Ig only maintains the off state of the GTO 7 Only a very small current flows.

At time t14, the current a of the GTO circuit
Is in the negative direction, and during the period from time t14 to time t15, the same operation as that from time t10 to time t11 is repeated. At time t14, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed, for example, by using an FET or the like for the off-gate switch 23a, and using the time constant of the pull-up resistor 9c generated by the parasitic capacitance at both ends. GTO in order not to be delayed
7, the overdrive signal generation circuit 50 is turned on by setting the overdrive command signal c to L level, and the gate-cathode voltage e is fixed at the threshold voltage h until time t16.

At time t16, the direction of the current a of the GTO circuit is switched from negative to positive. By setting the threshold voltage h of the gate-cathode voltage level discriminating circuit 41 to a negative value, the gate-cathode voltage The output f of the level discriminating circuit 41 can have a slight time difference before the current stops flowing through the diode 8. At time t16, the output f of the gate-cathode voltage level discriminating circuit 41 becomes L level, the first AND Circuit 4
2 is set to the L level, the wide on-gate signal generation circuit 10 is turned on, and the GTO 7 waits as an on-state gate signal for flowing a positive current.
Therefore, during the period from time t16 to time t17, GTO
7 turns on.

During the period from time t17 to time t18,
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the GTO 7, and at the time t18, the turning off of the GTO 7 is completed. Not.

As described above, according to the first embodiment, when the current flowing through the GTO circuit is in the negative direction,
During the period in which the current flows through the diode 8 connected in anti-parallel to the TO 7, the loss generated in the wide on-gate signal generation circuit 10 can be eliminated, so that the conventional GTO pulse transformer type on-gate shown in FIG. Since a wide on-gate signal that is continuous for half a cycle of the inverter output in the control device is applied to the GTO 7, the problem that the power consumption of the gate circuit is large and the gate control device becomes large and expensive can be solved. Similarly, the conventional on-gate control device shown in FIG. 17 also applies a wide on-gate signal to the GTO 7 that is continuous for a half cycle of the inverter output. It is possible to solve the problem that the control device is large and expensive. In order to monitor the voltage between the anode and the cathode in the voltage level determination circuit of the conventional narrow pulse signal control type transformer on-gate control device shown in FIG. 18, a withstand voltage against the DC voltage of the inverter is required during the GTO off period. In particular, it is possible to obtain an effect that the problem that the diode 1g in the discrimination circuit 1 requires a withstand voltage can be solved, and an ideal circuit having the stability of the wide-type wide-on-gate signal generation circuit can be obtained. realizable.

Embodiment 2 Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a configuration of a semiconductor element drive circuit according to Embodiment 2 of the present invention. In the figure, 7 is a GTO as a semiconductor element, and 8 is this GTO.
It is a diode that forms a GTO circuit with TO7.
Reference numeral 10 denotes a wide on-gate signal generating circuit including an on-gate switch 12a, a resistor 16, a wide on-gate voltage source 17, and a smoothing capacitor 18. Reference numeral 20 denotes an overdrive signal generation circuit 50 including an overdrive switch 22a, a resistor 26, an overdrive voltage source 27, and a smoothing capacitor 28; This is a single pulse gate signal generation circuit including a generation circuit 60.

Reference numeral 3a denotes a command signal generation circuit for generating a command signal corresponding to the GTO 7 on / off command.
Reference numeral 1 denotes a gate-cathode voltage level discriminating circuit for discriminating whether the voltage between the gate and cathode of the GTO 7 is higher or lower than a predetermined level. Reference numeral 42 denotes a wide on-gate command signal that is turned on, and current flows through the diode 8 of the GTO circuit. Is a first AND circuit for turning off the on-gate switch 12a when it is detected that the current flows. These components are the same as those in the first embodiment shown in FIG.

Reference numeral 43 denotes a first bypass resistor connected in parallel to the on-gate switch 12a. After the on-gate switch 12a is turned off, an on-gate voltage source is connected by a series connection of the resistor 16 and the first bypass resistor 43. 17 to allow a very small current to flow through the gate of the GTO 7. In the semiconductor element drive circuit of the second embodiment, the gate-cathode of the GTO 7 is used to eliminate the voltage difference between the gate-cathode of the GTO 7 when the negative direction period of the current flowing in the GTO circuit ends. Are not connected in parallel. As described above, the semiconductor element drive circuit of the second embodiment differs from that of the first embodiment in that the pull-up resistor 9c is omitted and the first bypass resistor 43 is connected in parallel to the on-gate switch 12a. Are different.

Next, the operation will be described. Here, FIG. 4 is a waveform diagram for explaining the operation of the semiconductor element drive circuit according to the second embodiment. FIG. 4A shows an example of the current waveform of the GTO circuit. A broken line portion in the current waveform a is a current flowing through another GTO circuit of the inverter not shown in the figure. The positive side of the current a is GT
The GTO 7 of the O circuit indicates that an inverter current is flowing from the anode to the cathode, and the negative side indicates that the diode 8 of the GTO circuit is flowing an inverter current from the anode to the cathode. 4B, 4C, and 4D are ON / OFF command signals of the respective gate signal generating circuits sent from the command signal generating circuit 3a of FIG. 3, and b is a source for operating the wide ON gate signal generating circuit 10. GTO7 by a single pulse
Is an overdrive command signal for operating the overdrive signal generation circuit 50, and d is an off-gate signal generation circuit 6.
0 is an off-gate command signal for operating 0. FIG.
The on-gate switch 12a, over-drive switch 22a and off-gate switch 23a shown in FIG.

At time t0 in FIG. 4, wide on-gate command signal b is at H level and overdrive command signal c
Is also at the H level, and the overdrive signal generation circuit 50
Is turned off. At this time, since the off-gate command signal d is at the L level, the off-gate signal generation circuit 60 is turned on. Therefore, the gate-cathode voltage e of GTO7
Is reverse-biased by the DC voltage of the off-gate voltage source 29, and becomes lower than the threshold voltage h. Therefore, the output f of the gate-cathode voltage level determination circuit 41 becomes H level, and the output g of the first AND circuit 42 becomes H level. As a result, the on-gate switch 12a is turned off, and the wide on-gate signal generation circuit 1 is turned off.
0 indicates an off operation.

At time t1, the wide on-gate command signal b and the overdrive command signal c become L level,
By the L level of the overdrive command signal c,
The overdrive signal generation circuit 50 turns on. At that time, the off-gate signal command d goes high, so that the off-gate signal generation circuit 60 is turned off. In the GTO circuit, as shown in FIG. 2A, a current flows to the GTO 7 side.
The gate-cathode voltage e of the GTO 7 is forward-biased in the forward direction by the forward ON voltage of the PN junction between the gate and the cathode, and becomes higher than the threshold voltage h. Therefore, the output f of the gate-cathode voltage level determination circuit 41 becomes L level, and the output g of the first AND circuit 42 becomes L level. As a result, the on-gate switch 12a is turned on, and the wide on-gate signal generation circuit 10 is turned on.

At time t2, the wide on-gate command signal b is at L level, but the overdrive command signal c
Becomes H level. When the overdrive command signal c goes high, the overdrive signal generation circuit 50 turns off. Since the off-gate command signal d remains at the H level, the off-gate signal generation circuit 60 is off. At this time, in the GTO circuit, since a current flows to the GTO 7 side, the gate-cathode voltage e of the GTO 7 is also forward-biased in the forward direction by the forward ON voltage of the PN junction between the gate and cathode during this period. As a result, the voltage becomes higher than the threshold voltage h. Therefore, the output f of the gate-cathode voltage level discriminating circuit 41 and the output g of the first AND circuit 42 both become L level. This first
The wide on-gate signal generation circuit 10 is turned on by the L level of the output g of the AND circuit 42, and the gate current Ig for maintaining the GTO 7 on is supplied to the gate of the GTO 7.

At time t3, wide on-gate command signal b attains H level, and overdrive command signal c
Maintain the H level as it is. Due to the H level of the overdrive command signal c, the overdrive signal generation circuit 50 remains off. Further, since the off-gate command signal d becomes L level, the off-gate signal generation circuit 60 is turned on. Therefore, the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29, becomes lower than the threshold voltage h, and the GTO 7 enters an off operation. As a result, the output f of the gate-cathode voltage level determination circuit 41 becomes H level, the output g of the first AND circuit 42 becomes H level, and the wide on-gate signal generation circuit 10 turns off.

The period from time t3 to time t4 is GTO
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the gate electrode 7. At the time t4, the turning off operation of the GTO 7 is completed.
Flows only a small current enough to maintain the off state of the GTO 7.

At time t5, since the current a of the GTO circuit is in the positive direction, the same operation as from time 1 to time t3 is repeated again before reaching time t7. Near the time t7, the gate-cathode voltage level determining circuit 41
Has a slight time difference after the current starts to flow through the diode 8, and goes high at time t7. The reason for this is that the threshold voltage h may actually become unstable near the intersection of the current on the GTO 7 side and the current on the diode 8 side of the GTO circuit. This is because it is better to set the voltage to a minus voltage at which the forward ON voltage of the diode 8 is established after the current starts flowing. Therefore, at time t7, the output g of the first AND circuit 42 becomes H level, and the wide on-gate signal generation circuit 10 turns off.

Next, the operation until time t8 will be described. Here, FIG. 5 is an explanatory diagram showing an internal model and a circuit model of the GTO, wherein a1 shows an internal model of the heavy metal-doped GTO, and a2 shows a circuit model of the heavy metal-doped GTO. In the drawing, b1 indicates an internal model of the anode-emitter short GTO, and b2 indicates a circuit model of the anode-emitter short GTO. FIG. 6 is a circuit diagram when a current flows through the diode 8 of the GTO circuit to generate a forward ON voltage. In FIG. 6, reference numeral 7a denotes a diode parasitic between the anode and the gate of the anode-emitter short type GTO 7, 8a denotes a forward ON voltage generated when a current flows through the diode 8, and 23b denotes an off-gate switch 2.
3a is a parasitic capacitance.

Since the present invention particularly relates to an anode-emitter short type GTO, its internal model is as shown by b1 in FIG.
Since a diode is parasitically connected between the gate and the gate G in anti-parallel, the circuit diagram model is represented as b2 in FIG.
Here, with reference to the anode A of the GTO 7, the voltage value of the forward ON voltage 8a of the diode 8 is VF1, the voltage value of the on-gate voltage source 17 is V2, and the diode 7a Is VF3, the resistance of the resistor 16 is R1, and the resistance of the first bypass resistor 43 is R2, Ig = (V
A current determined by (F1 + V2-VF3) / (R1 + R2) flows from the gate of GTO7 to the anode. This current is lower than the normal gate current Ig = V2 / R1, for example, 1 /
Since it is set to about 100, the generation loss of the wide on-gate signal generation circuit 10 during this period is minimized. Than this,
-(VF1-VF3) is generated for the gate-cathode voltage e until the time t8.

In the second embodiment, as in the case of the first embodiment, wide on-gate signal generating circuit 1
The reason why 0 is not completely turned off when a current flows to the diode 8 side of the GTO circuit is as follows. That is, the off-gate switch 23a shown in FIG.
When ET or the like is used, this off-gate switch 23
The parasitic capacitance 23b at both ends of the terminal a is equal to the forward on-voltage 8a generated when a current flows through the diode 8 from the voltage charged to the voltage of the off-gate voltage source 29 while the off-gate signal generating circuit 60 is on. This is because the gate voltage of the GTO 7 remains negative unless it is recharged. Therefore, it is more preferable to charge the GTO 7 from the voltage of the on-gate voltage source 29 than to charge from the cathode potential as in the first embodiment. Is not delayed.

During the period from time t8 to time t9, GT
This is a period during which the carrier between the gate and the cathode is removed to turn off O7. At time t9, the off operation of GTO7 is completed, and thereafter, until time t10, the gate current Ig only maintains the off state of GTO7. Only a very small current is flowing.

At time t11, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3).

The period from time t12 to time t13 is
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the GTO 7. At time t13, the turning off of the GTO 7 is completed. Only a very small current is flowing.

At time t14, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3).

At time t16, the direction of the current a of the GTO circuit is switched from negative to positive. The output f of the level discriminating circuit 41 can have a slight time difference before the current stops flowing through the diode 8. At time t16, the output f of the gate-cathode voltage level discriminating circuit 41 becomes L level, the first AND Circuit 4
2 is set to the L level, the wide on-gate signal generation circuit 10 is turned on, and waits as an on-state gate signal for flowing the positive current of the GTO 7.
For example, when an FET or the like is used as the off-gate switch 23a, the capacitor 23b parasitic at both ends of the switch is rapidly charged. Therefore, during the period from time t16 to time t17, the GTO 7 is turned on.

During the period from time t17 to time t18,
This is a period in which the carrier between the gate and the cathode is removed in order to turn off the GTO 7, and the turning off of the GTO 7 is completed at time t <b> 18, and thereafter, the gate current Ig flows only a small current enough to maintain the off state of the GTO 7. Absent.

As described above, also in the second embodiment, when the current flowing through the GTO circuit is in the negative direction,
During the period in which the current flows through the diode 8 connected in anti-parallel to the TO 7, the loss generated in the wide on-gate signal generation circuit 10 can be eliminated, so that the conventional GTO pulse transformer type on-gate shown in FIG. Since a wide on-gate signal that is continuous for half a cycle of the inverter output in the control device is applied to the GTO 7, the problem that the power consumption of the gate circuit is large and the gate control device becomes large and expensive can be solved. Similarly, the conventional on-gate control device shown in FIG. 17 also applies a wide on-gate signal to the GTO 7 that is continuous for a half cycle of the inverter output. It is possible to solve the problem that the control device is large and expensive. In the conventional voltage level discriminating circuit using the on-gate control device of the narrow pulse signal control method shown in FIG. 18, a withstand voltage against the DC voltage of the inverter is required during the GTO off period in order to monitor the voltage between the anode and the cathode. In particular, it is possible to solve the problem that the problem that the diode 1g in the discrimination circuit 1 requires a withstand voltage can be solved, and the ideal circuit having the stability of the wide-type wide-on-gate signal generation circuit can be obtained. Can be realized.

Embodiment 3 Next, a third embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing a configuration of a semiconductor element driving circuit according to a third embodiment of the present invention. Parts corresponding to those in the second embodiment are denoted by the same reference numerals as in FIG. I do. In the semiconductor element driving circuit according to the third embodiment, the first bypass resistor 43 is connected in parallel to the on-gate switch 12a, as in the second embodiment, and the gate-cathode voltage level determination circuit 41 The gate-cathode voltage of the GTO 7 is monitored, and when a current flows through the diode 8 connected in anti-parallel to the GTO 7 of the GTO circuit when the wide ON gate command signal is ON, the wide ON gate signal is output by the output of the first AND circuit 42. After the on-gate switch 12a of the generating circuit 10 is turned off and the on-gate switch 12a is turned off, a minute current flows to the gate of the GTO 7 through the series connection of the resistor 16 and the first bypass resistor 43, and the anode-emitter short circuit occurs. During the period when current flows through the diode 8 antiparallel to the GTO 7 of the GTO circuit using the Is a circuit that prevents operating the on-gate signal generating circuit 10, the on-gate switch 12a, and is further connected switches in series.

In the figure, reference numeral 44 denotes a gate current cutoff switch connected in series to the on-gate switch 12a, which is turned on / off in synchronization with a wide on-gate command signal from the command signal generating circuit 3a, and the GTO 7 is turned off. During this period, the current flowing from the wide on-gate signal generation circuit 10 to the off-gate voltage source 29 to turn on the off-gate switch 23a is cut off. The semiconductor element drive circuit according to the third embodiment is different from the second embodiment in that the gate current cutoff switch 44 is provided.

Next, the operation will be described. Here, the operation waveforms of the semiconductor element drive circuit according to the third embodiment are the same as those shown in FIG. FIG. 4A shows an example of a current waveform of the GTO circuit. A broken line portion in the current waveform a represents a current flowing in another GTO circuit of the inverter not shown in the figure, and a positive side portion is a GTO circuit. GTO7
The negative part indicates that the diodes 8 of the GTO circuit are each carrying an inverter current. FIG.
c and d are on / off command signals of each gate signal generation circuit from the command signal generation circuit 3a of FIG. 7, b is a wide on-gate command signal, c is an overdrive command signal, and d is an off-gate command signal. Also, the on-gate switch 12a and the overdrive switch 22 shown in FIG.
a, the off-gate switch 23a, and the gate current cut-off switch 44 all operate in a low active state.

At time t0 in FIG. 4, since the wide width on-gate command signal b is at the H level, the gate current cutoff switch 44 is turned off, and the overdrive command signal c is also at the H level.
Since the level is the level, the overdrive signal generation circuit 50 is also turned off. At this time, since the off-gate command signal d is at the L level, the off-gate signal generation circuit 60 is on. Therefore, since the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29 and is lower than the threshold voltage h, the output f of the gate-cathode voltage level discriminating circuit 41 becomes H level. Becomes Therefore, the output g of the first AND circuit 42 becomes H level, and the wide on-gate signal generation circuit 10 is off.

At time t1, wide-width on-gate command signal b goes low, so that gate current cutoff switch 44 turns on, overdrive command signal c also goes low, and overdrive signal generating circuit 50 also turns on. . Further, since the off-gate command signal d becomes H level, the off-gate signal generation circuit 60 is turned off. At this time, since a current flows to the GTO 7 side, the gate-cathode voltage e of the GTO 7 is forward-biased in the forward direction by the forward ON voltage of the PN junction between the gate and the cathode, and the threshold voltage h Therefore, the output f of the gate-cathode voltage level determination circuit 41 becomes L
Level. Therefore, the output g of the first AND circuit 42 becomes L level, the on-gate switch 12a is turned on, and the wide on-gate signal generation circuit 10 is turned on.

At time t2, the wide on-gate command signal b remains at the L level, but the overdrive command signal c attains the H level, so that the gate current cutoff switch 44 is turned on and the overdrive signal generation circuit 5
0 is off. Further, since the off-gate command signal d remains at the H level, the off-gate signal generation circuit 60 is off. At this time, since the current flows to the GTO 7 side, the gate-cathode voltage e of the GTO 7 is also forward-biased in the positive direction by the forward ON voltage of the PN junction between the gate and the cathode during this period. Since the voltage is higher than the hold voltage h, the output f of the gate-cathode voltage level determination circuit 41 becomes L level. Therefore, the output g of the first AND circuit 42 becomes L level, and the on-gate switch 12a is turned on. As a result, the wide on-gate signal generating circuit 10 is turned on, the gate current Ig is supplied to the gate of the GTO 7, and the GTO 7 is kept on.

At time t3, wide on-gate command signal b attains H level and gate current cutoff switch 4
4 is turned off, and the overdrive command signal c remains at the H level, so that the overdrive signal generation circuit 5
0 is off. Further, since the off-gate command signal d becomes L level, the off-gate signal generation circuit 60 is turned on. Therefore, the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29 and becomes lower than the threshold voltage h. Therefore, G
TO7 enters an off operation, and the output f of the gate-cathode voltage level determination circuit 41 becomes H level. Therefore the first
The output g of the AND circuit 42 goes high, and the on-gate switch 12a is also turned off, so that the wide on-gate signal generation circuit 10 is turned off.

During the period from time t3 to time t4, GT
This is a period during which the carrier between the gate and the cathode is removed in order to turn off O7. At time t4, the off operation of GTO7 is completed. Thereafter, until time t5, the gate current Ig becomes G.
Only a small current flows to maintain the OFF state of TO7.

At time t5, since the current a of the GTO circuit is in the positive direction, the same operation as from time 1 to time t3 is repeated until time t7. Near the time t7, the gate-cathode voltage level determining circuit 41
Has a slight time difference after the current starts to flow through the diode 8, and goes high at time t7. The reason for this is that the threshold voltage h may actually become unstable near the intersection of the current on the GTO 7 side and the current on the diode 8 side of the GTO circuit. This is because it is better to set the voltage to a minus voltage at which the forward ON voltage of the diode 8 is established after the current starts flowing. Therefore, the output g of the first AND circuit 42 becomes H level, the on-gate switch 12a is turned off, and the wide on-gate signal generation circuit 10
Turns off.

Next, the operation until time t8 will be described. FIG. 8 is a circuit diagram when a current flows through the diode 8 of the GTO circuit and a forward ON voltage is generated. The same reference numerals as those in FIG. Omitted. This case also relates to an anode-emitter short type GTO. The internal model of the GTO 7 is as shown in b1 of FIG. 5, and a diode is parasitically connected between the anode A and the gate G in anti-parallel. The model is represented as b2 in FIG. With reference to the anode A of the GTO 7, the voltage value of the forward ON voltage 8a of the diode 8 is VF1, the voltage value of the on-gate voltage source 17 is V2, the forward ON voltage value of the parasitic diode 7a of the GTO 7 is VF3, Assuming that the resistance value of R16 is R1 and the resistance value of the first bypass resistor 43 is R2, Ig =
A current determined by (VF1 + V2-VF3) / (R1 + R2) flows from the gate of GTO7 to the anode. Since this current is set lower than the normal gate current Ig = V2 / R1, for example, about 1/100, the generation loss of the wide on-gate signal generation circuit 10 during this period is minimized. Thus,-(VF1-VF3) is generated for the gate-cathode voltage e until the time t8.

In the third embodiment, the reason why the wide on-gate signal generation circuit 10 is not completely turned off when a current flows to the diode 8 side as in the first embodiment is, for example, in FIG. As shown, when an FET or the like is used for the off-gate switch 23a, the parasitic capacitance 23b on both ends of the off-gate switch 23a becomes higher than the voltage charged to the voltage of the off-gate voltage source 29 while the off-gate signal generation circuit 60 is on. Is reduced by the forward ON voltage 8a generated when a current flows through the gate electrode, and the gate voltage remains negative unless recharged. This is because charging does not need to be delayed as compared with the voltage of the on-gate voltage source 29.

In the semiconductor device driving circuit according to the second embodiment,
While the GTO 7 is off, the off-gate switch 2
3a is turned on, the wide on-gate signal generation circuit 10
Causes a current to flow toward the off-gate voltage source 29, which causes loss to occur in the resistor 16 and the first bypass resistor 43. However, as in the third embodiment, By providing the switch 44, the loss can be suppressed.

The period from time t8 to time t9 is GT
This is a period during which the carrier between the gate and the cathode is removed to turn off O7. At time t9, the off operation of GTO7 is completed, and thereafter, until time t10, the gate current Ig only maintains the off state of GTO7. Only a very small current is flowing.

At time t11, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). Further, the gate current cutoff switch 44 is turned on, and a small gate current Ig flows through the gate of the GTO 7.

The period from time t12 to time t13 is
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the GTO 7. At time t13, the turning off of the GTO 7 is completed. Only a very small current is flowing.

At time t14, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). Further, the gate current cutoff switch 44 is turned on, and a small gate current Ig flows through the gate of the GTO 7.

At time t16, the direction of the current a of the GTO circuit is switched from negative to positive. By setting the threshold voltage h of the gate-cathode voltage level discriminating circuit 41 to minus, the gate-cathode voltage The output f of the level discriminating circuit 41 can have a slight time difference before the current stops flowing through the diode 8, and at time t16, the output f of the gate-cathode voltage level discriminating circuit 41 is set to L level, The output g of the circuit 42 is set to L level, and the wide on-gate signal generation circuit 10
Is turned on, and waits as an on-state gate signal for flowing a positive current of the GTO 7. For example, when an FET or the like is used for the off-gate switch 23 a, the parasitic capacitance 23 b at both ends of the switch is rapidly reduced. To charge. As a result, the GTO 7 turns on during the period from the time t16 to the time t17.

The period from time t17 to time t18 is
This is a period in which the carrier between the gate and the cathode is removed in order to turn off the GTO 7, and the turning off of the GTO 7 is completed at time t <b> 18, and thereafter, the gate current Ig flows only a small current enough to maintain the off state of the GTO 7. Absent.

As described above, also in the third embodiment, when the current flowing through the GTO circuit is in the negative direction,
During the period in which the current flows through the diode 8 connected in anti-parallel to the TO 7, the loss generated in the wide on-gate signal generation circuit 10 can be eliminated, so that the conventional GTO pulse transformer type on-gate shown in FIG. Since a wide on-gate signal that is continuous for half a cycle of the inverter output in the control device is applied to the GTO 7, the problem that the power consumption of the gate circuit is large and the gate control device becomes large and expensive can be solved. Similarly, the conventional on-gate control device shown in FIG. 17 also applies a wide on-gate signal to the GTO 7 that is continuous for a half cycle of the inverter output. It is possible to solve the problem that the control device is large and expensive. In the conventional voltage level discriminating circuit using the on-gate control device of the narrow pulse signal control method shown in FIG. 18, a withstand voltage against the DC voltage of the inverter is required during the GTO off period in order to monitor the voltage between the anode and the cathode. In particular, it is possible to solve the problem that the problem that the diode 1g in the discrimination circuit 1 requires a withstand voltage can be solved, and the ideal circuit having the stability of the wide-type wide-on-gate signal generation circuit can be obtained. Can be realized.

Embodiment 4 Next, a fourth embodiment of the present invention will be described. FIG. 9 is a circuit diagram showing a configuration of a semiconductor element driving circuit according to a fourth embodiment of the present invention. Components corresponding to those of the second embodiment are denoted by the same reference numerals as in FIG. I do. In the semiconductor element driving circuit according to the fourth embodiment, the first bypass resistor 43 is connected in parallel to the on-gate switch 12a in the same manner as in the second embodiment. The gate-cathode voltage of the GTO 7 is monitored, and when a current flows through the diode 8 connected in anti-parallel to the GTO 7 of the GTO circuit when the wide ON gate command signal is ON, the wide ON gate signal is output by the output of the first AND circuit 42. After the on-gate switch 12a of the generating circuit 10 is turned off and the on-gate switch 12a is turned off, a minute current flows to the gate of the GTO 7 through the series connection of the resistor 16 and the first bypass resistor 43, and the anode-emitter short circuit occurs. During the period when current flows through the diode 8 antiparallel to the GTO 7 of the GTO circuit using the Is a circuit that prevents operating the on-gate signal generating circuit 10, the series connection of the switch and the first bypass resistor 43 is connected in parallel to the on-gate switch 12a.

In the figure, reference numeral 45 denotes a first bypass resistor 43 connected in parallel to the on-gate switch 12a.
The first bypass switch is connected in series to the switch 16 and operates in synchronization with the wide on-gate command signal from the command signal generation circuit 3a. GTO via connector
7 turns on / off the minute current flowing through the gate. In the semiconductor device drive circuit according to the fourth embodiment, the series connection of the first bypass switch 45 and the first bypass resistor 43 is equivalent to the on-gate switch 12.
The second embodiment is different from the second embodiment in that it is connected in parallel to a.

Next, the operation will be described. Here, the operation waveforms of the semiconductor element drive circuit according to the fourth embodiment are the same as those shown in FIG. FIG. 4A shows an example of a current waveform of the GTO circuit. A broken line portion in the current waveform a represents a current flowing in another GTO circuit of the inverter not shown in the figure, and a positive side portion is a GTO circuit. GTO7
The negative part indicates that the diodes 8 of the GTO circuit are each carrying an inverter current. FIG.
c and d are on / off command signals of each gate signal generation circuit from the command signal generation circuit 3a in FIG. 9, b is a wide on-gate command signal, c is an overdrive command signal, and d is an off-gate command signal. Also, the on-gate switch 12a and the overdrive switch 22 shown in FIG.
a, the off-gate switch 23a, and the first bypass switch 45 all operate low active.

At time t0 in FIG. 4, since the wide on-gate command signal b is at the H level, the first bypass switch 45 is turned off, and the overdrive command signal c is also at the H level.
Since the level is the level, the overdrive signal generation circuit 50 is also turned off. At this time, since the off-gate command signal d is at the L level, the off-gate signal generation circuit 60 is on. Therefore, since the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29 and is lower than the threshold level h, the output f of the gate-cathode voltage level discriminating circuit 41 becomes H level. Becomes Therefore, the output g of the first AND circuit 42 becomes H level, the on-gate switch 12a and the first bypass switch 45 are both turned off, and the wide on-gate signal generation circuit 10 is turned off.

At time t1, the wide on-gate command signal b goes low, so that the first bypass switch 45 is turned on, the overdrive command signal c goes low, and the overdrive signal generating circuit 50 is turned on. Become. Further, since the off-gate command signal d becomes H level, the off-gate signal generation circuit 60 is turned off. At this time, since a current flows to the GTO 7 side, the gate-cathode voltage e of the GTO 7 is forward-biased in the forward direction by the forward ON voltage of the PN junction between the gate and the cathode, and the threshold voltage h Therefore, the output f of the gate-cathode voltage level determination circuit 41 becomes L
Level. Therefore, the output g of the first AND circuit 42 becomes L level, the on-gate switch 12a is turned on, and the wide on-gate signal generation circuit 10 is turned on.

At time t2, the wide on-gate command signal b remains at the L level, but the overdrive command signal c goes to the H level, so that the first bypass switch 45 is turned on and the overdrive signal generation circuit 5
0 is off. Further, since the off-gate command signal d remains at the H level, the off-gate signal generation circuit 60 is off. At this time, since the current flows to the GTO 7 side, the gate-cathode voltage e of the GTO 7 is also forward-biased in the positive direction by the forward ON voltage of the PN junction between the gate and the cathode during this period. Since the voltage is higher than the hold voltage h, the output f of the gate-cathode voltage level determination circuit 41 becomes L level. Therefore, the output g of the first AND circuit 42 becomes L level, and the on-gate switch 12a is turned on. As a result, the wide on-gate signal generating circuit 10 is turned on, the gate current Ig is supplied to the gate of the GTO 7, and the GTO 7 is kept on.

At time t3, wide on-gate command signal b attains H level, causing first bypass switch 4
5 is turned off, and the overdrive command signal c remains at the H level.
0 is off. Further, since the off-gate command signal d becomes L level, the off-gate signal generation circuit 60 is turned on. Therefore, the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29 and becomes lower than the threshold voltage h. Therefore, G
TO7 enters an off operation, and the output f of the gate-cathode voltage level determination circuit 41 becomes H level. Therefore the first
The output g of the AND circuit 42 goes high, and the on-gate switch 12a is also turned off, so that the wide on-gate signal generation circuit 10 is turned off.

The period from time t3 to time t4 is GT
This is a period during which the carrier between the gate and the cathode is removed in order to turn off O7. At time t4, the off operation of GTO7 is completed. Thereafter, until time t5, the gate current Ig becomes G.
Only a small current flows to maintain the OFF state of TO7.

At time t5, the current a of the GTO circuit
Is a positive direction, so that the same operation from time 1 to time t3 is repeated until time t7 is reached. Time t7
In the vicinity, a gate-cathode voltage level determining circuit 4
The output f of 1 has a slight time difference after the current starts to flow through the diode 8, and goes to the H level at time t7.
The reason for this is that the threshold voltage h may actually become unstable near the intersection of the current on the GTO 7 side and the current on the diode 8 side of the GTO circuit. This is because it is better to set the voltage to a minus voltage at which the forward ON voltage of the diode 8 is established after the current starts flowing. Therefore, the output g of the first AND circuit 42 becomes H level, the on-gate switch 12a is turned off, and the wide on-gate signal generation circuit 1
0 indicates an off operation. At this time, since the first bypass switch 45 is on, a minute current flows as the gate current Ig to the gate of the GTO 7.

Next, the operation until time t8 will be described. FIG. 10 shows a circuit diagram when a current flows through the diode 8 of the GTO circuit and a forward ON voltage is generated. The same reference numerals as those in FIG. Omitted. This case also relates to an anode-emitter short type GTO. The GTO 7 part model is as shown by b1 in FIG. 5 and a diode is parasitically connected between the anode A and the gate G in anti-parallel. Is represented as b2 in FIG. With reference to the anode A of the GTO 7, the voltage value of the forward ON voltage 8a of the diode 8 is VF1, the voltage value of the on-gate voltage source 17 is V2, the forward ON voltage value of the parasitic diode 7a of the GTO 7 is VF3, 16 is R1, the first
If the resistance value of the bypass resistor 43 is R2, Ig =
A current determined by (VF1 + V2-VF3) / (R1 + R2) flows from the gate of GTO7 to the anode. Since this current is set lower than the normal gate current Ig = V2 / R1, for example, about 1/100, the generation loss of the wide on-gate signal generation circuit 10 during this period is minimized. Thus,-(VF1-VF3) is generated for the gate-cathode voltage e until the time t8.

In the fourth embodiment, the reason why the wide on-gate signal generating circuit 10 is not completely turned off when a current flows to the diode 8 side as in the first embodiment is, for example, in FIG. As shown, when an FET or the like is used for the off-gate switch 23a, the parasitic capacitance 23b at both ends of the off-gate switch 23a becomes higher than the voltage charged to the voltage of the off-gate voltage source 29 during the period when the off-gate signal generation circuit 60 is on. Is reduced by the forward ON voltage 8a generated when a current flows through the gate electrode, and the gate voltage remains negative unless the battery is recharged. This is because charging does not need to be delayed as compared with the voltage of the on-gate voltage source 29.

Here, for example, in the case of the third embodiment, since the gate current cutoff switch 44 is connected in series to the output of the wide on-gate signal generation circuit 10, a switching element such as an FET is used for it. in case of,
Although the loss at the time of normal wide on-gate signal output is increased by the on-resistance due to the on-resistance.
As described above, the series connection of the first bypass resistor 43 and the first bypass switch 45 is connected to the on-gate switch 12.
a, the output of the wide on-gate signal generation circuit 10 can be directly connected to the gate of the GTO 7, and the gate current cutoff switch 4 of the third embodiment can be connected.
4 can be reduced.

During the period from time t8 to time t9, GT
This is a period during which the carrier between the gate and the cathode is removed to turn off O7. At time t9, the off operation of GTO7 is completed, and thereafter, until time t10, the gate current Ig only maintains the off state of GTO7. Only a very small current is flowing.

At time t11, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). At this time, the first bypass switch 45 is on because the wide on-gate command signal b is at the L level, and a very small current flows through the gate of the GTO 7 as the gate current Ig.

The period from time t12 to time t13 is
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the GTO 7. At time t13, the turning off of the GTO 7 is completed. Only a very small current is flowing.

Also at time t14, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). At this time, the first bypass switch 45 is turned on because the wide on-gate command signal b is at the L level, and a minute current flows as the gate current Ig to the gate of the GTO 7.

At time t16, the direction of the current a of the GTO circuit is switched from negative to positive. By setting the threshold voltage h of the gate-cathode voltage level discriminating circuit 41 to a negative value, the gate-cathode voltage is reduced. The output f of the level discriminating circuit 41 can have a slight time difference before the current stops flowing to the diode 8, and at time t16, the output f of the gate-cathode voltage level discriminating circuit 41 and the first AND circuit 42 Output g
Is set to the L level, the wide on-gate signal generation circuit 10 is turned on, and waits as an on-state gate signal for flowing the positive direction current of the GTO 7. For example, when the FET or the like is used for the off-gate switch 23 a, The capacitor 23b parasitic at both ends of the switch is rapidly charged. As a result, the GTO 7 is turned on during the period from the time t16 to the time t17.

The period from time t17 to time t18 is
This is a period in which the carrier between the gate and the cathode is removed in order to turn off the GTO 7, and the turning off of the GTO 7 is completed at time t <b> 18, and thereafter, the gate current Ig flows only a small current enough to maintain the off state of the GTO 7. Absent.

As described above, also in the fourth embodiment, when the current flowing through the GTO circuit is in the negative direction,
During the period in which the current flows through the diode 8 connected in anti-parallel to the TO 7, the loss generated in the wide on-gate signal generation circuit 10 can be eliminated, so that the conventional GTO pulse transformer type on-gate shown in FIG. Since a wide on-gate signal that is continuous for half a cycle of the inverter output in the control device is applied to the GTO 7, the problem that the power consumption of the gate circuit is large and the gate control device becomes large and expensive can be solved. Similarly, the conventional on-gate control device shown in FIG. 17 also applies a wide on-gate signal to the GTO 7 that is continuous for a half cycle of the inverter output. It is possible to solve the problem that the control device is large and expensive. In the voltage level discriminating circuit of the conventional narrow pulse signal control type transformer type gate control device shown in FIG. In particular, it is possible to achieve an effect that the problem that the diode 1g in the discrimination circuit 1 requires a withstand voltage can be solved, and an ideal circuit having the stability of the wide-type wide-on-gate signal generation circuit is realized. it can.

Embodiment 5 Next, Embodiment 5 of the present invention will be described. FIG.
FIG. 10 is a circuit diagram showing a configuration of a semiconductor element drive circuit according to a fifth embodiment of the present invention. Parts corresponding to those in the fourth embodiment are denoted by the same reference numerals as in FIG. 9 and description thereof is omitted. The semiconductor element driving circuit according to the fifth embodiment has an on-gate switch 12a as in the fourth embodiment.
, A series connection of a first bypass resistor 43 and a first bypass switch 45 is connected in parallel, and a gate-cathode voltage level discriminating circuit 41 monitors the gate-cathode voltage of the GTO 7 to obtain a wide on-gate. When a current flows through the diode 8 connected in anti-parallel to the GTO 7 of the GTO circuit when the command signal is on, the output of the first AND circuit 42 turns off the on-gate switch 12a of the wide on-gate signal generation circuit 10 to turn on the on-gate. Switch 12a
A small current flowing to the gate of the GTO 7 through a series connection of the resistor 16 and the first bypass resistor 43 is turned on / off by the first bypass switch 45 after the transistor is turned off, and an anode-emitter short type GTO is used. GT of GTO circuit
A period in which a current flows through the diode 8 antiparallel to O7,
This is a circuit for preventing the wide on-gate signal generation circuit 10 from operating. The first bypass switch 45 connected in series with the first bypass resistor 43 is directly operated by the wide on-gate command signal from the command signal generation circuit 3a. It is controlled by a logical product with the output of the first AND circuit 42 without control.

In the figure, 46 is a first bypass switch 45 connected in series to the first bypass resistor 43.
A second AND circuit for controlling on / off of the
In order to turn on the bypass switch 45, the output of the first AND circuit 42 and the wide ON gate command signal from the command signal generation circuit 3a are input, and the first AND circuit 4
An output function of turning on the first bypass switch 45 is provided when the output of the second output switch 2a outputs a signal for turning off the on-gate switch 12a and the wide on-gate signal outputs a signal for turning on the GTO 7. have. The semiconductor device driving circuit according to the fifth embodiment is
Embodiment 4 is different from Embodiment 4 in that the output of the second AND circuit 46 controls ON / OFF of the first bypass switch 44.

Next, the operation will be described. Here, FIG. 12 is a waveform diagram for explaining the operation of the semiconductor element drive circuit according to the fifth embodiment. FIG. 12A shows an example of the current waveform of the GTO circuit. The broken line portion in the current waveform a is another GT of the inverter not shown in the figure.
This is the current flowing in the O circuit. The positive side of the current a indicates that the GTO 7 of the GTO circuit is passing an inverter current from the anode to the cathode, and the negative side is that the diode 8 of the GTO circuit is passing an inverter current from the anode to the cathode. Represents. B, c, in FIG.
d is an on / off command signal for each gate signal generation circuit from the command signal generation circuit 3a in FIG. 11, b is a wide on-gate command signal serving as a source for operating the wide on-gate signal generation circuit 10, and c is GTO7 with single pulse
Is an overdrive command signal for operating the overdrive signal generation circuit 50, and d is an off-gate signal generation circuit 6.
0 is an off-gate command signal for operating 0. FIG.
1, the on-gate switch 12a, the overdrive switch 22a, the off-gate switch 23a, and the first bypass switch 45 all operate in a low active state.

At time t0 in FIG. 12, wide on-gate command signal b and overdrive command signal c are both at H level. Due to the H level of the overdrive command signal c, the overdrive signal generation circuit 50 is turned off. At this time, since the off-gate command signal d is at the L level, the off-gate signal generation circuit 60 is on. Accordingly, the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29 and is lower than the threshold voltage h.
The output f of the gate-cathode voltage level determination circuit 41 becomes H level. Therefore, the output g of the first AND circuit 42
Becomes H level, and the on-gate switch 12a is turned off. Also, at this time, since the wide on-gate command signal b is at the H level, the output i of the second AND circuit 46 also goes to the H level. Therefore, the first bypass switch 4
5 is also off, and the wide on-gate signal generation circuit 10 is off.

At time t1, both wide-width on-gate command signal b and overdrive command signal c are at L level, so that overdrive signal generation circuit 50 is turned on by the L level of overdrive command signal c. Further, since the off-gate command signal d becomes H level, the off-gate signal generation circuit 60 is turned off. Then GT
Since a current flows to the O7 side, the gate-cathode voltage e of the GTO7 is forward-biased in the forward direction by an amount corresponding to the forward ON voltage of the PN junction between the gate and the cathode, and is higher than the threshold voltage h. The gate is
The output f of the inter-cathode voltage level determination circuit 41 becomes L level. Therefore, the output g of the first AND circuit 42 becomes L level, the on-gate switch 12a is turned on, and the wide on-gate signal generation circuit 10 is turned on.

At time t2, wide-width on-gate command signal b remains at L level, but overdrive command signal c goes to H level. When the overdrive command signal c is at H level, the overdrive signal generation circuit 50 is turned off. The off-gate command signal d is H
Since the level remains, the off-gate signal generation circuit 60 is off. At this time, since the current flows to the GTO 7 side, the gate-cathode voltage e
Is forward-biased in the positive direction by the forward ON voltage of the PN junction between the gate and the cathode, and is higher than the threshold voltage h. become. Therefore the first
The output g of the AND circuit 42 goes low, and the on-gate switch 12a is turned on. As a result, the wide on-gate signal generation circuit 10 is turned on, the gate current Ig is supplied to the gate of the GTO 7, and the GTO 7 is kept on.

At time t3, wide on-gate command signal b attains H level, and overdrive command signal c
Maintain the H level as it is. The overdrive signal generation circuit 50 remains off due to the H level of the overdrive command signal c. Further, since the off-gate command signal d becomes L level, the off-gate signal generation circuit 60 is turned on. Therefore, the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29 and becomes lower than the threshold voltage h. Therefore, the GTO 7 enters an off operation, and the output f of the gate-cathode voltage level determination circuit 41 becomes H level. Therefore, the output g of the first AND circuit 42 becomes H level and the on-gate switch 12a is also turned off, so that the wide on-gate signal generation circuit 10 is turned off.

The period from time t3 to time t4 is GT
This is a period during which the carrier between the gate and the cathode is removed in order to turn off O7. At time t4, the off operation of GTO7 is completed. Thereafter, until time t5, the gate current Ig becomes G.
Only a small current flows to maintain the OFF state of TO7.

At time t5, the current a of the GTO circuit
Is a positive direction, so that the same operation from time 1 to time t3 is repeated until time t7 is reached. Time t7
In the vicinity, a gate-cathode voltage level determining circuit 4
The output f of 1 has a slight time difference after the current starts to flow through the diode 8, and goes to the H level at time t7.
The reason for this is that the threshold voltage h may actually become unstable near the intersection of the current on the GTO 7 side and the current on the diode 8 side of the GTO circuit. This is because it is better to set the voltage to a minus voltage at which the forward ON voltage of the diode 8 is established after the current starts flowing. Therefore, the output g of the first AND circuit 42 becomes H level, the on-gate switch 12a is turned off, and the wide on-gate signal generation circuit 1
0 indicates an off operation. At this time, the first AND circuit 42 input to the second AND circuit 46 is first input.
Becomes high, and the wide on-gate command signal b from the command signal generation circuit 3a goes low, so that the output i of the second AND circuit 46 goes low. Therefore, the first bypass switch 4 that has been turned off
5 is turned on, and the gate current Ig is supplied to the gate of GTO7.
And a very small current flows.

Next, the operation until time t8 will be described. Also in this case, anode / emitter short type GT
O, and the internal model of GTO7 is b1 in FIG.
Since a diode is parasitically connected between the anode A and the gate G in anti-parallel, the circuit diagram model is represented as b2 in FIG. With reference to the anode A of the GTO 7, the voltage value of the forward ON voltage 8a of the diode 8 is VF1, and the voltage value of the ON gate voltage source 17 is V
2. Assuming that the forward ON voltage value of the parasitic diode 7a of the GTO 7 is VF3, the resistance value of the resistor 16 is R1, and the resistance value of the first bypass resistor 43 is R2, Ig = (VF1 +
The current determined by V2-VF3) / (R1 + R2) is GTO
7 flows to the anode A from the gate G. This current is lower than the normal gate current Ig = V2 / R1, for example, 1/1
Since it is set to about 00, the generation loss of the wide on-gate signal generation circuit 10 during this period is minimized. Thus,-(VF1-VF3) is generated for the gate-cathode voltage e until the time t8.

In the fifth embodiment, the reason why the wide on-gate signal generation circuit 10 is not completely turned off when a current flows to the diode 8 side as in the first embodiment is, for example, in FIG. As shown, when an FET or the like is used for the off-gate switch 23a, the parasitic capacitance 23b at both ends of the off-gate switch 23a becomes higher than the voltage charged to the voltage of the off-gate voltage source 29 while the off-gate signal generation circuit 60 is on. Is reduced by the forward ON voltage 8a generated when a current flows through the gate electrode, and the gate voltage remains negative unless recharged. This is because the charging is not delayed as compared with the voltage of the on-gate voltage source 29.

In the case of the fourth embodiment, the gate current Ig flowing to the gate of the GTO 7 during the normal GTO 7 on-period is divided between the on-gate switch 12a and the first bypass switch 45. Therefore, it is necessary to select a switch element having a sufficient current capacity as the first bypass switch 45. However, a second AND circuit 46 is provided to provide the first bypass switch 45.
By considering only the period during which a current flows through the diode 8, it becomes possible to select a switch element having a current capacity approximately half that of the fourth embodiment.

During the period from time t8 to time t9, GT
This is a period during which the carrier between the gate and the cathode is removed to turn off O7. At time t9, the off operation of GTO7 is completed, and thereafter, until time t10, the gate current Ig only maintains the off state of GTO7. Only a very small current is flowing. At this time, since the wide-band on-gate command signal b input from the command signal generation circuit 3a to the second AND circuit 46 is at H level, the output of the second AND circuit 46 is at H level, Is turned off.

At time t11, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). At this time, the wide on-gate command signal b input to the second AND circuit 46 becomes L level, and the output g of the first AND circuit 42 becomes H level. Therefore, the output i of the second AND circuit 46 becomes an L level output, the first bypass switch 45 is turned on, and a very small current flows as a gate current Ig to the gate of the GTO 7.

The period from time t12 to time t13 is
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the GTO 7. At time t13, the turning off of the GTO 7 is completed. Only a very small current is flowing. Also, during this period, the wide on-gate command signal b input to the second AND circuit 46 goes high, so that the output i of the second AND circuit 46 goes high, and the first bypass switch 45 is turned off. I do.

At time t14, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the first bypass resistor 43, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). At this time, the wide ON gate command signal b input to the second AND circuit 46 becomes L level, and the output g of the first AND circuit 42 becomes H level, so that the output i of the second AND circuit 46 becomes L level. Level, the first bypass switch 45 is turned on, and the GTO
A very small current flows as the gate current Ig to the gate 7.

At time t16, the direction of the current a of the GTO circuit is switched from negative to positive. By setting the threshold voltage h of the gate-cathode voltage level discriminating circuit 41 to a negative value, the gate-cathode voltage The output f of the level discriminating circuit 41 can be made to have a slight time difference before the current stops flowing through the diode 8, and the output f of the gate-cathode voltage level discriminating circuit 41 and the first AND circuit 42 at time t16. Output g
Is set to the L level, the wide on-gate signal generation circuit 10 is turned on, and waits as an on-state gate signal for flowing the positive current of the GTO 7. For example, when the FET or the like is used for the off-gate switch 23a, ,
The capacitor 23b parasitic at both ends of the switch is rapidly charged. As a result, the GTO 7 is turned on during the period from time t16 to time t17. At this time, the wide ON gate command signal b input to the second AND circuit 46 is at L level, and the output g of the first AND circuit 42 is
Becomes L level, the output i of the second AND circuit 46
Is at H level, and the first bypass switch 45 is turned off.

The period from time t17 to time t18 is
This is a period in which the carrier between the gate and the cathode is removed in order to turn off the GTO 7, and the turning off of the GTO 7 is completed at time t <b> 18, and thereafter, the gate current Ig flows only a small current enough to maintain the off state of the GTO 7. Absent.

As described above, also in the fifth embodiment, when the current flowing through the GTO circuit is in the negative direction,
During the period in which the current flows through the diode 8 connected in anti-parallel to the TO 7, the loss generated in the wide on-gate signal generation circuit 10 can be eliminated, so that the conventional GTO pulse transformer type on-gate shown in FIG. Since a wide on-gate signal that is continuous for half a cycle of the inverter output in the control device is applied to the GTO 7, the problem that the power consumption of the gate circuit is large and the gate control device becomes large and expensive can be solved. Similarly, the conventional on-gate control device shown in FIG. 17 also applies a wide on-gate signal to the GTO 7 that is continuous for a half cycle of the inverter output. It is possible to solve the problem that the control device is large and expensive. In the voltage level discriminating circuit of the conventional narrow pulse signal control type transformer type gate control device shown in FIG. In particular, it is possible to achieve an effect that the problem that the diode 1g in the discrimination circuit 1 requires a withstand voltage can be solved, and an ideal circuit having the stability of the wide-type wide-on-gate signal generation circuit is realized. it can.

Embodiment 6 FIG. Next, a sixth embodiment of the present invention will be described. FIG. 13 shows Embodiment 6 of the present invention.
1 is a circuit diagram showing a configuration of a semiconductor element drive circuit according to the first embodiment.
In the figure, 7 and 8 are GTOs constituting the GTO circuit.
And a diode, and 10 is an on-gate switch 12
a, a resistor 16, a wide on-gate voltage source 17, and a wide on-gate signal generation circuit including a smoothing capacitor 18.
6. Overdrive voltage source 27, smoothing capacitor 2
8 and an off-gate signal generation circuit 60 including an off-gate switch 23 a, an off-gate voltage source 29, and a smoothing capacitor 30. Also, 3
a is a command signal generation circuit, 41 is a gate-cathode voltage level discrimination circuit, and 42 is a first AND circuit. These components are the same as those in the first embodiment shown in FIG.

9d is a GTO 7 forming a GTO circuit.
GTO7 connected in parallel between the gate and cathode of
And 47, a second bypass resistor for turning on / off a parallel connection of the second bypass resistor 9d between the gate and the cathode of the GTO 7. Switch. Reference numeral 46 denotes a second AND circuit having an AND function equivalent to that of the fifth embodiment shown in FIG. 11 with the same reference numerals and controlling ON / OFF of the second bypass switch 47. . As described above, the semiconductor element drive circuit according to the sixth embodiment includes a series connection of the second bypass resistor 9d and the second bypass switch 47 in parallel between the gate and the cathode of the GTO 7 instead of the pull-up resistor 9c. The second embodiment is different from the first embodiment in that the second AND switch 46 controls ON / OFF of the second bypass switch 47.

Next, the operation will be described. Here, the operation waveforms of the semiconductor element drive circuit according to the sixth embodiment are the same as those shown in FIG. FIG. 12A shows an example of a current waveform of the GTO circuit. A broken line portion in the current waveform a represents a current flowing in another GTO circuit of the inverter not shown in the figure, and a positive side portion is a GTO circuit. GTO7
However, the negative portion indicates that the diodes 8 of the GTO circuit are each carrying an inverter current. 12, b, c, and d are on / off command signals for the respective gate signal generation circuits from the command signal generation circuit 3a in FIG. 13, where b is a wide on-gate command signal, c is an overdrive command signal, and d is off-gate. This is a command signal. Further, the on-gate switch 12a, the overdrive switch 22a, the off-gate switch 23a, and the second bypass switch 47 shown in FIG. 13 all operate low active.

At time t0 in FIG. 12, wide on-gate command signal b and overdrive command signal c are both at H level. The overdrive signal generation circuit 50 is turned off by the H level of the overdrive command signal c. At this time, since the off-gate command signal d is at the L level, the off-gate signal generation circuit 60 is on. Accordingly, since the gate-cathode voltage e of the GTO 7 is reverse-biased by the DC voltage of the off-gate voltage source 29 and is lower than the threshold voltage h, the output f of the gate-cathode voltage level determination circuit 41 becomes H
Level. Therefore, the output g of the first AND circuit 42 becomes H level, the on-gate switch 12a is turned off, and the wide-width on-gate signal generation circuit 10 is turned off.

At time t1, both wide-width on-gate command signal b and overdrive command signal c are at L level, so that overdrive signal generation circuit 50 is turned on by the L level of overdrive command signal c. Further, since the off-gate command signal d becomes H level, the off-gate signal generation circuit 60 is turned off. Then G
Since a current is flowing to the TO7 side, the gate of the GTO7
The voltage e between the cathodes is forward-biased in the forward direction by an amount corresponding to the forward ON voltage of the PN junction between the gate and the cathode,
Since the voltage becomes higher than the threshold voltage h, the output f of the gate-cathode voltage level determination circuit 41 becomes L level. Therefore, the output g of the first AND circuit 42 becomes L level, the on-gate switch 12a is turned on, and the wide on-gate signal generation circuit 10 is turned on.

At time t2, wide-width on-gate command signal b remains at L level, but overdrive command signal c attains H level. The overdrive signal generation circuit 50 is turned off by the H level of the overdrive command signal c. Since the off-gate command signal d remains at the H level, the off-gate signal generation circuit 60 is off. At this time, since a current flows to the GTO 7 side, the gate-cathode voltage e of the GTO 7 is also forward-biased in the positive direction by the forward ON voltage of the PN junction between the gate and the cathode during this period. Since the voltage is higher than the hold voltage h, the output f of the gate-cathode voltage level determination circuit 41 becomes L level. Therefore, the output g of the first AND circuit 42 becomes L level, and the on-gate switch 12a is turned on. As a result, the wide on-gate signal generation circuit 10 is turned on, the gate current Ig is supplied to the gate of the GTO 7, and the GTO 7 is kept on.

At time t3, wide on-gate command signal b goes high, and overdrive command signal c
Maintain the H level as it is. Due to the H level of the overdrive command signal c, the overdrive signal generation circuit 50 remains off. Further, since the off-gate command signal d becomes L level, the off-gate signal generation circuit 60 is turned on. Therefore, the gate of GTO7
The inter-cathode voltage e is reverse-biased by the DC voltage of the off-gate voltage source 29 and becomes lower than the threshold voltage h. Therefore, the GTO 7 enters the off operation, and the gate-
The output f of the inter-cathode voltage level determination circuit 41 becomes H level. Therefore, the output g of the first AND circuit 42 becomes H level and the on-gate switch 12a is also turned off, so that the wide on-gate signal generation circuit 10 is turned off.

During the period from time t3 to time t4, GT
This is a period during which the carrier between the gate and the cathode is removed in order to turn off O7. At time t4, the off operation of GTO7 is completed. Thereafter, until time t5, the gate current Ig becomes G.
Only a small current flows to maintain the OFF state of TO7.

At time t5, the current a of the GTO circuit
Is a positive direction, so that the same operation from time 1 to time t3 is repeated until time t7 is reached. Time t7
In the vicinity, a gate-cathode voltage level determining circuit 4
The output f of 1 has a slight time difference after the current starts to flow through the diode 8, and goes to the H level at time t7.
The reason for this is that the threshold voltage h may actually become unstable near the intersection of the current on the GTO 7 side and the current on the diode 8 side of the GTO circuit. This is because it is better to set the voltage to a minus voltage at which the forward ON voltage of the diode 8 is established after the current starts flowing. Therefore, the output g of the first AND circuit 42 becomes H level, the on-gate switch 12a is turned off, and the wide on-gate signal generation circuit 1
0 indicates an off operation. At this time, the first AND circuit 42 input to the second AND circuit 46 is first input.
Becomes high, and the wide on-gate command signal b from the command signal generation circuit 3a goes low, so that the output i of the second AND circuit 46 goes low. As a result, the second bypass switch 47 which has been turned off is turned on, and the forward on voltage of the diode 8 connected in anti-parallel to the GTO 7 of the GTO circuit causes the second bypass switch 47 to turn on.
The current from the cathode of the GTO 7 is bypassed through the bypass resistor 9d, and a minute current flows as a gate current Ig to the gate of the GTO 7.

Next, the operation until time t8 will be described. FIG. 14 is a circuit diagram when a current flows through the diode 8 of the GTO circuit and a forward ON voltage is generated. The same reference numerals as those in FIG. Omitted. Also in this case, the anode-emitter short type GTO is concerned. The internal model of the GTO 7 is as shown by b1 in FIG. 5, and a diode is parasitically connected between the anode A and the gate G in anti-parallel.
The circuit diagram model is represented as b2 in FIG. GTO7
When the voltage value of the forward ON voltage 8a of the diode 8 is VF1, the forward ON voltage value of the parasitic diode 7a of the GTO 7 is VF3, and the resistance value of the second bypass resistor 9d is R3. , Ig = (VF1-
A current determined by VF3) / R3 flows from the gate G of the GTO 7 to the anode A. This current is equal to the normal gate current Ig.
= V2 / R1, for example, about 1/100, so that the generation loss of the wide on-gate signal generation circuit 10 during this period is minimized. Accordingly, the gate-cathode voltage e until time t8 is-(VF1-
VF3) will occur.

As described above, in the sixth embodiment, for example, as shown in FIG.
When an FET or the like is used for 3a, when a current flows through the diode 8 from the voltage charged to the DC voltage of the off-gate voltage source 29 during the on-period of the off-gate signal generation circuit 60 due to the parasitic capacitance 23b at both ends thereof, The pull-up resistor 9c used in the first embodiment has a resistance value that is reduced by the generated forward ON voltage 8a to prevent the gate voltage from remaining negative unless recharged. If not high, losses will occur even during the off period,
By providing the second bypass switch 47 that is turned on / off by the output of the second AND circuit 46, it is possible to reduce the resistance value of the second bypass resistor 9d, and it is parasitic on the off-gate switch 23a. This prevents a delay for recharging the capacitor 23b.

During the period from time t8 to time t9, GT
This is a period during which the carrier between the gate and the cathode is removed to turn off O7. At time t9, the off operation of GTO7 is completed, and thereafter, until time t10, the gate current Ig only maintains the off state of GTO7. Only a very small current is flowing. Also, at this time, since the wide on-gate command signal b input from the command signal generation circuit 3a to the second AND circuit 46 is at H level, the output i of the second AND circuit 46 is at H level, The second bypass switch 47 is turned off.

At time t11, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the second bypass resistor 9d and the second bypass resistor 9d, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). At this time, the wide on-gate command signal b input to the second AND circuit 46 goes low, and the output g of the first AND circuit goes high. Accordingly, the output i of the second AND circuit 46 to which they are input becomes L level, and the second bypass switch 47 is turned on. When the second bypass switch 47 is turned on, a small current flows as a gate current Ig to the gate of the GTO 7 due to the forward ON voltage 8a of the diode 8 connected in anti-parallel to the GTO 7 of the GTO circuit.

The period from time t12 to time t13 is
This is a period during which the carrier between the gate and the cathode is removed in order to turn off the GTO 7. At time t13, the turning off of the GTO 7 is completed. Only a very small current is flowing. Also, during this period, the wide on-gate command signal b input to the second AND circuit 46 goes high, so that the output i of the second AND circuit 46 goes high, and the second bypass switch 47 is turned off. I do.

At time t14, the current a of the GTO circuit
Is in the negative direction, the voltage discrimination by the gate-cathode voltage level discriminating circuit 41 is performed by, for example, when a FET or the like is used for the off-gate switch 23a, a resistor 16b generated by a capacitor 23b parasitic at both ends of the switch. In order not to delay the operation by the time constant of the second bypass resistor 9d and the second bypass resistor 9d, the overdrive command signal c of the GTO 7 is set to L level to turn on the overdrive signal generation circuit 50, and the gate-cathode voltage e To-(VF
1-VF3). Also, at this time, the wide on-gate command signal b input to the second AND circuit 46 goes low, and the output of the first AND circuit 42 goes high, so that the output i of the second AND circuit 46 goes low. Becomes
The second bypass switch 47 is turned on, and a minute current flows through the gate of the GTO 7 as the gate current Ig.

At time t16, the direction of the current a of the GTO circuit is switched from negative to positive. By setting the threshold voltage h of the gate-cathode voltage level discriminating circuit 41 to a minus value, the gate-cathode voltage is reduced. The output f of the level discriminating circuit 41 can be made to have a slight time difference before the current stops flowing through the diode 8, and the output f of the gate-cathode voltage level discriminating circuit 41 and the first AND circuit 42 at time t16. Output g
Is set to the L level, the wide on-gate signal generation circuit 10 is turned on, and waits as an on-state gate signal for flowing the positive current of the GTO 7. For example, when the FET or the like is used for the off-gate switch 23a, ,
The capacitor 23b parasitic at both ends of the switch is rapidly charged. As a result, the GTO 7 is turned on during the period from time t16 to time t17. At this time, the wide ON gate command signal b input to the second AND circuit 46 is at L level, and the output g of the first AND circuit 42 is
Becomes L level, the output i of the second AND circuit 46
Is at H level, and the second bypass switch 47 is turned off.

The period from time t17 to time t18 is
This is a period in which the carrier between the gate and the cathode is removed in order to turn off the GTO 7, and the turning off of the GTO 7 is completed at time t <b> 18, and thereafter, the gate current Ig flows only a small current enough to maintain the off state of the GTO 7. Absent.

As described above, also in the fifth embodiment, when the current flowing through the GTO circuit is in the negative direction,
During the period in which the current flows through the diode 8 connected in anti-parallel to the TO 7, the loss generated in the wide on-gate signal generation circuit 10 can be eliminated, so that the conventional GTO pulse transformer type on-gate shown in FIG. Since a wide on-gate signal that is continuous for half a cycle of the inverter output in the control device is applied to the GTO 7, the problem that the power consumption of the gate circuit is large and the gate control device becomes large and expensive can be solved. Similarly, the conventional on-gate control device shown in FIG. 17 also applies a wide on-gate signal to the GTO 7 that is continuous for a half cycle of the inverter output. It is possible to solve the problem that the control device is large and expensive. In order to monitor the voltage between the anode and the cathode in the voltage level discriminating circuit of the conventional narrow pulse signal control type transformer type gate control device shown in FIG. 18, a withstand voltage against the DC voltage of the inverter is required during the GTO off period. In particular, it is possible to solve the problem that the problem that the diode 1g in the discrimination circuit 1 requires a withstand voltage can be solved, and an ideal circuit having the stability of the wide-type wide-on-gate signal generation circuit can be obtained. realizable.

[0150]

As described above, according to the present invention, the GT
Since the pull-up resistor is connected between the gate and the cathode of O, when the negative direction period of the current flowing through the GTO circuit ends, the potential difference between the gate and the cathode of the GTO disappears, so that the current flows through the GTO circuit. When the current is in the negative direction, that is, during the period when the current is flowing through the diode connected in anti-parallel to the GTO, the on-gate signal is not output and the gate current value is reduced, thereby eliminating the loss that occurs in the on-gate switch. There is an effect that becomes possible.

According to the present invention, since the first bypass resistor is connected in parallel to the on-gate switch, after the on-gate switch is turned off, the resistance of the wide on-gate signal generating circuit and the DC of the bypass resistor are reduced. When the minute current flows through the connection body and the current flowing in the GTO circuit is in the negative direction, that is, during the period when the current flows through the diode connected in anti-parallel to the GTO, the gate current value decreases and is generated by the on-gate switch. There is an effect that the loss can be reduced.

According to the present invention, the first bypass resistor is connected in parallel to the on-gate switch, and the gate current cutoff switch is connected in series between the wide on-gate signal generation circuit and the gate of the GTO. As a result, not only can the loss generated in the on-gate switch be reduced, but also because the off-gate switch is turned on while the GTO is off, the current flowing from the on-gate signal generation circuit to the off-gate voltage source is reduced. And blocking the resistance of the wide on-gate signal generation circuit generated by the current and the loss by the first bypass resistance.

According to the present invention, the first bypass resistor is connected in parallel to the on-gate switch, and the first bypass switch is connected in series to the first bypass resistor. In addition to reducing the loss that occurs in the switch for ON, the ON-gate switch is directly connected to the gate of the GTO, so even if an FET switch or the like is used as a switch element, the influence of the ON resistance is eliminated, There is an effect that the loss due to the on-resistance of the FET switch or the like can be eliminated by the normal on-gate signal current.

According to the present invention, the series connection of the first bypass resistor and the first bypass switch is connected in parallel with the on-gate switch, and the first bypass switch is connected to the second AND circuit. Since it is configured to be controlled by the output, it is possible to reduce the loss generated by the on-gate switch, and it is possible to eliminate the loss due to the on-resistance of the FET switch, etc.
It is not necessary to provide a margin for the current capacity of the first bypass switch, and it is possible to select a switch element having a small current capacity.

According to the present invention, the series connection of the second bypass resistor and the second bypass switch is connected between the gate and the cathode of the GTO.
When the negative direction period of the current flowing through the O circuit ends, GTO
The potential difference between the gate and the cathode is eliminated, and the loss generated in the on-gate switch can be eliminated. Even when an FET or the like is used for the off-gate switch, the effect of the parasitic capacitance on both ends of the switch is prevented. Therefore, it is sufficient to insert the second bypass resistor having a low resistance value at the position of the pull-up resistor for which a high resistance value was required, and the delay for recharging the parasitic capacitance of the off-gate switch is eliminated. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor element drive circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart for explaining an operation of the semiconductor element drive circuit according to the first embodiment;

FIG. 3 is a circuit diagram showing a semiconductor element drive circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform chart for explaining operations of the semiconductor element drive circuits according to the second, third, and fourth embodiments.

FIG. 5 is an explanatory diagram showing an internal model and a circuit model of a GTO.

FIG. 6 is a circuit diagram when a current flows through a diode of the GTO circuit according to the second embodiment to generate a forward ON voltage.

FIG. 7 is a circuit diagram showing a semiconductor element drive circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram when a current flows through a diode of the GTO circuit according to the third embodiment to generate a forward ON voltage.

FIG. 9 is a circuit diagram showing a semiconductor element drive circuit according to a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram when a current flows through the diodes of the GTO circuits according to the fourth and fifth embodiments and a forward ON voltage is generated.

FIG. 11 is a circuit diagram showing a semiconductor element drive circuit according to a fifth embodiment of the present invention.

FIG. 12 is a waveform chart for explaining the operation of the semiconductor element drive circuits according to the fifth and sixth embodiments.

FIG. 13 is a circuit diagram showing a semiconductor element drive circuit according to a sixth embodiment of the present invention.

FIG. 14 is a circuit diagram when a current flows through a diode of the GTO circuit according to the sixth embodiment to generate a forward ON voltage.

FIG. 15 is a circuit diagram showing a conventional on-gate control device of a wide pulse signal control method using a pulse transformer.

FIG. 16 is a signal waveform diagram of an on-gate control device of the wide pulse signal control method using the conventional pulse transformer.

FIG. 17 is a circuit diagram showing another conventional on-gate control device using a wide pulse signal control method.

FIG. 18 is a circuit diagram showing a conventional narrow-pulse signal control type on-gate control device using a pulse transformer.

FIG. 19 is a waveform chart for explaining the operation of the above-described on-gate control device using a narrow pulse signal control method using a pulse transformer.

[Explanation of symbols]

3a command signal generation circuit, 7 GTO, 8 diode, 9c pull-up resistor, 9d second bypass resistor, 10 wide on-gate signal generation circuit, 20 single pulse gate signal generation circuit, 41 gate-cathode voltage level determination circuit, 42 first AND circuit, 43 first bypass resistor, 44 gate current cutoff switch,
45 First bypass switch, 46 Second AND circuit, 47 Second bypass switch.

Claims (6)

[Claims] A wide on-gate signal generating circuit for generating a wide on-gate signal applied between a gate and a cathode of the gate turn-off thyristor for driving an anode-emitter short type gate turn-off thyristor; A single pulse overdrive signal applied between the gate and the cathode of the thyristor and a single pulse gate signal generating circuit for generating an off-gate signal; and a gate turn-off thyristor having a gate-cathode voltage level higher than a predetermined level. A gate-cathode voltage level discriminating circuit for discriminating whether it is high or low and outputting a high or low level discrimination signal; a wide on-gate signal generating circuit and a single pulse according to an on / off command of the gate turn-off thyristor Gate signal generation A command signal generation circuit for generating a command signal for controlling a circuit; and a wide on-gate command signal generated by the command signal generation circuit and an output of the gate-cathode voltage level discrimination circuit. When the signal is on, and when the gate-cathode voltage level discriminating circuit determines that a current flows through a diode which is connected in anti-parallel to the gate turn-off thyristor and forms a gate turn-off thyristor circuit, A first AND circuit having an AND function whose output is a signal for turning off the wide ON-gate signal generating circuit; When the negative period of
A semiconductor element drive circuit comprising a pull-up resistor for eliminating a voltage difference between cathodes. 2. A wide on-gate signal generating circuit for generating a wide on-gate signal applied between a gate and a cathode of the gate turn-off thyristor for driving an anode-emitter short type gate turn-off thyristor; A single pulse overdrive signal applied between the gate and the cathode of the thyristor and a single pulse gate signal generating circuit for generating an off-gate signal; and a gate turn-off thyristor having a gate-cathode voltage level higher than a predetermined level. A gate-cathode voltage level determining circuit that determines whether the signal is high or low and outputs a high or low level determination signal; Gate signal generation A command signal generation circuit for generating a command signal for controlling a circuit; and a wide on-gate command signal generated by the command signal generation circuit and an output of the gate-cathode voltage level discrimination circuit. When the signal is on, and when the gate-cathode voltage level discriminating circuit determines that a current flows through a diode which is connected in anti-parallel to the gate turn-off thyristor and forms a gate turn-off thyristor circuit, A first AND circuit having an AND function whose output is a signal for turning off the wide on-gate signal generation circuit; and a parallel connection to an on-gate switch of the wide on-gate signal generation circuit, bypassing a current flowing through the on-gate switch. And a first bypass resistor. 3. A gate current cutoff switch that is turned on / off in synchronization with a wide on-gate command signal output from a command signal generating circuit is connected in series between a wide on-gate signal generating circuit and a gate of a gate turn-off thyristor. 3. The semiconductor device drive circuit according to claim 2, wherein the circuit is connected. 4. A first bypass resistor connected in parallel to an on-gate switch of a wide on-gate signal generation circuit, a first bypass resistor which is turned on / off in synchronization with a wide on-gate command signal output from a command signal generation circuit. 3. The semiconductor element drive circuit according to claim 2, wherein said bypass switches are connected in series. 5. A second AND circuit having one input as a wide on-gate command signal from a command signal generation circuit and the other input as an output of a first AND circuit, wherein the wide on-gate command signal is When it is ON and the output of the first AND circuit turns off the ON gate switch of the wide ON gate signal generation circuit, the output of the second AND circuit turns ON the first bypass switch. 5. The semiconductor device drive circuit according to claim 4, wherein: 6. A wide on-gate signal generating circuit for generating a wide on-gate signal applied between a gate and a cathode of the gate turn-off thyristor for driving an anode-emitter short type gate turn-off thyristor; A single pulse overdrive signal applied between the gate and the cathode of the thyristor and a single pulse gate signal generating circuit for generating an off-gate signal; and a gate turn-off thyristor having a gate-cathode voltage level higher than a predetermined level. A gate-cathode voltage level discriminating circuit for discriminating whether it is high or low and outputting a high or low level discrimination signal; a wide on-gate signal generating circuit and a single pulse according to an on / off command of the gate turn-off thyristor Gate signal generation A command signal generation circuit for generating a command signal for controlling a circuit; and a wide on-gate command signal generated by the command signal generation circuit and an output of the gate-cathode voltage level discrimination circuit. When the signal is on, and when the gate-cathode voltage level discriminating circuit determines that a current flows through a diode which is connected in anti-parallel to the gate turn-off thyristor and forms a gate turn-off thyristor circuit, A first AND circuit having an AND function whose output is a signal for turning off the wide ON-gate signal generating circuit; and a gate of the gate turn-off thyristor, which is connected in parallel between a gate and a cathode of the gate turn-off thyristor. A second bypass for bypassing the current flowing from the cathode to the gate. A second bypass switch for turning on / off a parallel connection of the second bypass resistor between the gate and the cathode of the gate turn-off thyristor; and a wide on-gate command signal which is one input is turned on. And, when the output of the first AND circuit, which is the other input, is a signal for turning off the wide ON gate signal generation circuit, an AND function of outputting an ON signal to the second bypass switch is provided. And a second AND circuit having the same.