JP2001028191A - Method for automatic erasing of non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for automatic erasing of a non-volatile semiconductor memory by which a processing time for automatic erasing can be shortened. SOLUTION: When a block memory array 4 performs automatic erasing processing of a non-volatile semiconductor memory divided into a plurality of memory blocks 41-45, write-in processing before erasing is performed for the plurality of memory blocks in parallel, setting of erasing pulse width used for automatic erasing processing is made variable, and the pulse width used finally is held in a memory block 45. When erasing processing is started with the pulse width used in the previous time and erasing pulse width becomes larger than that used in the previous time at the time of finish of erasing processing, the value is updated and held in the memory block 45.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically erasing a non-volatile semiconductor memory using a non-volatile transistor as a memory cell, and in particular, it is possible to reduce a processing time for automatically erasing stored memory data. The present invention relates to a method for automatically erasing a nonvolatile semiconductor memory.

[0002]

2. Description of the Related Art FIG. 13 uses a nonvolatile transistor having a floating gate structure as a memory cell.
11 is a flowchart showing a procedure of a process for automatically erasing a so-called nonvolatile semiconductor memory having a block memory array divided into a plurality of memory cell arrays. When automatically erasing the nonvolatile semiconductor memory (flash memory), first, in step ST1, a command is input to enter an automatic erasing mode. After this mode entry, the process proceeds to step ST2 to perform a pre-erase write process. In the pre-erase write processing, serial write is performed while sequentially incrementing addresses from the lowest address to the highest address of the entire address space of the block memory array divided into a plurality of memory cell arrays. When the write-before-erase processing is completed, the process proceeds to step ST3 to execute erase processing. In this erasing process, the erasing process for the entire block memory array or the selected memory cell array is performed using an erasing pulse having a certain time length (pulse width).

After completion of the erasing process, the process shifts to step ST4 to perform an erasing verify process. In the erase verify process, a read process is performed by applying a constant verify voltage to the gate of the memory cell. In the erase verify read process, it is checked whether the erase process in step ST3 is normally performed while incrementing the address in order from the lowest address to the highest address. If the erase verify fails, the process shifts to step ST5 to execute the pre-erase process. In the pre-re-erase process, the counter value of the number of pre-re-erase processes is incremented (X = X + 1), and it is confirmed whether or not the count value has reached the maximum value (X = 512).
When the count value reaches the maximum value, the automatic erasure is terminated as an erasure error end.

On the other hand, if the erasing error has not been completed, that is, if the count value has not reached the maximum value, when the re-erase pre-processing of step ST5 is completed, the process returns to step ST3, and the erasing process is performed again. Transition. In the erasing process, the erasing process is performed again using the erasing pulse having the same pulse width as the previous one. After the end of the erasing process, the process returns to the erasing verifying process in step ST4. In these erase (step ST3), erase verify (step ST4), and pre-re-erase processing (step ST5), the final address is reached by the erase verify in step ST4, or the pre-re-erase processing counter is executed in the re-erase pre-process in step ST5. Loop processing is performed until the count value of reaches the maximum value.

If the last address is reached in the erase verify (step ST4) process, the process proceeds to step ST6 to perform over-erase verify process. In this over-erase verify process, all the word lines in the block memory array are deselected, the memory data is read by the sense amplifier, and the verify process is performed. If a fail (error) occurs in the over-erase verify process, the over-erase error is terminated and the automatic erasure is terminated. If the over-erase verify process passes, the automatic erasure is terminated as normal termination.

As described above, in the conventional automatic erasing method for the nonvolatile semiconductor memory, in the pre-erase write processing during the automatic erasing, the block memory array of the nonvolatile memory divided into a plurality of memory cell arrays is stored in the lowest order. From the address to the highest address, writing is performed serially while incrementing the address in order. This causes an increase in the automatic erasing time.

Further, in the erasing process during the automatic erasing, an erasing pulse having a constant pulse width is used, and the erasing pulse width is always constant even if the automatic erasing process is performed a plurality of times. However, the erasing time increases as the number of times of rewriting of the nonvolatile semiconductor memory increases, and as the number of times of rewriting increases, the number of loops of erasing, erasing verify, and pre-erasing increases, and the automatic erasing time increases. Is causing it.

[0008] References which describe such pre-erase writing of a non-volatile semiconductor memory include, for example, JP-A-6-131890 and JP-A-8-1155.
No. 97 publication. In the former, in the erase operation of the nonvolatile memory in which the block memory array is divided into a plurality of memory cell arrays, based on the erase selection data stored in the erase selection data storage means, for each single memory cell array, or for a plurality of memory cell arrays. The automatic erasing time is shortened by performing erasing in a lump, and there is no description about an operation of performing pre-erase writing in parallel on each memory cell array obtained by dividing the block memory array into a plurality. In the latter case, not the pulse width of the erase pulse but the number of erase pulses and voltage information applied to the flash memory are stored and held.

[0009]

Since the conventional method for automatically erasing a nonvolatile semiconductor memory is configured as described above, an automatic erasure is performed on a nonvolatile memory in which a block memory array is divided into a plurality of memory cell arrays. In the pre-erase write processing at the time of automatic erasure, the pre-erase write processing is sequentially performed on each of the plurality of divided memory cell arrays in order. There was a problem of becoming longer.

In the erasing process at the time of automatic erasing,
Erasing and erasing verification are repeated using an erasing pulse with a fixed pulse width, and loop processing is performed until the address reaches the maximum value or the erasure count value reaches the maximum value. However, the erasing pulse width is always constant, and the erasing time becomes longer as the number of times of rewriting of the nonvolatile memory increases, and the processing time of automatic erasing becomes longer as the number of times of rewriting increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. The pre-erase write processing is performed in parallel in a plurality of memory blocks, and the pulse width of the erase pulse is made variable. An object of the present invention is to obtain a nonvolatile semiconductor memory capable of shortening an automatic erasing processing time by retaining data of a used erase pulse width in the nonvolatile semiconductor memory.

[0012]

According to the present invention, there is provided a method for automatically erasing a nonvolatile semiconductor memory, comprising the steps of: performing an automatic erasing process on a nonvolatile semiconductor memory in which a block memory array is divided into a plurality of memory blocks; In addition, the pre-erase write processing when performing the automatic batch erase processing is performed in parallel on the memory cell arrays of a plurality of memory blocks.

According to the automatic erasing method for a nonvolatile semiconductor memory according to the present invention, when performing an automatic erasing process on a nonvolatile semiconductor memory in which a block memory array is divided into a plurality of memory blocks, erasing during automatic erasing is performed. The setting of the pulse width of the erase pulse at the time of processing is made variable, and the data of the erase pulse width finally used is held in the memory cell array of a predetermined memory block.

According to the automatic erasing method for a nonvolatile semiconductor memory according to the present invention, when performing an automatic erasing process on a nonvolatile semiconductor memory in which a block memory array is divided into a plurality of memory blocks, erasing during automatic erasing is performed. Set the pulse width of the erase pulse used during processing to the previously used value, the initial value of the pulse width, or the updated value of the pulse width. When it is necessary to update the value, the value is updated and held in the memory cell array of a predetermined memory block.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing an overall configuration of a nonvolatile semiconductor memory to which the automatic erasing method according to the first embodiment of the present invention is applied. In the figure, 1 is a microsequencer, 2 is a charge pump, 3 is a memory decoder, and 4 is a block memory array, which will be described later in detail with reference to the internal configuration thereof. 5 is an address A input / output to / from this nonvolatile semiconductor memory.
An address / data / control signal latch circuit that latches (16: 0) bus, data D (15: 0) bus, and various control signals and exchanges with the micro sequencer 1. This nonvolatile semiconductor memory is roughly composed of a microsequencer 1, a charge pump 2, a memory decoder 3, a block memory array 4, and an address / data / control signal latch circuit 5.

FIG. 2 shows a list of operation modes of the nonvolatile semiconductor memory configured as described above. “Read” is an operation mode in which the number of cycles for reading data at an arbitrary address in the nonvolatile semiconductor memory is one. “Status register read” is an operation mode in which the number of cycles for reading status information of automatic erasure / automatic writing is two. This “status register read” is performed on data D (15: 0)
The mode is entered by the command 70H input from the bus, and the mode is returned by FFH. "Status register clear" is an operation mode in which the number of cycles is 1 for clearing the contents of the status register. This "status register clear"
Is a command 5 input from the data D (15: 0) bus
Enter the mode at 0H. "Automatic write" is a command 40H input from the data D (15: 0) bus.
This is an operation mode in which the number of cycles is 2, in which a setup mode is entered, the write data and an address are fetched in the next cycle, and the mode entry is performed. This "auto-write"
After the end of writing, the write status is written to the status register. The "automatic batch erasing" is an operation mode in which the setup mode is entered by a command 20H input from the data D (15: 0) bus, and the mode is entered by the confirmation command 20H in the next cycle. After the "automatic batch erasure" is completed, the batch erasure status is written to the status register. "Automatic block erase"
Is a command 2 input from the data D (15: 0) bus
0H, enter the setup mode, and in the next cycle D0
H / operation mode in which the number of cycles is 2 for fetching a block address and mode entry. After the “automatic block erase” is completed, the automatic block erase status is written to the status register.

Next, the micro sequencer 1 will be described. FIG. 3 is a block diagram showing an internal configuration of the micro sequencer 1 in the nonvolatile semiconductor memory shown in FIG. In the figure, 11 is a command port, 12 is a status register, 13 is an automatic erase sequencer, 14 is an automatic write sequencer, 15 is a test mode sequencer, 16 is a power reset circuit, 17 is a clock generation circuit, and 18 is a decoder / charge pump control. This is a signal generation circuit, and the micro sequencer 1 is formed by these components.

The command port 11 sets various modes on the basis of information sent from the address / data / control signal latch input circuit 5, and sets the charge pump 2, the memory decoder 3, and the block memory array 4. The control is performed. The status register 12 is a register for holding a status state at the time of automatic erasure / automatic writing, and outputs the held value to the outside via the command port 11 if necessary.

The automatic erase sequencer 13 is a sequencer for controlling an automatic erase operation in accordance with an instruction from the command port 11. At this time, the control of the charge pump 2, the memory decoder 3, and the block memory array 4 is performed via the decoder / charge pump control signal generation circuit 18. The status state at the time of the automatic erase / automatic write operation is written to the status register 12. The automatic write sequencer 14 is a sequencer that controls an automatic write operation in accordance with an instruction from the command port 11. At this time, the control of the charge pump 2, the memory decoder 3, and the block memory array 4 is performed via the decoder / charge pump control signal generation circuit 18. The status state at the time of the automatic writing operation is written to the status register 12. The test mode sequencer 15 is a sequencer that controls the operation in the test mode according to an instruction from the command port 11. At this time, the control of the charge pump 2, the memory decoder 3, and the block memory array 4 is performed via the decoder / charge pump control signal generation circuit 18.

The power reset circuit 16 resets the power supply in accordance with an instruction from the command port 11, and makes all circuits inactive. Clock generation circuit 1
7 outputs a clock pulse corresponding to 10 MHz to the automatic erase sequencer 13, the automatic write sequencer 14, and the test mode sequencer 15. In addition,
When all the circuits are brought into a non-operation state by the power reset circuit 16, the function of the clock generation circuit 17 also stops and the clock signal also stops. The decoder / charge pump control signal generation circuit 18
3, receiving the outputs of the automatic write sequencer 14 and the test mode sequencer 15 to generate control signals for controlling the charge pump 2, the memory decoder 3, and the block memory array 4.

Next, the charge pump 2 will be described. FIG. 4 is a block diagram showing an internal configuration of the charge pump 2 in the nonvolatile semiconductor memory shown in FIG. In the figure, 21 is a -11V charge pump, 22
Is a +10 V charge pump, 23 is a +5 V charge pump, and 24 is a voltage switching circuit. The charge pump 2 is constituted by these components, and is controlled by the micro sequencer 1, and has a -11V charge pump 21,
Outputs of the +10 V charge pump 22 and the +5 V charge pump 23 are supplied to the memory decoder 3 and the block memory array 4.

The -11V charge pump 21 is a negative charge pump for erasing, and generates a negative voltage of -11V during automatic erasing. The +10 V charge pump 22 is a positive charge pump for writing / erasing, and generates a voltage of +10 V at the time of writing and a voltage of +7 V at the time of erasing. The +5 V charge pump 23 is a positive charge pump for reading / verifying,
A voltage of 5 V is generated, and a voltage of +6.5 V is generated during write / write verify. The voltage switching circuit 24 switches the outputs of the -11V charge pump 21, + 10V charge pump 22, and + 5V charge pump 23 to supply the outputs to the memory decoder 3 and the block memory array 4.

Next, the memory decoder 3 and the block memory array 4 will be described. FIG. 5 is a block diagram showing an internal configuration of the memory decoder 3 and the block memory array 4 in the nonvolatile semiconductor memory shown in FIG. In the memory decoder 3 in FIG.
(Column) address input buffer latch, 32 is an X (row) address latch, 33 is a block address latch, 34 is a Y (column) address predecoder, 35
Is an X (row) address predecoder, and 36 is a block address predecoder. The memory decoder 3 includes the latches 31 to 33 and the predecoders 34 to 36.

The Y address input buffer latch 31 latches the Y address portion in the 17-bit address A (16: 0) sent from the micro sequencer 1, and the X address latch 32 stores the 17 bit address. Latching the X address portion in the address A (16: 0). The block address latch 33 stores the above 1
This latches the block address portion in the 7-bit address A (16: 0). The Y address predecoder 34 performs a predecoding process on the address latched by the Y address input buffer latch 31 and outputs the predecoded address to the block memory array 4. The pre-decoding process of the address latched by the address latch 32 is performed, and the pre-decoded address is output to the block memory array 4. The block address predecoder 36 performs predecoding of the address latched by the block address latch 33 and outputs the predecoded address to the block memory array 4.

In the block memory array 4 in the figure, reference numeral 41 denotes a 32 KB memory cell array, a sense amplifier / write circuit, a data switching circuit, and a # 0 memory block comprising an X decoder and a Y decoder. Reference numeral 43 denotes a 32 KB # 2 memory block having the same configuration, and reference numeral 43 denotes a 32 KB # 3 memory block having the same configuration. 45 is an 8 KB memory cell array,
This is a # 4 memory block including a sense amplifier / write circuit, a data switching circuit, an X decoder, and a Y decoder. The block memory array 4 is formed by these # 0 memory blocks 41 to # 4 memory blocks 45.

FIG. 6 shows an address space of the block memory array 4. As shown in FIG. 6, the memory cell array of the # 0 memory block 41 is “00” in hexadecimal notation.
000H ”to“ 07FFFH ”.
The memory cell array of the # 1 memory block 42 has an address space of “08000H” to “0FFFFH” in hexadecimal notation. The memory cell array of the # 2 memory block 43 is represented by hexadecimal notation "10000H" to "17FFFH".
Address space. The memory cell array of the # 3 memory block 44 is “18000H” to “1” in hexadecimal notation.
FFFFH ”. The memory cell array of the # 4 memory block 45 is“ 0000 ”in hexadecimal notation.
It has an address space of “0H” to “01FFFH.” The access to the # 4 memory block 45 is output from the micro sequencer 1 because the address overlaps with a part of the address of the # 0 memory block 41. The access is performed using a control signal (# 4 memory block access signal).

FIG. 7 is a circuit diagram showing a detailed configuration of # 0 memory block 41 to # 4 memory block 45 in block memory array 4 shown in FIG. In the figure, 46 is a Y decoder, 47 is an X decoder, and 48 is
Is a sense amplifier / write circuit, and 49 is a memory cell array.

The Y decoder 46 receives the output from the Y address predecoder 34 of the memory decoder 3 and receives control signals CS0 to CS0 for selecting one bit line from the 256 bit lines BL0 to BL255. CS255
Is generated. The X decoder 47 receives an output from the X address predecoder 35, and selectively controls one of the 128 word lines WL0 to WL127. The sense amplifier / write circuit 48
The read / write of the memory cells of the selected word lines WL0 to WL127 is performed by controlling signals CS0 to CS25.
5 is performed in order from the bit lines BL0 to BL255 selected. Switching transistors Tr0-T
r255 is for sequentially selecting one bit line BL0 to BL255 based on the control signals CS0 to CS255 and connecting it to the sense amplifier / write circuit 48.

The memory cell array 49 includes memory cells Tr0-0 to Tr0-255 and Tr1-0 to Tr1-2 formed of nonvolatile transistors having floating gates.
55, Tr2-0 to Tr2-255, Tr3-0 to Tr
3-255,..., Tr127-0 to Tr127-255
Are arranged in a matrix. Of the memory cells, memory cells Tr0-0 to Tr0 arranged in the same row
127-0, Tr0-1 to Tr127-1, Tr0-2
... Tr127-2, ..., Tr0-255 to Tr127-
255, the same bit lines BL0 to BL255 are connected to the source terminals of the transistors, and different word lines WL0 to WL127 are connected to the gate terminals of the transistors.

The reading of the memory data is performed according to the outputs of the Y address predecoder 34 and the X address predecoder 35 and the bit lines BL0 to BL255 and the word line WL0.
To WL127, and is connected to the selected bit line and word line in the memory cell array 49, and the memory cells Tr0-0 to Tr127- are formed by nonvolatile transistors having floating gates.
0, Tr0-1 to Tr127-1, Tr0-2 to Tr1
27-2,..., Tr0-255 to Tr127-255 are output to the data bus via the sense amplifier of the sense amplifier / write circuit 48. The writing of the memory data is performed according to the outputs of the Y address predecoder 34 and the X address predecoder 35.
One memory cell is selected from each of the BL255 and the word lines WL0 to WL127, and the memory cells Tr0-0 to Tr127- each formed of a nonvolatile transistor having a floating gate connected to the selected bit line and the word line in the memory cell array 49. 0, Tr0-1 to Tr127
-1, Tr0-2 to Tr127-2, ..., Tr0-25
The value of the data bus is written to the Trs 127 to 255 through the write circuit of the sense amplifier / write circuit 48.

Next, the operation will be described. First, automatic batch erasing of the nonvolatile semiconductor memory will be described with reference to FIG. FIG. 8 is a block diagram showing the internal configuration of the automatic erase sequencer 13 forming the microsequencer 1 of this nonvolatile semiconductor memory. In the figure, 51 is an automatic erase sequence control circuit, 52 is a write control circuit before erase, 53 is an erase / erase verify control circuit, 54 is an over-erase verify control circuit, 55 is a write signal generation circuit before erase, and 56 is an address incrementer. 57, an erase verify circuit; 58, an erase pulse generation circuit / erase pulse width write circuit; and 59, an over-erase verify circuit. The automatic erasing sequencer 13 includes these circuits 51 to 59
Is formed by

The automatic erase sequence control circuit 51 receives control signals from the command port 11, the clock generation circuit 17, and the power reset circuit 16 in the micro sequencer 1, and when the nonvolatile semiconductor memory enters the automatic erase mode, It controls the pre-erase write control circuit 52, the erase / erase verify control circuit 53, and the over-erase verify control circuit 54. The pre-erase write control circuit 52
Upon receiving a signal from the automatic erase sequence control circuit 51,
It controls the pre-erase write processing for the block memory array 4. The pre-erase write control circuit 52 uses an address incrementer 56 to
While incrementing the address from the lowest address to the highest address, the pre-erase write signal generation circuit 55
, A write-before-erase signal is generated to perform write-before-erase processing. Here, at the time of the automatic batch erasing operation, the pre-erase write processing is performed in the # 0 memory block 41,
# 1 memory block 42, # 2 memory block 43, #
Since the operations are performed in parallel on each memory cell array 49 of the three memory blocks 44, the # 0 block write signals 60, #
All the one-block write signal 61, the # 2 block write signal 62, and the # 3 block write signal 63 are made valid. On the other hand, at the time of the automatic block erase operation, only the write signal of the target memory block is valid.

The address incrementer 56 sets the address to 0 during automatic batch erasing or automatic block erasing when the # 0 memory block 41, # 1 memory block 42, # 2 memory block 43, and # 3 memory block 44 are selected.
Increment from 0000H to 1FFFFH,
At the time of automatic block erasing when the # 4 memory block 45 is selected, the address is incremented from 00000H to 01FFFH. The pre-erase write signal generation circuit 55 performs automatic batch erasing or # 0 memory block 41, # 1 memory block 42, # 2 memory block 4
3, # 0 block write signal 60, # 1 block write signal 61, # 2 block write signal 6 at the time of automatic block erasure when # 3 memory block 44 is selected
2, # 3 block write signal 63 and # 4 in automatic block erase when # 4 memory block 45 is selected
It generates a pre-erase write signal such as a block write signal 64.

The erase / erase verify control circuit 53 receives a signal from the automatic erase sequence control circuit 51 and controls erasure and erase verify processing. After the erase operation, the erase verify circuit 57 reads the memory data, compares it with an expected value, and checks whether or not the data has been erased. This memory data reading process uses the address incrementer 56 to change the address from the lowest address to the highest address (00000H to 1).
FFFFH), and sequentially. The erase pulse generation circuit / erase pulse width write circuit 58
The erase pulse width is determined by reading the value of the erase pulse width registered in the # 4 memory block 45, and an erase pulse is generated. When the erase pulse width is updated, data of the erase pulse width is also written to the # 4 memory block 45. Thus, the erase pulse generation circuit / erase pulse width write circuit 58
Are # 0 memory blocks 41 to # 4 memory block 45
Function as a pulse width updating means for setting the pulse width of the erase pulse used for automatically erasing the data of each memory cell array 49 to be changeable.

The over-erase verify control circuit 54 receives the signal from the automatic erase sequence control circuit 51 and controls the over-erase verify process. In this over-erase verify process, all the word lines WL0 to WL127 in the memory cell array 49 are set to a non-selected state, and reading is performed by the sense amplifier of the sense amplifier / write circuit 48. The over-erase verify circuit 59 sequentially compares the read result with the expected value while incrementing the address by the address incrementer 56.

Next, the operation of the automatic batch erasing of the nonvolatile semiconductor memory will be described with reference to the flowchart shown in FIG. In the automatic batch erase in this case, the memory cell arrays 49 of all the memory blocks of the # 0 memory block 41, the # 1 memory block 42, the # 2 memory block 43, and the # 3 memory block 44 are targeted.

When the automatic batch erasure starts, first, in step ST11, a setup mode is entered by a first command 20H input from the data D (15: 0) bus, and then the process proceeds to step ST12, where a confirmation command is input. The mode is entered by the second command 20H. When this mode entry is completed, the process proceeds to step ST13, and shifts to the pre-erase write phase. In the pre-erase write phase, the data “1” generated by the pre-erase write signal generation circuit 55 of the automatic erase sequencer 13 is transferred to the # 0 memory block 41, # 1 memory block 42, # 2 memory block 43, and # 3. An operation of writing in parallel to all memory bits of each memory cell array 49 of the memory block 44 is performed. After the pre-erase write phase in step ST13 is completed, the process proceeds to step ST14 and shifts to the erase phase. In this erasing phase, in the erasing pulse generation circuit / erasing pulse width writing circuit 58, the default erasing pulse width of 1 ms or # 4 of the block memory array 4 in which the erasing pulse width used in the previous erasing process is stored.
It decides to use any of the data values of the erase pulse width read from the memory block 45, and generates an erase pulse with the pulse width. The erasing process is performed using the erasing pulse.

After the erasing phase is completed, step ST
The process proceeds to step 15 to shift to the erase verify phase. In this erase verifying phase, the address verifying circuit 57 is sequentially incremented from the lowest address (00000H) to the highest address (1FFFFH) using the address incrementer 56.
Verify whether the erase verify process, that is, the erase process in step ST14 is normally performed.
If a verify fail occurs in the erase verify phase in step ST15, the process proceeds to step ST16 to shift to the pre-erase pre-processing phase in order to perform re-erase. In this pre-re-erase processing phase, it is confirmed whether or not the count value of the number of pre-re-erase processings has reached the maximum value (X = 512). If the count value has not reached the maximum value, in step ST17, the erase pulse width is updated to a value increased by 1 ms (erase pulse width =
After performing (erasing pulse width + 1 ms) processing and incrementing the count value of the number of pre-re-erasing processings (X = X + 1), the processing returns to the erasing phase of step ST14. In the current erasing phase, the erasing operation is performed again using the erasing pulse width updated in the re-erasing pre-processing phase.
After the end of the erasing phase in step ST14, the process again proceeds to step ST15 to shift to the erase verify phase. In the erase verify phase, the erase verify process is restarted from the address where the previous erase verify failed.

The erasing phase, the erasing verifying phase, and the pre-re-erasing processing phase are either completed in the erasing verifying phase (step ST15) or completed in the re-erasing pre-processing phase (step ST16). Loop processing is continued until the count value of the number of pre-erase processing reaches the maximum value (X = 512). If it is detected in the pre-re-erase processing phase in step ST16 that the count value of the number of pre-re-erase processings has reached the maximum value (X = 512), the automatic batch erasing processing is terminated as an erasure error end. I do. If the erase verify has reached the final address in the erase verify phase in step ST15, the process proceeds to step ST18, where the over-erase verify circuit 59 performs the process of the over-erase verify phase. In this over-erase verify phase, # 0
All the word lines WL0 to WL127 of the memory cell array 49 in the memory blocks 41 to # 3 memory block 44 are set to the non-selected state, and the memory data is read by the sense amplifier of the sense amplifier / write circuit 48 to perform the over-erase verify processing. . This over-erase verify process
This is performed while the address is incremented by the address incrementer 56.

If a fail (error) occurs in the over-erase verify process, the over-erase error is terminated, and the automatic batch erasure process is terminated. If the over-erase verify process has passed, the process proceeds to step ST19 to shift to the erase pulse width writing phase. In the erase pulse width writing phase, the value of the pulse width of the erase pulse finally used in the erase phase is written to the memory cell array 49 of the # 4 memory block 45 by the erase pulse generation circuit / erase pulse width write circuit 58. Perform the operation. When the erase pulse width writing phase ends, the automatic batch erasing process ends as normal end.

Next, in this nonvolatile semiconductor memory, # 0
The operation of automatic block erasure for any one of the memory block 41, the # 1 memory block 42, the # 2 memory block 43, and the # 3 memory block 44 will be described with reference to the flowchart of FIG. When the automatic block erase starts, first, in step ST21, the first command 20 input from the data D (15: 0) bus is input.
H to enter the setup mode, and then to step ST22
The mode is entered by taking in the second command D0H of the confirmation command and the block address. Upon completion of this mode entry, the flow shifts to the pre-erase write phase in step ST23. In the pre-erase write phase, the data “1” generated by the pre-erase write signal generation circuit 55 of the automatic erase sequencer 13 is used.
To # 0 memory block 41 and # 1 memory block 4
2, an operation of writing to a memory bit of the memory cell array 49 of either the # 2 memory block 43 or the # 3 memory block 44 is performed. After the end of the pre-erase write phase, the process proceeds to step ST24 and shifts to the erase phase. In this erasing phase, the erasing pulse generation circuit / erasing pulse width writing circuit 58
The erase pulse width is determined by using either the default erase pulse width of 1 ms or the data value of the erase pulse width read from the # 4 memory block 45 in which the erase pulse width used in the previous erase process is stored. Generate
The erasing process is performed using the erasing pulse.

When the erasing phase is completed, the process proceeds to step ST25, and shifts to the erase verifying phase. In the erase verify phase, the erase verify circuit 57 performs the erase verify process while incrementing the address from the lowest address (00000H) to the highest address (1FFFFH) by the address incrementer 56. If a verify fail occurs in the erase verify phase, the process proceeds to step ST26 to perform a re-erase, and shifts to a pre-erase process phase. In this pre-re-erase processing phase, it is confirmed whether or not the count value of the number of pre-re-erase processings has reached the maximum value (X = 512). If the count value has not reached the maximum value, in step ST27, the erase pulse width is updated to a value increased by 1 ms (erase pulse width =
After performing (erasing pulse width + 1 ms) processing and incrementing the count value of the number of pre-re-erasing processings (X = X + 1), the processing returns to the erasing phase of step ST24. In the current erasing phase, the erasing operation is performed again using the erasing pulse width updated in the re-erasing pre-processing phase.
After the end of the erasing phase, the process shifts again to the erasing verification phase in step ST25. In this erase verify phase, erase verify is restarted from the address where the previous erase verify failed.

The erase phase, the erase verify phase, and the pre-re-erase processing phase are performed by performing the erase verify up to the last address in the erase verify phase, or by counting the number of re-erase pre-processes in the re-erase pre-process phase. Is continued until the maximum value (X = 512) is reached. If it is detected in the pre-erasure pre-processing phase in step ST26 that the count value of the number of pre-erasure pre-processing times has reached the maximum value (X = 512), the processing of the automatic block erasure is terminated as an erasure error end. Also, in the erase verification phase of step ST25, when the erase verification has proceeded to the final address, the process proceeds to step ST28, and the over-erase verification circuit 59 performs the processing of the over-erase verification phase. In this over-erase verify phase, all the word lines WL0 to WL127 of the memory cell array 49 of the target memory block in the block memory array 4 are deselected, and the memory data is sent to the sense amplifier of the sense amplifier / write circuit 48. Read and over-erase verify processing are performed. The over-erase verify process is performed while incrementing the address.

If the over-erase verify process fails, the over-erase error is terminated and the automatic block erase process is terminated. If the over-erase verify process is passed, the process proceeds to step ST29 to shift to the erase pulse width writing phase. In the erase pulse width writing phase, an operation of writing the information of the erase pulse width finally used in the erase phase from the erase pulse generating circuit / erase pulse width writing circuit 58 to the memory cell array 49 of the # 4 memory block 45 is performed. When the erase pulse width writing phase ends, the automatic block erase processing is terminated as normal termination.

Next, in this nonvolatile semiconductor memory, # 4
The operation of the automatic block erase for the memory block 45 will be described with reference to the flowchart of FIG. When the automatic block erase starts, first, at step ST
At 31, a setup mode is entered by a first command 20 H input from the data D (15: 0) bus, and then the process proceeds to step ST 32 to enter a mode by taking in a second command D 0 H of a confirmation command and a block address. . Upon completion of this mode entry, the flow shifts to the pre-erase write phase in step ST33. In the pre-erase write phase, an operation of writing the data “1” generated by the pre-erase write signal generation circuit 55 of the automatic erase sequencer 13 to the memory bits of the memory cell array 49 of the # 4 memory block 45 is performed. After the end of the pre-erase write phase, the process proceeds to step ST34 to shift to the erase phase. In this erasing phase, the erasing pulse generation circuit / erasing pulse width writing circuit 58 uses the default erasing pulse width 1
An erase pulse is generated using an erase pulse width of ms.
The erasing process is performed using the erasing pulse.

When the erasing phase is completed, the process proceeds to step ST35, and shifts to the erase verifying phase. In the erase verify phase, the erase verify circuit 57 performs the erase verify process while incrementing the address from the lowest address (00000H) to the highest address (1FFFFH) by the address incrementer 56. If a verify fail occurs during this erase verify phase, to perform re-erase,
The process proceeds to step ST36 to shift to the pre-erasing pre-processing phase. In this pre-re-erase processing phase, it is confirmed whether or not the count value of the number of pre-re-erase processings has reached the maximum value (X = 512). If the count value has not reached the maximum value, in step ST37, the erase pulse width is updated to a value obtained by increasing the erase pulse width by 1 ms (erase pulse width = erase pulse width + 1 ms), and the count value of the number of pre-reerase processing is incremented. After (X = X + 1), the process proceeds to step S
The process returns to the erasing phase of T34. In the current erasing phase, the erasing operation is performed again using the erasing pulse width updated in the re-erasing pre-processing phase. After the end of the erasing phase, the process returns to the erase verifying phase in step ST35. In the erase verify phase, the erase verify process is restarted from the address where the previous erase verify failed.

The erase phase, the erase verify phase, and the pre-re-erase processing phase are performed by performing erase verify up to the final address in the erase verify phase, or by counting the number of pre-re-erase processes in the re-erase pre-process phase. Is continued until the maximum value (X = 512) is reached. In the pre-re-erase processing phase in step ST36, when it is detected that the count value of the number of pre-re-erase processings has reached the maximum value (X = 512), the automatic block erasure of the # 4 memory block 45 is regarded as an erasure error end. Is completed. In addition, in the erase verify phase of step ST35, when the erase verify advances to the final address, the process proceeds to step ST38, where the over-erase verify circuit 59 performs the process of the over-erase verify phase. In this over-erase verify phase, all the word lines WL0 to WL127 of the memory cell array 49 in the # 4 memory block 45 are deselected, and the memory data is read by the sense amplifier of the sense amplifier / write circuit 48, and the over-erase verify is performed. Is performed. The over-erase verify process is performed while incrementing the address by the address incrementer 56. If the over-erase verify process fails, the process of automatic block erasure of the # 4 memory block 45 is terminated as an over-erase error end. If the over-erase verify process passes, the automatic block erase process of the # 4 memory block 45 is terminated as normal termination.

FIG. 12 shows the data of the pulse width of the erase pulse, the memory address value holding the pulse width of the erase pulse at the time of automatic batch erasure, read and written to the memory cell array 49 of the # 4 memory block 45, and # FIG. 9 is an explanatory diagram showing memory address values in which the pulse widths of the erase pulses of the 0 memory block 41, the # 1 memory block 42, the # 2 memory block 43, or the # 3 block 44 are held. This nonvolatile semiconductor memory can read and write one word (16 bits) of memory data per address.

The data of one word (D15 to D0) of the pulse width of the erase pulse at the time of the above-mentioned automatic batch erase is the address 000 of the memory cell array 49 of the # 4 memory block 45.
It is kept at 00H. When all the values of the 16-bit data held at the address 00000H of the memory cell array 49 are 0, the erase pulse width is set to 1 ms (initial value). When only the value of the D0 bit data in one word is 1, the erase pulse width is set to 2 ms. When only the D1 bit in one word is 1, the erase pulse width is set to 3 ms. Have been. Similarly, when only the D2 bit in one word is 1, the erase pulse width is 4 ms. When only the D3 bit is 1, the erase pulse width is 5 ms. When only the D4 bit is 1, the erase pulse is erased. When the pulse width is 6 ms, the erase pulse width is 7 ms when only the D5 bit is 1, the erase pulse width is 8 ms when only the D6 bit is 1, and the erase pulse width when only the D7 bit is 1. Is 9 ms, if only D8 bit is 1, the erase pulse width is 10 ms, and only D9 bit is 1
, The erase pulse width is 11 ms, when only the D10 bit is 1, the erase pulse width is 12 ms, when only the D11 bit is 1, the erase pulse width is 13 ms,
When only 12 bits are 1, the erase pulse width is 14 ms
When only the D13 bit is 1, the erase pulse width is 1
The erase pulse width is set to 5 ms, the erase pulse width is set to 16 ms when only the D14 bit is 1, and the erase pulse width is set to 17 ms when only the D15 bit is 1.

Also, one word (D15) of the pulse width of the erase pulse at the time of the automatic block erase of the # 0 memory block 41 is used.
To D0) are held at the address 00001H of the memory cell array 49 of the # 4 memory block 45.
When all the values of the 16-bit data held at the address 00001H of the memory cell array 49 are 0, the erase pulse width is set to 1 ms. When only the value of the D0 bit data in one word is 1, the erase pulse width is set to 2 ms. When only the D1 bit in one word is 1, the erase pulse width is set to 3 ms. Have been. Similarly, when only the D2 bit in one word is 1, the erase pulse width is 4 ms. When only the D3 bit is 1, the erase pulse width is 5 ms. When only the D4 bit is 1, the erase pulse is erased. When the pulse width is 6 ms, the erase pulse width is 7 ms when only the D5 bit is 1, the erase pulse width is 8 ms when only the D6 bit is 1, and the erase pulse width when only the D7 bit is 1. To 9ms, D8
When only the bit is 1, the erase pulse width becomes 10 ms,
When only D9 bit is 1, the erase pulse width is 11 ms
When only the D10 bit is 1, the erase pulse width is 1
2 ms, the erase pulse width is 13 ms when only the D11 bit is 1, the erase pulse width is 14 ms when only the D12 bit is 1, and the erase pulse width is 15 ms when only the D13 bit is 1. When only the D14 bit is 1, the erase pulse width is set to 16 ms, and when only the D15 bit is 1, the erase pulse width is set to 17 ms.

Also, one word (D15) of the pulse width of the erase pulse at the time of the automatic block erase of the # 1 memory block 42 is used.
To D0) are held at the address 00002H of the memory cell array 49 of the # 4 memory block 45.
When all the values of the 16-bit data held at the address 00002H of the memory cell array 49 are 0, the erase pulse width is set to 1 ms. When only the value of the D0 bit data in one word is 1, the erase pulse width is set to 2 ms. When only the D1 bit in one word is 1, the erase pulse width is set to 3 ms. Have been. Similarly, when only the D2 bit in one word is 1, the erase pulse width is 4 ms. When only the D3 bit is 1, the erase pulse width is 5 ms. When only the D4 bit is 1, the erase pulse is erased. When the pulse width is 6 ms, the erase pulse width is 7 ms when only the D5 bit is 1, the erase pulse width is 8 ms when only the D6 bit is 1, and the erase pulse width when only the D7 bit is 1. To 9ms, D8
When only the bit is 1, the erase pulse width becomes 10 ms,
When only D9 bit is 1, the erase pulse width is 11 ms
When only the D10 bit is 1, the erase pulse width is 1
2 ms, the erase pulse width is 13 ms when only the D11 bit is 1, the erase pulse width is 14 ms when only the D12 bit is 1, and the erase pulse width is 15 ms when only the D13 bit is 1. When only the D14 bit is 1, the erase pulse width is set to 16 ms, and when only the D15 bit is 1, the erase pulse width is set to 17 ms.

Also, one word (D15) of the pulse width of the erase pulse at the time of the automatic block erase of the # 2 memory block 43 is used.
To D0) are held at the address 00003H of the memory cell array 49 of the # 4 memory block 45.
When all the values of the 16-bit data held at the address 00003H of the memory cell array 49 are 0, the erase pulse width is set to 1 ms. When only the value of the D0 bit data in one word is 1, the erase pulse width is set to 2 ms. When only the D1 bit in one word is 1, the erase pulse width is set to 3 ms. Have been. Similarly, when only the D2 bit in one word is 1, the erase pulse width is 4 ms. When only the D3 bit is 1, the erase pulse width is 5 ms. When only the D4 bit is 1, the erase pulse is erased. When the pulse width is 6 ms, the erase pulse width is 7 ms when only the D5 bit is 1, the erase pulse width is 8 ms when only the D6 bit is 1, and the erase pulse width when only the D7 bit is 1. To 9ms, D8
When only the bit is 1, the erase pulse width becomes 10 ms,
When only D9 bit is 1, the erase pulse width is 11 ms
When only the D10 bit is 1, the erase pulse width is 1
2 ms, the erase pulse width is 13 ms when only the D11 bit is 1, the erase pulse width is 14 ms when only the D12 bit is 1, and the erase pulse width is 15 ms when only the D13 bit is 1. When only the D14 bit is 1, the erase pulse width is set to 16 ms, and when only the D15 bit is 1, the erase pulse width is set to 17 ms.

One word (D15) of the pulse width of the erase pulse at the time of the automatic block erase of the # 3 memory block 44 is used.
To D0) are held at the address 00004H of the memory cell array 49 of the # 4 memory block 45.
When all the values of the 16-bit data held at the address 00004H of the memory cell array 49 are 0, the erase pulse width is set to 1 ms. When only the value of the D0 bit data in one word is 1, the erase pulse width is set to 2 ms. When only the D1 bit in one word is 1, the erase pulse width is set to 3 ms. Have been. Similarly, when only the D2 bit in one word is 1, the erase pulse width is 4 ms. When only the D3 bit is 1, the erase pulse width is 5 ms. When only the D4 bit is 1, the erase pulse is erased. When the pulse width is 6 ms, the erase pulse width is 7 ms when only the D5 bit is 1, the erase pulse width is 8 ms when only the D6 bit is 1, and the erase pulse width when only the D7 bit is 1. To 9ms, D8
When only the bit is 1, the erase pulse width becomes 10 ms,
When only D9 bit is 1, the erase pulse width is 11 ms
When only the D10 bit is 1, the erase pulse width is 1
2 ms, the erase pulse width is 13 ms when only the D11 bit is 1, the erase pulse width is 14 ms when only the D12 bit is 1, and the erase pulse width is 15 ms when only the D13 bit is 1. When only the D14 bit is 1, the erase pulse width is set to 16 ms, and when only the D15 bit is 1, the erase pulse width is set to 17 ms.

Updating of the erasing pulse width at the time of automatic batch erasing in step ST17 of FIG. 9 or updating of the erasing pulse width at the time of automatic block erasing of the # 0 memory blocks 41 to # 3 memory block 44 in step ST27 of FIG. This is performed by writing 1 to the data of the pulse width of the erase pulse held in the addresses 00000H to 00004H of the memory cell array 49 of the # 4 memory block 45, and thereafter shifting the position of 1 sequentially.

In the above description, the case where the pulse width of the erase pulse is updated from the initial value of 1 ms in increments of 1 ms has been described, but the present invention is not limited to this. For example, if the pulse width of the erase pulse is N
(N is a real number), and the increment is K (K is a real number), and N = N
The update may be performed in accordance with + K, and the increment K may not necessarily be a fixed value.

[0056]

As described above, according to the present invention, when performing the automatic batch erasing process on the nonvolatile semiconductor memory obtained by dividing the block memory array into a plurality of memory blocks, the pre-erase writing is performed. Since the processing is configured to be performed in parallel by the memory cell array of a plurality of memory blocks, the pre-erase write processing is performed at a time in the memory cell array of a plurality of memory blocks, and the automatic erasing time can be reduced. There is an effect that an automatic erasing method for a nonvolatile semiconductor memory can be realized.

According to the present invention, the pulse width of the erase pulse used when performing the automatic block erase and the automatic batch erase processing on the nonvolatile semiconductor memory obtained by dividing the block memory array into a plurality of memory blocks. Can be set variably, and the data of the pulse width of the erase pulse finally used is stored in a predetermined memory cell array in the memory block. At the time of processing, the processing can be performed using the value held in the memory cell array of the predetermined memory block as the pulse width of the erasing pulse to be used, so that the time for the second and subsequent automatic erasing can be reduced. There is an effect that it can be realized.

According to the present invention, the pulse width of the erase pulse used when performing the automatic block erase and the automatic batch erase processing on the nonvolatile semiconductor memory obtained by dividing the block memory array into a plurality of memory blocks. Is set to the value used last time, the initial value of the pulse width, or the updated value of the pulse width.
When the previously set erase pulse width value needs to be updated, the value is updated and held in the memory cell array of a predetermined memory block, so that the time for automatic erase can be reduced. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire configuration of a nonvolatile semiconductor memory to which an automatic erasing method according to a first embodiment of the present invention is applied;

FIG. 2 is an explanatory diagram showing an operation mode list of the nonvolatile semiconductor memory according to the first embodiment;

FIG. 3 is a block diagram illustrating an internal configuration of a microsequencer of the nonvolatile semiconductor memory according to the first embodiment;

FIG. 4 is a block diagram showing an internal configuration of a charge pump of the nonvolatile semiconductor memory according to the first embodiment;

FIG. 5 is a block diagram showing an internal configuration of a memory decoder and a block memory array of the nonvolatile semiconductor memory according to the first embodiment;

FIG. 6 is an explanatory diagram showing an address space of a block memory array of the nonvolatile semiconductor memory according to the first embodiment;

FIG. 7 is a circuit diagram showing an internal configuration of a memory block in the block memory array according to the first embodiment;

FIG. 8 is a block diagram showing an internal configuration of an automatic erase sequencer of the micro sequencer according to the first embodiment.

FIG. 9 is a flowchart showing a processing procedure of automatic batch erasing in the first embodiment.

FIG. 10 is a flowchart showing a processing procedure of automatic block erasure of # 0 memory block to # 3 memory block in the first embodiment.

FIG. 11 is a flowchart showing a processing procedure of automatic block erasure of # 4 memory block in the first embodiment.

FIG. 12 shows the data of the pulse width of the erasing pulse written to the # 4 memory block and the memory address value holding the pulse width of the erasing pulse at the time of automatic batch erasing and each automatic block erasing in the first embodiment. FIG.

FIG. 13 is a flowchart showing a processing procedure of a conventional automatic erasing method for a nonvolatile semiconductor memory.

[Description of Signs] 4 block memory array, 41 # 0 memory block, 42 # 1 memory block, 43 # 2 memory block, 44 # 3 memory block, 45 # 4 memory block, 49 memory cell array, 58 erase pulse generating circuit Erase pulse width writing circuit (pulse width updating means), Tr0-0 to Tr127-225 memory cells.

Claims (3)

[Claims] 1. A non-volatile semiconductor memory in which a plurality of memory blocks each having a memory cell array in which a plurality of memory cells each composed of a non-volatile transistor are arranged in a matrix form a block memory array. In the automatic erasing method for a nonvolatile semiconductor memory for erasing data in a memory cell array of a block, when performing an automatic block erasing process for erasing only data of a memory cell array of one memory block of the block memory array, An automatic batch erasing process of performing the pre-erase write process of writing the same data to the memory cell array of the memory block to be processed with the automatic block erasure, and erasing data of the memory cell array of all the memory blocks of the block memory array When performing the above, Automatic erase method of a nonvolatile semiconductor memory and performs the processing of pre-erase write writing the same data in parallel to all the memory cell array of the triblock. 2. A non-volatile semiconductor memory comprising a plurality of memory blocks each having a memory cell array in which a plurality of memory cells each including a non-volatile transistor are arranged in a matrix to form a block memory array. In an automatic erasing method for a nonvolatile semiconductor memory for erasing data in a memory cell array of a block, the pulse width of an erasing pulse used for automatically erasing data of a memory cell array in the memory block is determined by a pulse width updating unit. An automatic block that is set to be changeable and that individually erases data in a memory cell array of each memory block of the block memory array using an erase pulse having a pulse width independently set in each case by the pulse width updating unit. Erasing process,
An automatic batch erasing process for erasing data in the memory cell array of all the memory blocks of the block memory array at once is performed, and a pulse width of an erasing pulse used in the automatic block erasing process and the automatic batch erasing process is performed. Is written to a memory cell array of a predetermined memory block in the block memory array. 3. A nonvolatile semiconductor memory in which a plurality of memory blocks each having a memory cell array in which a plurality of memory cells each composed of a nonvolatile transistor are arranged in a matrix form a block memory array. In an automatic erasing method for a nonvolatile semiconductor memory for erasing data in a memory cell array of a block, the pulse width of an erasing pulse used for automatically erasing data of a memory cell array in the memory block is determined by a pulse width updating unit. Set to be changeable, the pulse width of the corresponding erase pulse read from the memory cell array of a predetermined memory block predetermined in the block memory array, the initial value of the pulse width of the corresponding erase pulse, and further, Of the erase pulse whose value has been updated by the pulse width updating means. The pulse width of the erase pulse to be used is set using the pulse width, and the automatic block erase processing of the memory cell array of each memory block of the block memory array or the memory cell array of all the memory blocks of the block memory array is performed. Performing an automatic batch erase process, at the end of each of the automatic block erase processes or the automatic batch erase process, a pulse of an erase pulse previously set in a memory cell array of a predetermined memory block in the block memory array. A method for automatically erasing a non-volatile semiconductor memory, characterized in that when it is necessary to update the width value, the value of the pulse width is updated and held in the memory cell array of the memory block.