JP2001027966A - Memory controller, facsimile equipment and image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of excessive waiting time even if the electric deletion requests of a physical sector are continuously inputted in a system where a flash memory is shared by plural units by appropriately processing other requests such as reading/writing. SOLUTION: In a buffer (FIFO(B)) of a FIFO system, the processing order of commands is unitarily decided. A format command instructing the deletion of the physical sector of a flash memory is preliminarily accumulated in FIFO(C). Then, the commands are transferred to FIFO(B) one by one with the absence of the format command waiting for the processing or during the processing in FIFO(B) as a condition. Such management is executed by a format command queue management part 37.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory control device,
The present invention relates to an image forming apparatus such as a facsimile machine and a digital copying machine.

[0002]

2. Description of the Related Art Flash memories are widely used in various devices as nonvolatile memories capable of storing a large amount of data.

The memory space in a flash memory is
As shown in FIG. 9A, a predetermined number of bytes (for example,
This is regarded as an aggregate of 4 Kbytes) physical sectors, and “electrical erasure” can be performed only in units of the physical sectors.

However, one physical sector is divided into blocks (for example, 1 Kbyte), and when a data erasure request is issued from a device, "logical erasure" must be performed in block units. Can be. "Logical erasure"
Is an apparent erasure in response to a data erasure request from the device, and in fact means that the block is virtually unusable. Making the block unusable is achieved, for example, by performing processing such as writing zero to the entire area of the block or setting a flag indicating unusable in the block management information.

[0005] When logical erasure is performed in units of blocks and all blocks constituting one physical sector are erased, the physical sector is electrically erased at that time.

For example, as shown on the left side of FIG.
Document data of the first page and the second page are stored in one physical sector, and when the data of the second page is logically erased, it is determined that the entire area of the physical sector has just been erased. Then, as shown on the right side of FIG. 9, the electrical erasure of the physical sector is executed at that time.

The erasure of the physical sector generally takes a considerable time (several hundred milliseconds to several seconds). In addition, when erasing the physical sector, other processes such as write / read cannot be executed, and these processes wait until the erasure of the physical sector is completed.

[0008]

It is considered that the frequency of requests for erasing physical sectors is not so high. However, as in the case of erasing data of an original document covering several pages at a time, the number of physical sector Erasing may occur continuously.

[0009] Considering a case where a flash memory is shared by a plurality of devices, when a physical sector erasure request issued from one device is continuously executed, the other devices are connected to the flash memory. Access (read / write) cannot be performed at all.

For example, when electrical erasure of a large number of physical sectors continues, data reading / writing cannot be performed for several tens of seconds in some cases, thereby causing a communication error in a communication device such as a facsimile. It is possible.

If the read / write processing is given the highest priority and the priority order is set so that the electrical erasure of the physical sector is postponed, the read / write can be performed smoothly. However, a situation may occur in which the physical sector cannot be electrically erased forever. If the physical sector cannot be erased (that is, the unnecessary data cannot be erased), the data write efficiency will deteriorate,
Once the memory area is full, no more writes can be made.

Since each device operates independently and independently to generate a request for a flash memory, it is not possible to arbitrate in advance the request for a flash memory between the devices.

The present invention has been made in view of such a problem, and even if a physical sector erasure request is continuously issued from one device, a write / read or the like generated from another device can be performed. It is another object of the present invention to appropriately process a request, enable smooth use of a shared memory, and improve processing efficiency of the entire system.

[0014]

According to the present invention, when a plurality of commands related to electrical erasure are continuous and a command other than the command related to electrical erasure exists, the command related to the electrical erasure exists. Prohibits continuous processing of commands.

As a result, even when a large number of physical sectors are continuously erased, after one erasing process is completed, processes such as read and write can be performed, and a situation in which a long process wait is required. Does not occur.

In the present invention, the processing order is desirably centrally managed in a command queue of FIFO format,
Only the command related to electrical erasure is temporarily stored separately from the command queue, and then transferred to the command queue individually. In other words, if there is a command related to electrical erasure waiting or being executed in the command queue, no further transfer to the command queue (queuing) is performed.

In this manner, other commands (commands such as write / read) generated during execution of one command related to electrical erasure are successively changed to F.
Since the next command related to electrical erasure is stored in the command queue of the IFO format and queued after that, other commands are surely inserted between commands related to electrical erasure. And automatically adjust the order of command processing without any special management.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In one aspect of the memory control device of the present invention, the order of processing commands generated independently from a plurality of devices in a memory in which electrical erasing can be performed only for each region of a predetermined size is described. When managing a plurality of commands related to the electrical erasure, if there is a command other than the command related to the electrical erasure, if there is a command other than the command related to the electrical erasure, continuous processing of the command related to the electrical erasure Ban.

As a result, even when a large number of physical sectors are continuously erased, a process such as reading or writing can be performed after one erasing process is completed, and a situation occurs in which a long waiting time is required. Absent.

Another aspect of the memory control device of the present invention relates to a memory which can be electrically erased only for each area of a predetermined size, a write command, a read command and an erase command generated independently from a plurality of devices. A memory controller that sequentially processes commands related to electrical erasure of data by a FIFO-type command queue, and temporarily stores commands related to electrical erasure of data separately from other commands. On the condition that there is no command relating to electrical erasure that is waiting for processing or is currently being executed, a configuration having command management means for queuing the temporarily stored command relating to electrical erasure in the command queue is adopted.

The processing order is centrally managed in a FIFO type command queue, and only commands relating to electrical erasure are temporarily stored separately from the command queue, and are stored separately. The method of moving to the command queue is adopted. In other words, in the command queue,
If there is a command related to electrical erasure that is waiting for processing or is being executed, no further transfer to the command queue (queuing) is performed.

In this way, other commands (commands such as write / read) generated during execution of one command related to electrical erasure are successively changed to F.
Since the next command related to electrical erasure is stored in the command queue of the IFO format and queued after that, other commands are surely inserted between commands related to electrical erasure. And automatically adjust the order of command processing without any special management.

A third aspect of the memory control device according to the present invention relates to a memory which can be electrically erased only for each area of a predetermined size, which is generated independently from a plurality of devices. A memory controller that manages and executes processing commands to be executed and other processing commands, and stores a command queue that determines the processing order of the commands.
A first buffer in an FIFO format, a second buffer in a FIFO format for preliminarily storing only a command for a process related to the electrical erasure, and a command for inputting a command related to the electrical erasure process. , Or a command for the other process, sends a command for the other process to the first buffer, and sends a command for an electrical erase process to the second buffer. The command distribution unit and the first buffer are provided with the electric power preliminarily stored in the second buffer on condition that there is no processing command waiting for processing or processing currently being executed related to electrical erasure. And buffer management means for performing a process of queuing a command of a process related to the target erasure in the first buffer.

As in the second embodiment, a method is adopted in which only commands related to electrical erasure are separately stored and transferred one by one to a FIFO buffer (command queue) that determines the processing order of the commands. By adopting this configuration, commands relating to electrical erasure can be naturally distributed without complicated management.

According to the embodiment of the present invention, when a plurality of devices share a non-volatile memory having a large storage capacity and a low price, such as a flash memory, the processing efficiency of the entire system can be improved. .

Further, by controlling the timing of queuing to the FIFO queue, the order of command processing can be easily and naturally changed, so that there is no problem such as an increase in cost. Therefore, the present invention can be applied to a device such as a popular facsimile machine that requires strict cost reduction and size reduction.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing a main configuration of a system for controlling a flash memory (and a facsimile machine including this system).

As shown, the facsimile machine 15
Is provided with a facsimile control unit 12 for overall control of facsimile communication and storage of communication data in a memory, a scanner device 13 and a printer 14, each of which is independently flashed via a bus 11. The memory 10 can be accessed.

The facsimile device 15 has a file input interface unit 1, a file output interface unit 2, a file erasure interface unit 3, a block data write unit, and a file input interface unit 1 for managing and controlling access to the flash memory 10. It has a unit 4, a block data reading unit 5, a block data erasing unit 6, a file information management unit 7, a physical sector format unit 8, and a flash memory control unit 9.

In the flash memory control unit 9 described above, a characteristic operation of the present invention is performed in which the queuing timing to the command queue in the FIFO format is changed to adjust the order of command processing. This will be described later with reference to FIG.

In the configuration shown in FIG. 1, the file input interface unit 1 receives a command for inputting (writing) file data from devices such as the facsimile control unit 12, the scanner 13, and the printer 14, and writes the write data. The file information is sent to the block data write unit 4. In addition, a process of receiving the write result and notifying the device is performed.

The file output interface unit 2
Outputs file data to devices such as the facsimile control unit 12, the scanner 13, and the printer device 14 (read).
To perform the process. That is, the read file information is sent to the block data read unit 5, and the read result is received and notified to the device.

The file erasing interface unit 3
Receives an instruction to delete a file from a device such as the facsimile control unit 12, the scanner 13, or the printer device 14, accepts the instruction, sends the deleted file information to the block data erasing unit 6, and receives the erasure result. A process for notifying the device is performed.

The block data writing section 4 sends file data and a write command to the flash memory 9 based on the file input information from the file input interface section 1 and issues commands for generating and updating file management information. The file is sent to the file information management unit 7. When the result of the write process is sent from the flash memory control unit 9, the result is notified to the file input interface unit 1.

The block data read unit 5 sends a read command to the flash memory 9 based on the file output information from the file output interface unit 2, receives the read data, and sends the read data to the file output interface unit 2. Perform the sending process. In addition, a command for updating the file management information is sent to the file information management unit 7. Further, it performs a process of sending the read result sent from the flash memory control unit 9 to the file output interface unit 2.

Further, the block data erasing section 6 sends a “block data erasing command” to the flash memory 9 based on the file erasing information from the file erasing interface section 3. The "block data erasure command" specifically instructs erasure of blocks included in the file data one by one. The flash memory controller 9 erases the designated block, and returns an erase result to the block data eraser 6 each time one block is completed. The block data erasure unit 6 receives the erasure result and sends it to the file erasure interface unit 3. In addition, a command for updating (erasing) the file management information is sent to the file information management unit 7.

Here, "erasing block data" means
This means the logical erasure in units of blocks described with reference to FIG. The “erase of block data” specifically includes erasure of data and erasure of management information. That is, the flash memory control unit 9 erases the file management information after setting the block to the unusable state. Then, the end of the erasure is notified to the device that has requested the erasure.

Further, the file information management section 7 operates the actual file management information in accordance with the instructions for generating, updating, and erasing the file management information, and integrally manages the current state of the flash memory 10 in real time. I do. Here, it should be noted that when erasing the file management information, the erased block (see FIG. 9A) is managed and grasped, and the physical sector is erased as described in FIG. 9B. When all the blocks in the block have been erased, the physical sector format unit 8 is instructed to execute the format processing of the physical sector.

The physical sector format section 8 receives a format processing command output from the file information management section 7 and instructs the flash memory control section 9 to format a specified physical sector. Here, the “formatting process” means the process of electrically erasing the physical sector described with reference to FIG. More specifically, it also includes a process of writing data indicating that the erased physical sector is in a writable state at a predetermined position in the block.

The flash memory controller 9 inputs (writes), outputs (reads), and erases (erases) data with respect to the flash memory (data storage area) 10.
And executes the process. The command processing order in the flash memory control unit 9 is basically the input order. That is, as shown in FIG. 2, if each command of the write 1, read 1, and physical sector 1 format is input in this order, the processing is performed in the input order, and the processing results are sequentially returned. That is the principle.

However, if only the control in the input order is performed, when format commands are continuously input, there is an adverse effect that other processing is waited for a long period of time. Therefore, in order to prevent this, in the present embodiment, the internal configuration of the flash memory control unit 9 is devised.

Next, the configuration of the flash memory control unit 9 and the features of its operation, which are the features of this embodiment, will be described with reference to FIGS.

As shown in FIG. 3, the flash memory control unit 9 includes a buffer reception unit 31 and a command control unit 32
, A processing result notifying unit 33, a command distribution unit 34, a processing buffer queue management unit 35, a processing command queue management unit 36, and a format command queue management unit 37.
And three FIFO (first-in first-out) type buffers (FIOs) for storing queues managed by each of these management units 35, 36, and 37.
FO (A), FIFO (B), FIFO (C)), and a command execution unit 38. FIFO (C)
Is a dedicated buffer specially provided for preliminarily storing only the format command.

Here, the buffer receiving unit 31 receives a buffer (information for securing an area necessary for storing data) for temporarily storing file data for reading or writing a block. The received buffer is stored in the F buffer under the management of the processing buffer queue management unit 35.
It is queued in IFO (A). Here, queuing refers to “accumulating processing commands in sequence”, and command queuing refers to “a sequence of accumulated commands”.
Say. The order of processing in the command queue matches the order of accumulation. That is, the command is stored in a first-in first-out format.
It may be called an IFO queue.

The command receiving section 32 receives actual processing contents (processing commands). The received processing command is sent to the command distribution unit 34.

The command distribution unit 34 classifies a physical sector format processing command (hereinafter, referred to as a “format command”) from other processing commands (hereinafter, referred to as a normal processing command). It is passed to the management queue 37, and the latter is passed to the processing command queue management unit 36. Here, the “format command” includes a physical sector erase command and a command instructing writing of a flag (write enable flag) indicating that the erased physical sector is writable.

The format commands are accumulated in the FIFO (C) by the format command queue management unit 37 and are queue-managed. Once the format command is stored in the FIFO (C),
It will be moved to O (B) so that successive format commands will be naturally distributed and processed. As a result, adjustment of the processing order with other commands is achieved. This will be specifically described later with reference to FIG.

The processing result notifying section 33 returns the processing result to each processing section instructing the processing.

Normal commands (write / read commands) managed by the processing command queue management unit 36 are sent to the command execution unit 38 in the order of input and processed. That is, the processing order of the commands is F
It is managed in a unified manner by the order of the command queue in the IFO (B).

When a block buffer is necessary for executing a command (in the case of read / write), write data is read from the block buffer corresponding to the processing command, which is managed by the processing buffer queue management unit 35, and Read data is stored in the block buffer. Since both FIFO (A) and FIFO (B) perform processing in the order of input, the processing is kept in synchronization. In other words, even without special management, the processing command and the block buffer required for the processing are naturally 1
Correspondence will be made on a one-to-one basis.

The command executing section 38 only executes the given processing command to the flash memory 9. That is, it is the processing command queue management unit 36 that performs exclusive control so as not to process a plurality of commands at the same time.

Next, the operation of the format command queue management unit 37 will be described with reference to FIGS.

As shown in FIG. 4A, the FIFO (c)
Format command FORM1 (erase A
And each command of the write flag B)
It is queued in the FIFO (B) on condition that there is no processing command in (B) or there is no format command currently being executed. The arrow in the figure indicates the format command F
This indicates that ORM1 has been moved to FIFO (B). Each command of the write C and the write D previously input is queued in the FIFO (B).

FIG. 4B shows the FIFO (B)
The processing of each command of the write C and the write D is completed, and the format command FORM1 is processed in the order.
This shows a state in which the processing has been started. Since the formatting process involves a long-time process of erasing physical sectors, it takes a considerable amount of time to complete the process.

In FIG. 4C, the characteristic operation procedure performed by the format command queue management unit 37 is as follows.
Are shown.

That is, if a new format command is sent from the command distribution unit 34 while the format command FORM1 is being processed in the FIFO (B), it is queued in the FIFO (C) (operation). .

When the processing command queue management unit 36 receives a notification that the processing of the format command FORM1 being executed has been completed (operation), the format command FORM1 is deleted from the FIFO (C) (operation). Operation, x in the figure indicates that the command has been erased).

Subsequently, a new format command (F
ORM2) is stored (operation),
The format command FORM2 is sent to the FIFO
Move to (B) (operation).

In FIG. 4C, the format command F
Since the write G and write H commands are accumulated while the ORM 1 is being executed, the format command FORM 2 is queued after the write G and write H commands.

Accordingly, as shown in FIG. 4D, the order of command processing is FORM1, write G, write H, FORM2, and other commands (write G, write H) are interposed between format commands. Will be inserted. Therefore, even when format commands are continuously input, at the stage of actual command processing, each command is distributed (divided), and processing of other commands is secured.

The distribution (division) of the format command is achieved by the fact that "there is no format command waiting or being processed in the FIFO (B)". Is a condition for transferring

That is, in the FIFO (B), the existence of two or more unprocessed (including in-process) format commands is not allowed. Therefore, during the period in which one format command is executed, If another command is entered, the newly entered command is then guaranteed to be executed reliably.

As shown in FIG. 1, the format command queue management unit 37 processes the format command () sent from the command distribution unit 34 and the format command sent from the processing command queue management unit 36. End notification () is input.

The format command queue management unit 37 determines that the format command is stored in the FIFO (C) and that there is no format command in the FIFO (B) waiting to be processed or being processed. The next format command is sent to the processing command queue management unit 36. Processing command queue management unit 36
Sends the format command to FIFO
(B), and the transfer of the format command from the FIFO (C) to the FIFO (B) is completed (the arrow indicated by the dotted line in FIG. 1).

FIG. 5 summarizes the main operations of the format command queue management unit 37 described above.

That is, when a new format command is input (step 40), this is sent to the FIFO (C).
(Step 41). Further, it is checked whether or not there has been a processing end notification from the processing command queue management unit 36 (step 42). If there is a processing end notification, the processing of the format command previously transferred to the FIFO (B) is performed by the FIFO. Since the process is completed on the (B) side, the command is similarly deleted from the FIFO (C) queue (step 43).

If a format command is stored in the FIFO (C) (step 45), the format command is stored in the processing command queue management unit 3 (step 45).
6 (step 46).

On the other hand, if there is no processing end notification in step 42 and there is a format command which has been transferred to the FIFO (B) first (step 44), the transferred format command is stored in the FIFO (B). The processing command queue management unit 3 does not proceed to step 45 because it is waiting for processing or is currently being executed.
The operation of waiting for a format command end notification from C.6 is performed.

By controlling the flash memory as described above, command processing as shown in FIG. 6 is performed.

In FIG. 6, first, commands for formatting each of the sectors 1 to 4 are successively input, and immediately thereafter, commands for write 1 and write 2 are input. Each command of 2, read 3, write 3, and write 4 is input.

A period T1 shown on the right side of FIG. 6 is a period during which the sector 1 is being formatted. In this period T1, the input commands of the write 1 and the write 2 are executed in the next processing period T2.

In the next processing period T3, the format processing of the sector 2 is performed. Each command of read 1, read 2, read 3, write 3, and write 4 inputted in this period T3 is It is executed in the processing period T4.

As described above, even when the format commands are continuously input, the format commands are not actually processed continuously, and the subsequently input write or read command is promptly executed. So
The request for access to the independent flash memory from each device shown in FIG. 1 can be fairly met, and smooth and efficient memory access can be guaranteed as a whole system.

Further, in the flash memory control device of FIG. 3, the processing order of the commands is centrally managed by the FIFO (B), and the format commands preliminarily stored in the FIFO (C) are stored in the FIFO (C) one by one. Only the very simple operation of moving to B) is performed, the execution is easy, and there is no concern about an increase in cost and complexity of the apparatus.

FIG. 7 shows a comparative example (an example not using the present invention).
3 is a diagram showing a configuration of a flash memory control unit 9 of FIG. The basic configuration is the same as in FIG. 3, but in the case of FIG.
There are only O (A) and FIFO (B), and there is no FIFO (C) for preliminarily storing format commands.

In the case of such a configuration, as shown in FIG. 8, when the format commands of the sectors 1 to 4 are continuously input, the format commands are accepted thereafter until all the format processes are completed. The command is kept waiting, and the processing efficiency of the command as a whole system is reduced. Comparing FIG. 6 with FIG. 8, it can be seen that by performing the memory management to which the present invention is applied, the disadvantage in the comparative example is completely eliminated.

In the above description, a flash memory is used. However, the present invention is not limited to this, and the present invention can be widely applied to a system using a memory that requires a long time for erasing. In the above description, the facsimile apparatus has been described. However, the present invention is not limited to this, and the present invention is widely applicable to image forming apparatuses such as digital copying machines.

[0079]

As described above, according to the present invention,
Even if commands for instructing electrical erasure of the physical sector are continuously input, in the actual processing, it is guaranteed that the subsequent write and read processing will be performed promptly, and many devices Can be used with confidence in a system to which the flash memory is connected as a file storage area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a flash memory control system according to an embodiment of the present invention;

FIG. 2 is a diagram showing a basic operation of the system shown in FIG.

FIG. 3 is a block diagram showing a configuration of a memory control device according to the embodiment of the present invention;

4A is a diagram showing an example of a queue state in a FIFO buffer; FIG. 4B is a diagram showing an example of a queue state in a FIFO buffer; FIG. 4C is a diagram showing an operation procedure of a format command queue management unit; FIG. 4 is a diagram illustrating an example of a command processing order in the embodiment.

FIG. 5 is a flowchart showing an operation procedure of a format command queue management unit;

FIG. 6 is a diagram showing an example of command processing in the system according to the embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration of a flash memory control unit according to a comparative example.

FIG. 8 is a diagram showing an example of command processing in the system of the comparative example.

9A is a diagram showing a configuration of a flash memory; FIG. 9B is a diagram for explaining an electrical erase operation of the flash memory;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 file input interface unit 2 file output interface unit 3 file erase interface unit 4 block data write unit 5 block data read unit 6 block data erase unit 7 file information management unit 8 physical sector format unit 9 flash memory control unit 10 flash memory 12 facsimile Control unit 13 Scanner device 14 Printer device

Claims (6)

[Claims] When managing the order of processing of commands generated independently from a plurality of devices in a memory in which electrical erasing can be performed only for each area of a predetermined size, a command related to the electrical erasing is managed. A memory control device for prohibiting continuous processing of commands related to electrical erasure when a plurality of commands are continuous and a command other than a command related to electrical erasure exists. 2. A write command, a read command, and a command related to erasure, which are generated independently from a plurality of devices, are sequentially transmitted to a memory in which electrical erasing can be performed only for each area of a predetermined size by a command queue of FIFO format. A memory control device for processing, wherein a command relating to electrical erasure of data is temporarily stored separately from other commands, and is waited for processing in the command queue or is currently being executed. And a command management means for queuing the temporarily stored command related to electrical erasure in the command queue on condition that there is no command related to the command. 3. A processing command related to electrical erasing and other processing commands, which are generated independently from a plurality of devices, are managed and executed for a memory in which electrical erasing can be performed only for each area of a predetermined size. A memory control device, comprising: a first buffer in a FIFO format in which a command queue for determining a processing order of a command is stored; and a second buffer in a FIFO format in which only a command of a process related to the electrical erasure is preliminarily stored. And whether the input command is a command for the electrical erasure process or a command for the other process, and sends a command for the other process to the first buffer. A command distribution unit that sends a command for an electrical erase process to the second buffer; In this case, on condition that there is no processing command related to the electrical erasure that is waiting or currently being executed, a command of the processing related to the electrical erasure that has been preliminarily stored in the second buffer is transmitted. And a buffer management unit for performing a process of queuing in the first buffer. 4. The memory control device according to claim 1, wherein the memory capable of electrically erasing only the area of the predetermined size is a flash memory. 5. A facsimile apparatus comprising the memory control device according to claim 1. 6. An image forming apparatus comprising the memory control device according to claim 1. Description: