JP2001027954A - Computer with program rewriting function - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer with program rewriting function, which can rewrite a program when the writing of the program that is down-loaded from a host computer is failed. SOLUTION: A main processor 100 down-loads a program on a flash memory 104 from a host computer 12 usually in cooperation with a communication coprocessor. When a power monitor circuit 109 detects the abnormality of power during down loading and down loading is interrupted, for example, the communication coprocessor compulsorily resets the main processor, sets a bus connecting the communication coprocessor and a flash memory to be an active state and down-loads the program on the flash memory 104 without the aid of the main processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a computer with a program rewriting function, and more particularly to a computer with a program rewriting function capable of rewriting a program downloaded from a host computer when the writing of the program fails. About.

[0002]

2. Description of the Related Art As a control device for a peripheral device such as a printer, a microprocessor system mainly including a microprocessor and a memory is often used in order to easily cope with an upgrade or the like. The microprocessor sequentially reads the program code, which is the execution form of the program stored in the memory,
The program code is analyzed to execute a predetermined operation.

As a memory used in a conventional microprocessor system, an EPROM (Erasable and Programmable Memory) is used.
mable Read-Only Memory). But E
In order to change the program code stored in the PROM, it is necessary to temporarily remove the EPROM from the microprocessor system and write the corrected program code into the EPROM using a ROM writer. In each case, the trouble of disassembling the peripheral device and removing the EPROM cannot be avoided.

In order to solve this problem, an EPROM has recently been used as a memory used in a microprocessor system.
Instead, flash memories have been used. That is, the flash memory clears the stored contents by applying an erasing signal, and it becomes possible to store the downloaded modified program code again. There is no need to remove memory.

[0005] However, the flash memory has a configuration in which data can be rewritten for each sector of a predetermined size.
It is necessary to download the program code again after erasing all the memory cells in the sector. For this reason, if an abnormality such as a power failure occurs during the download of the program code, the download is interrupted and the flash memory cannot store the correct program code. As a result, the main processor cannot retrieve the correct program from the flash memory even after the abnormality has been resolved, and it is impossible to correctly control the peripheral device to be controlled by the microprocessor system.

[0006] To solve this problem, for example, It is assumed that the rewriting of the vector area of the flash memory (the area where the boot program is stored) is prohibited, and the system can be reloaded at least after the abnormality is cleared. 2. A so-called sequence power supply is used so that the power supply can be maintained at least during the download of the program code. Etc. have been proposed.

[0007]

However, if the rewriting of the vector area is prohibited, it is necessary to replace the memory element itself in order to correct or upgrade the program code stored in the vector area itself. The problem arises. Further, when a sequence power supply is used, the power supply itself is expensive, so that there is a problem that the system becomes expensive.

The present invention has been made in view of the above problems, and provides a computer with a program rewriting function capable of rewriting a program when writing of a program downloaded from a host computer fails. With the goal.

[0009]

According to a first aspect of the present invention, a computer with a program rewriting function assists a main processor when the main processor communicates with a host computer and resets the main processor. A coprocessor that outputs a reset signal for setting the main processor, a rewritable memory that stores a program to be executed by the main processor, a main bus that connects the main processor to the memory, and a connection between the coprocessor and the memory When the auxiliary bus and the coprocessor installed in the main bus reset the main processor, the main bus is deactivated, and the communication coprocessor installed in the auxiliary bus resets the main processor. Make the auxiliary bus active It includes a bus transceiver, a.

According to the present invention, when an abnormality occurs in the main processor during the download of the program from the host computer to the memory via the main processor and the main processor is reset, the program is stored in the coprocessor. Is downloaded directly to memory. According to a second aspect of the present invention, there is provided a computer with a program rewriting function, which includes at least one main processor and a reset for setting the main processor in a reset state while assisting the main processor when the main processor executes communication with the host computer. At least one coprocessor for outputting a signal, a rewritable memory having at least two areas for storing a program executed by the main processor, at least one main processor and at least one
Interface means for permitting two-way communication between the two coprocessors, and stored in a first area of the memory when a program in the memory is installed in each of the at least one main processor and needs to be rewritten. Copying means for copying the program to a second area of the memory, download means installed in each of the at least one main processor and downloading a new program to the first area of the memory, A flash memory accessible by the main processor when there is a response to the coprocessor via the interface as to whether the newly downloaded program is normal or not, or when there is no response Region from region 1 to region 2 Re-downloading a program again when the area of the flash memory installed in each of the dress signal control means and the at least one main processor and accessible by the main processor by the address signal control means shifts from area 1 to area 2 Means.

In the present invention, when a new program in the memory is not normally downloaded,
After the coprocessor switches the memory area accessible by the main processor, the download is executed again. A computer with a program rewriting function according to a third aspect of the present invention includes a main processor, a rewritable memory having at least two areas for storing a program to be executed by the main processor, and a memory installed in the main processor. Copying means for copying the program stored in the first area of the memory to the second area of the memory when the program needs to be rewritten;
Download means installed in the main processor for downloading a new program to a first area of the memory, and time monitoring for monitoring whether the main processor is operating normally based on whether a watchdog signal changes at predetermined intervals. Means, an address signal control means for shifting the area of the flash memory accessible by the main processor from area 1 to area 2 when the time monitoring means determines that the main processor is abnormal, and an address signal control means. Reset control means for resetting the main processor when the area of the flash memory accessible to the processor shifts from area 1 to area 2.

According to the present invention, when a new program in the memory is not normally downloaded,
After switching the memory area accessible by the main processor by the address signal control means, the download is executed again.

[0013]

FIG. 1 shows a first embodiment of a printer to which a computer with a program rewriting function according to the present invention is applied.
FIG. 2 is a configuration diagram of the embodiment, wherein the printer 1 includes a control unit 10.
And a print unit 11. The main processor 100 of the control unit 10 is connected to a communication coprocessor 102 via an interface 101 by a bus.
The main processor 100 also includes an address decoder 1
03, flash memory 104, RAM (Random Acces
s Memory) 105 is also connected by a bus. The address decoder 103 stores the address output from the main processor 100 in the flash memory 104 or the RAM 10
5 is determined, and an enable signal is output to the flash memory 104 or the RAM 105.

The control unit 10 further includes an address bus transceiver 106, a data bus transceiver 107, and a control transceiver 108, and specific configurations and functions will be described later. The control unit 10
Further, the power supply monitoring circuit 109 includes a power supply monitoring circuit 109. When the power supply voltage supplied to the control unit 10 is normal, the power supply monitoring circuit 109 connects to the reset terminal of the main processor 100 via the first diode 1091. An H-level reset signal is supplied. Then, when the power supply voltage becomes abnormal, the reset signal is set to the “L” level, and the main processor 100 is reset.

A reset terminal of the main processor 100 is connected to a reset signal output terminal of the communication coprocessor 102 via a second diode 1092.
The operation of the main processor 100 can be controlled from the communication coprocessor 102. The printing unit 11 of the printer 1 includes a thermal head 110 for executing printing and a platen 111 for feeding printing paper. The thermal head 110 is directly controlled by the main processor 100, and the platen 111 is Motor 113 controlled by processor 100
Driven by

Further, the communication coprocessor 1 of the control unit 10
Reference numeral 02 is connected to the host computer 12 via the cable 13, and the host computer 12 can download the program code executed by the main processor 100 to the flash memory 104. FIG.
Are the main processor 100 and the address decoder 10
3 is a detailed circuit diagram around the address transceiver 106, in which the address bus 30 has n lines (30 ₁ , 30 _2.
.. 30 _n ). Address bus 3
0 indicates that when the main processor 100 is in a reset state,
It shall be in a high impedance state.

The address bus 30 is connected to the address bus 31 of the communication coprocessor 102.
OR connection is made through the line 06. The address transceiver 106 has n gates with control terminals (106 ₁ , 106
₂ ... 106 _n ). The gate 106 _i is with respective control terminals, when the control input 32 the reset signal of the main processor 100 CC 102 outputs a is "H" level, each output is maintained at a high impedance, address Decoder 1
03 is insulated from the communication coprocessor 102.

Conversely, the control input 32 is at "L" level.
Sometimes, the gate 106 with the control terminal _iBecomes conductive
You. The fact that the control input is "L" level indicates that the communication
The processor 102 resets the main processor 100
Means that the main processor 100
Is in the reset state, the address bus 30 goes high.
-Dance. Therefore, the communication coprocessor 102
When the in-processor 100 is reset,
The decoder 103 sends out from the communication coprocessor 102.
Decodes the address to be used.

The same applies to the data bus and the control bus. When the communication coprocessor 102 is resetting the main processor 100, data sent from the communication coprocessor 102 is stored in the flash memory 1
04 and the RAM 105. Figures 3 and 4
9 is a flowchart of a program rewriting routine executed by the communication coprocessor 102, which is executed each time the main processor 100 is reset and each time the power is turned on.

First, in step 30, an index n indicating the number of rewrites is set to an initial value "1".
In step 1, the main processor 100 is requested to inspect the flash memory 104. If the main processor 100 is not in the reset state, the main processor 100 executes, for example, a parity check of the flash memory 104 in response to this request, and returns a communication coprocessor 102 as to whether or not there is an abnormality. If the main processor 100 is in the reset state, it does not respond to the request of the communication coprocessor 102.

At step 32, the contents of the reply or the presence or absence of the reply is determined. If there is a reply indicating that the reply is normal, the program code is regarded as correctly loaded, and this routine is terminated. Conversely, if there is a response to the effect that there is an abnormality, or if there is no response itself, it is determined that the program code has not been correctly loaded, and the routine proceeds to step 33, where the reset signal is set to the "L" level.

As a result, the main processor 100 is reset. The address transceiver 10
6. The data transceiver 107 and the control transceiver 108 are activated, and the communication coprocessor 1
02, an address bus, a data bus and a control bus correspond to an address decoder 103 and a flash memory
And connected to the RAM 105.

In step 34, the host computer 12 is requested to retransmit the program code. When the host computer 12 starts resending the program code, the communication coprocessor 102 receives the program code and transfers it directly to the flash memory 104 in step 35. At step 36, it is determined whether or not the loading of all the program codes has been completed. If the loading has not been completed, the process returns to step 35 to continue loading the program codes. If it is determined in step that the loading of all the program codes has been completed, the process proceeds to step 37, where a reset signal is output.
As the "H" level, the address bus, data bus and control bus of the communication coprocessor 102, the address decoder 103, the flash memory 104 and the RAM 1
05 is disconnected.

Subsequently, at step 38, the main processor 100 is requested to inspect the flash memory 104. In step 39, the contents of the response from the main processor 100 or the presence or absence of the response is determined. If there is a response indicating that the response is normal, the program code is regarded as correctly reloaded, and this routine is terminated. I do.

Conversely, if there is a response indicating that something is abnormal,
Alternatively, if there is no response itself, it is determined that the program code has not been correctly reloaded, and the process proceeds to step 40, where it is determined whether or not the index n indicating the number of rewrites is equal to or larger than the threshold N. If a negative determination is made in step 40, that is, if the rewrite is repeated N times or more, an alarm is output assuming that the program code cannot be correctly loaded even if the rewrite is further performed in step 41. This routine is terminated.

Conversely, if the result of the determination in step 40 is affirmative, that is, if the rewriting has not been repeated N times or more, the program code is reloaded.
After incrementing the index n in step 42, the process returns to step 33. In the above embodiment, since the main processor has a structure in which each bus becomes high impedance when reset, the main processor, the address decoder, the flash memory, and the R
There is no need to install a transceiver between the AM and the AM, but if each bus does not become high impedance even after resetting, install a bus transceiver on each bus of the main processor, and when the main processor is reset It is necessary to separate the main processor from the address decoder, the flash memory and the RAM.

Further, in the above embodiment, the control unit 10 mounted on the printer is connected to the host computer by a communication cable via a communication coprocessor, but the main processor of the control unit 10 is connected to the host computer. If the bus can be directly connected to the bus, the bus of the main processor and the bus of the host computer may be connected via a transceiver.

In the first embodiment, when the correct program is not downloaded to the flash memory at the time of version upgrade, control by the main processor cannot be resumed unless the program is downloaded again using the coprocessor. However, the system configuration becomes complicated. The second embodiment is for solving the above-mentioned problem, and enables redownloading of a program with a relatively simple configuration.

FIG. 5 is a configuration diagram of a second embodiment of a printer using a computer with a program rewriting function according to the present invention. Changes from the first embodiment will be described. That is, in the first embodiment, the address bus 31, the data bus and the control bus of the communication coprocessor 102 are connected to the address transceiver 10 respectively.
6. Although connected to each bus of the main processor 100 via the data transceiver 107 and the control transceiver 108, the communication coprocessor 102 and the main processor 100 are not connected to the bus in the second embodiment.

Instead, the address control signal a output from the communication coprocessor 102 is connected to the most significant digit of the address of the flash memory 104 via the first address control unit 50. Further, the communication coprocessor 1
The address control signal 02 is directly connected to the digital input port of the main processor 100. FIG. 6 is a detailed circuit diagram around the first address control unit 50. The address bus of the main processor has 24 bits (A0 to A23).
And has a memory space of 16 megabytes,
The flash memory 104 has a capacity of 256 kilobytes,
It is assumed that the RAM 105 has a capacity of 128 kilobytes.

The address control signal a output from the digital output port of the communication coprocessor 102 is applied to the base of the NPN transistor 502 via the first resistor 501. The emitter of NPN transistor 502 is directly grounded, and the collector of NPN transistor 502 is directly connected to the most significant digit address terminal of flash memory 104. Further, the eighteenth address bus A17 of the main processor is connected to the collector of the NPN transistor 502 via the second resistor 503.

FIG. 7 shows a memory map according to the second embodiment.
0000) _H- (FFFFFF) 1 accessible by _H
It has 8 megabytes of memory space. The physical address is (00000) _H to (3FFFF) _H 25
The 6-Kbyte flash memory 104 stores logical addresses (FFC000) _H to (FFFFF) of the main processor.
F) Allocated to _H and the physical address is (00000) _H
~ (1FFFF) _H , 128 kilobytes of RAM1
05 is the logical address of the main processor (40000)
0) _H to (41FFFF) _H Therefore, the flash memory 104 and the RAM 105 store the lower 18 bits (A0 to A0) of the address bus of the main processor.
17) can be accessed.

The upper two bits (A22, A23) of the address bus of the main processor are stored in the address decoder 1
03 is used to switch the memory used by the main processor 100 between the flash memory 104 and the RAM 105. That is, (A22, A23)
Is "L, H", the address recorder outputs a disable signal to the flash memory 104, and outputs an enable signal to the RAM 105. When (A22, A23) is "H, H", the address recorder outputs an enable signal to the flash memory 104 and outputs a disable signal to the RAM 105.

The flash memory 104 is further divided into an area 1 and an area 2 each having a capacity of 128 kilobytes, and the area 1 has a logical address (FFE000) _H
To (FFFFFF) _H , and the area 2 has logical addresses (FFC000) _H to (FFDFFF) _H. In the normal state, the same program is stored in the area 1 and the area 2.

In the above configuration, the communication coprocessor 10
2 is "L", the NPN transistor 502 is turned off. Therefore, when the 18th bit A17 of the address bus output from the main processor is "H", the area 1 Can be accessed, and when it is "L", the area 2 can be accessed. In the normal state, the main processor 10
0 executes the process using the program stored in the area 1 of the flash memory 104, so that the main processor sets the 18th bit A17 of the address bus as
"H" is output.

Conversely, if the address control signal a output from the communication coprocessor 102 is "H", the NPN transistor 502 is turned on, and the 18th bit A17 of the address bus is forced to "L". Therefore, the main processor can access only the area 2.
Here, the main processor control program (first edition) V ₁ is stored in the area 1 of the flash memory 104, and the main processor control program (zero edition) V ₀ is stored in the area 2 of the flash memory 104. in order to upgrade to the second version V _2, failure occurred during downloading from the host computer 12 through the cable 13 and CC 102, successfully download main processor control program 2nd edition V ₂ Suppose that it was not done.

FIG. 8 is a flowchart of a first program rewriting routine executed by the main processor 100, which is executed as an interrupt process when the main processor control program needs to be rewritten. That is, when a rewrite request occurs, it is first determined in step 8A whether the address control signal a is "L", that is, whether the area of the flash memory 104 accessible by the main processor 100 is the area 1.

When an affirmative determination is made in step 8A, that is, when the main processor 100 can access the area 1 of the flash memory 104, a control program copy routine is executed in step 8B. FIG. 9 is a detailed flowchart of the control program copy routine,
In step 8B1, the copy routine stored in the area 1 of the flash memory 104 is copied to the RAM 105. Then, in step 8B2, the main processor 100
Is transferred to the RAM 105 so that the main processor 100 can execute the copy routine stored in the RAM 105. Then, in step 8B3, the main processor control program (which is stored in the area 1 of the flash memory 104) is executed. copy the first edition) V ₁ in the region 2 of the flash memory 104 to end the routine.

Next, in step 8C (FIG. 8), it is determined whether or not the copying has been normally performed by performing a parity check on the area 2. When a positive determination is made in step 8C,
That is, when it is determined that the copy has been normally performed, the process proceeds to step 8D to execute the download routine. FIG.
0 is a detailed flowchart of download routine, downloaded After migration task control of the main processor 100 to the flash memory 104 in step 8D1, a control program at step 8D2 Second Edition V ₂ from the host computer 12 to the RAM105 I do. In step 8D3, the area 1 of the flash memory 104 is again
After the copy routine stored in the RAM 105 is copied to the RAM 105, task control is performed in the RAM 105 in step 8D4.
It is shifted to, and copy the downloaded control program 2nd edition V ₂ in the region 1 of the flash memory 104 to the RAM105 in step 8D5, the routine ends.

In step 8E (FIG. 8), a parity check is performed on area 1 to determine whether copying to area 1 has been performed normally. When an affirmative determination is made in step 8E, that is, when copying to the area 1 has been normally executed, the communication coprocessor 102 is executed in step 8F.
, And terminates this routine.
On the other hand, when a negative determination is made in steps 8C and 8E, that is, when the copy is not normally executed, an abnormal status is transmitted to the communication coprocessor 102 in step 8G, and this routine ends.

FIG. 11 is a flowchart of a coprocessor routine executed by the communication coprocessor 102.
This is executed as interrupt processing when the main processor control program needs to be rewritten. First, a main processor diagnosis routine is executed in step 11A. FIG. 12 is a detailed flowchart of the main processor diagnosis routine. In step 11A1, the reception of the status transmitted from the main processor is started, and in step 11A2, it is determined whether the status has been received.

When an affirmative determination is made in step 11A2,
That is, when the status is received, step 11A3
It is determined whether the status received in is normal status.
When an affirmative determination is made in step 11A3, that is, when the normal status is received, a flag MS indicating whether or not the download has been normally completed in the main processor indicates in step 11A4 that the download has been normally completed. 1 is set, and this routine ends.

When a negative determination is made in step 11A2,
That is, if the status has not been received, step 11
It is determined whether a predetermined time set based on a copy time from the flash memory to the RAM or a download time of the control program has elapsed since the start of the status reception in A5. If a negative determination is made in step 11A5, that is, if the predetermined time has not elapsed since the start of status reception, the process returns to step 11A2, and the standby state for status reception is continued.

When an affirmative determination is made in step 11A5,
That is, when a predetermined time has elapsed since the start of status reception, and when a negative determination is made in step 11A3, that is, when an abnormal status is received, step 1
At 1A6, the flag MS is set to "0" indicating that the download has not been completed normally, and the routine ends.

In step 11B (FIG. 11), it is determined whether or not the download was normally performed in the main processor based on the setting of the flag. If a negative determination is made in step 11B, that is, when the download control program 2nd edition V ₂ is not normally performed in the main processor executes memory area switching routine at step 11C.

FIG. 13 is a detailed flowchart of the memory area switching routine. In step 11C1, a reset signal is output via the reset signal output terminal of the communication coprocessor 102 to reset the main processor.
Set to "L" level. After resetting the main processor 100, the address control signal is set to "H" level in step 11C2, and the area of the flash memory 104 accessed by the main processor is switched to area 2.

Thereafter, in step 11C3, the reset signal is set to the "H" level via the reset signal output terminal of the communication coprocessor 102 to put the main processor 100 into an operating state, and this routine ends. Then, the main processor starts the execution of the download routine of FIG. 8 again, but this time, since the address control signal is at the "H" level, a negative determination is made in step 8A and the process directly proceeds to step 8D, where the control program second version V ₂ is RAM1
05 again. Steps 8E to 8G
In the download status control program 2nd edition V ₂ transmits to the communication coprocessor terminates the routine. The communication coprocessor processes this status by executing the main processor diagnostic routine shown in FIG. 12 at step 11D.

That is, in step 11E (FIG. 11), it is determined whether the download has been normally performed in the main processor based on the setting of the flag. Step 11E
When in a negative determination, that is, when the re-download the control program 2nd edition V ₂ is not normally performed in the main processor executes fault processing in step 11F and this routine is terminated. Note that the abnormal processing includes processing such as re-executing the download or displaying an appropriate abnormal display.

When an affirmative determination is made in step 11B or 11E, that is, when the download is normally performed in the main processor, the address control signal is set to "L" level in step 11G to change the flash memory area accessed by the main processor. The routine returns to the area 1 and the routine ends. In the second embodiment, the communication coprocessor determines whether or not the download has been normally performed in the main processor by software. However, when the communication processor is not provided, the determination is made by hardware. It is also possible.

FIG. 14 is a block diagram of a third embodiment of a printer using a computer with a program rewriting function according to the present invention. Changes from the second embodiment will be described. That is, instead of the communication coprocessor 102,
A reset control unit 140, a time monitoring unit 141, and a second address signal control unit 142 are used.

FIG. 15 is a detailed circuit diagram around the reset control unit, the time monitoring unit and the second address signal control unit. FIG. 16 is a waveform diagram of each part of the detailed circuit.
g ○ correspond to each other, and Sig 1 is the power supply monitoring circuit 10
9 shows a main processor reset signal output from the main processor 91. The reset control unit 140 is a primary delay circuit 140
1 and an exclusive OR gate 1402, and a reset signal Sig 2 output from the primary delay circuit 1401 is connected to one input terminal of the NOR gate 1402. NO
The output of the R gate 1402 is connected via a diode 1092 to the reset terminal of the main processor 100.

The time monitoring section 141 includes an OR gate 1411,
Timer 1412, charging circuit 1413, NOT element 141
4. A first transistor 1415 is provided, and a first input terminal of the OR gate 1411 is connected to a watchdog timer terminal of the main processor 100. When the main processor 100 is normal, a pulse signal having a constant period is generated. Receive the watchdog timer signal Sig3.

The output Sig 4 of the OR gate 1411 is supplied to the trigger terminal of the timer IC 1412. Depending on whether the watchdog timer signal Sig 3 changes at a predetermined cycle,
It monitors whether the main processor 100 is normal. The output Sig5 of the timer IC 1412 is
If 0 is determined to be normal, it is at the "H" level, and if it is determined to be abnormal, it is at the "L" level. The output Sig5 of the timer IC 1412 is inverted by the NOT element 1414 and the signal Sig5 is inverted.
It becomes 6.

The base of the first transistor 1415 is connected to the output Sig4 of the OR gate 1411, the emitter is connected to the discharge terminal and the threshold terminal of the timer IC 1412, and the collector is grounded. The second address signal control unit 142 includes a flip-flop 1421, a second transistor 1422, and a third transistor 1423.
The output of the NOT element 1414 is connected to one clock terminal.

The non-inverted output Q of the flip-flop 1421 is connected to the other input terminal of the NOR gate 1402, and the inverted output Q ^* is connected to the input of the primary delay circuit 1401. The normal output Q of the flip-flop 1421 is
And the digital input port of the main processor 100. Second
The collector of the transistor 1422 is connected to the third
The base of the transistor 1423 is connected to a digital output port of the main processor 100 via a resistance dividing circuit. Then, the third transistor 14
The emitter of 23 is grounded, and the collector is directly connected to the most significant digit address terminal of the flash memory 104 and also to the most significant digit terminal A17 of the address bus of the main processor 100 via a resistor.

FIG. 17 is a flowchart of a second program rewriting routine executed by the main processor 100. This routine is executed as an interrupt process when the main processor control program needs to be rewritten.
Most of the processing is the same as the second program rewriting routine (FIG. 8), so only the differences will be described. That is, if the copying is normally performed in step 8E, the access control signal Sig13 output from the digital output port is set to "L" level in step 16A, and this routine is terminated. Conversely, when a negative determination is made in Steps 8C and 8E, that is, when copying is not performed normally, the access control signal Sig 13 is determined in Step 16B.
Is set to the "H" level, an internal reset is performed in step 16C, and this routine ends.

Therefore, when the copying is not performed normally, the second program rewriting routine is executed again. In this case, a negative determination is made in step 8A and step 8 is executed.
At D, the program is downloaded again. When the contents stored in the area 1 of the flash memory 104 are destroyed so that the download routine cannot be executed by downloading the program, the watchdog timer Sig3 of the time monitoring unit 141 is not a periodic pulse. Then, the output Sig5 of the timer IC 1412 becomes "H",
5 is changed to "L" (time t ₁ in FIG. 16).

Then, the flip-flop 1421 of the address control unit 142 is driven, the non-inverted output Q becomes “H”, and the exclusive OR gate 140 of the reset control unit 140
2 is supplied to the input terminal, so that the output of the reset signal Sig 2 also becomes “H”. The inverted output Q ^* of the flip-flop 1421 becomes “L”, and the exclusive OR gate 140 is delayed by the time constant of the primary delay circuit 1401.
2 is supplied to the other input terminal of the reset signal Si.
g 2 is to "L" reset signal after a predetermined time the Purus like waveform (time t ₂ in FIG. 16). The main processor 100 is reset by the reset signal Sig 2 and can be executed again.

The normal output Q of the flip-flop 1421 is
When it becomes “H”, the second transistor 1422 and the third transistor 1422
Of the main processor 10 by the transistor 1423
The most significant bit A17 of the data address 0 is forcibly grounded, and the main processor 100 starts executing the program stored in the area 2 of the flash memory 104.

That is, a new control program is temporarily downloaded to the RAM 105 using the download routine stored in the area 2 of the flash memory 104. Then, the copy routine stored in area 2 is stored in RAM
After copying to the RAM 105, the task control is shifted to the RAM 105, the new control program stored in the RAM 105 is copied to the area 1 of the flash memory 104, the address control signal is set to "H", and the download process is completed. .

Note that while the normal output Q of the flip-flop 1421 is "H" and the most significant bit A17 of the data address of the main processor 100 is forcibly grounded, the OR gate 1411 of the time monitoring unit 141 is set. Of the timer IC 1412 is maintained at "H".
Therefore, the monitoring of the watchdog signal Sig3 is not executed.

Then, when the processing for setting the address control signal to "H" is executed by the main processor 100,
Reset pulse Si output from digital output port
g10 becomes “H” (time t _{3 in} FIG. 16), and the main processor 100 executes the control program stored in the area 1 of the flash memory 104. Then, the timer IC1 by Sig 12 at time t ₄ in FIG. 16 if normal
412 and flip-flop 1421 are reset.

In the third embodiment, whether the main processor is normal or not is determined by the watchdog signal Sig.
Although the time for the determination based on 3 is determined by a first-order lag circuit using a capacitor and a resistor, it can be substituted by, for example, a counter, a coil and a resistor, or a time counting circuit using a coil and a capacitor. . Also,
In the second and third embodiments, bipolar transistors are used as transistors, but it goes without saying that field effect transistors or integrated circuits can be used.

In the second and third embodiments, one flash memory is divided into two areas.
An independent flash memory may be used for each area. Note that, in each of the above embodiments, the batch-erasable nonvolatile memory is a flash memory. However, other types of memory, for example, an EEPROM (Electrically Eras
It is also possible to apply a programmable programmable read only memory (RAM) and a RAM (random access memory) with a battery backup.

The main processor or coprocessor may have a function of notifying the host computer that the download has not been completed.

[0066]

According to the computer with the program rewriting function according to the present invention, when the program is not normally downloaded from the host computer to the memory, it is automatically detected that the program was not normally performed. Then, since the download is performed again, all the programs can be correctly downloaded to the memory.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a printer to which a computer with a program rewriting function according to the present invention is applied.

FIG. 2 is a detailed circuit diagram.

FIG. 3 is a flowchart (1/2) of a program rewriting routine.

FIG. 4 is a flowchart (2/2) of a program rewriting routine.

FIG. 5 is a configuration diagram of a second embodiment of a printer to which a computer with a program rewriting function according to the present invention is applied.

FIG. 6 is a detailed configuration diagram around a first address signal control unit.

FIG. 7 is a memory map.

FIG. 8 is a flowchart of a first program rewriting routine.

FIG. 9 is a detailed flowchart of a control program copy routine.

FIG. 10 is a detailed flowchart of a download routine.

FIG. 11 is a flowchart of a coprocessor.

FIG. 12 is a detailed flowchart of a main processor diagnosis routine.

FIG. 13 is a detailed flowchart of a memory switching routine.

FIG. 14 is a configuration diagram of a third embodiment of a printer to which the computer with a program rewriting function according to the present invention is applied.

FIG. 15 is a detailed circuit diagram around a reset control unit, a time monitoring unit, and a second address control unit.

FIG. 16 is a waveform chart of a reset control unit, a time monitoring unit, and a second address control unit.

FIG. 17 is a flowchart of a second program rewriting routine.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Printer 10 ... Control part 100 ... Main processor 101 ... Interface 102 ... Communication coprocessor 103 ... Address decoder 104 ... Flash memory 105 ... RAM 106 ... Ad restaurant receiver 107 ... Data transceiver receiver 108 ... Control transceiver receiver 109 ... Power supply monitoring circuit 11 printing section 110 thermal head 111 platen 112 drive circuit 113 motor

Claims (6)

[Claims] A coprocessor that assists the main processor when the main processor communicates with a host computer and that outputs a reset signal for setting the main processor to a reset state; A rewritable memory for storing a program executed by the main processor; a main bus connecting the main processor and the memory; an auxiliary bus connecting the coprocessor and the memory; Installed, when the coprocessor puts the main processor in a reset state, deactivates the main bus, and is placed in the auxiliary bus, when the coprocessor puts the main processor in a reset state. Activate the auxiliary bus Program re-write function with a computer that includes and vinegar transceiver, a. 2. At least one main processor, and at least a reset signal for setting the main processor to a reset state while assisting the main processor when the main processor executes communication with a host computer. A coprocessor; a rewritable memory having at least two areas for storing a program executed by the main processor; and a bidirectional communication between the at least one main processor and the at least one coprocessor. Interface means for permitting communication, and the program installed in each of the at least one main processor and stored in a first area of the memory when the program in the memory needs to be rewritten. The memory Copying means for copying to a second area; download means installed in each of the at least one main processor for downloading a new program to a first area of the memory; The main processor accesses when the coprocessor asks a question via the interface as to whether the newly downloaded program is normal or abnormally. Address signal control means for shifting a possible area of the flash memory from area 1 to area 2; and the flash provided in each of the at least one main processor and accessible by the main processor by the address signal control means. Memory area is area 1 And a re-downloading means for re-downloading the program when the program shifts from the area to the area 2. A main processor; a rewritable memory having at least two areas for storing a program to be executed by the main processor; a rewritable memory installed in the main processor and rewriting the program in the memory Copying means for copying the program stored in the first area of the memory to the second area of the memory when it becomes necessary; and
Download means for downloading a new program to an area, time monitoring means for monitoring whether or not the main processor is operating normally based on whether a watchdog signal changes at predetermined intervals, and the time monitoring means Address signal control means for shifting the area of the flash memory accessible by the main processor from area 1 to area 2 when it is determined that the main processor is abnormal; Possible flash memory area is area 1
And a reset control means for resetting the main processor when the program shifts from the first area to the second area. 4. The computer with a program rewriting function according to claim 1, wherein said memory is a batch erasing nonvolatile memory (flash memory). 5. The computer with a program rewriting function according to claim 1, wherein said memory is an EEPROM. 6. The computer with a program rewriting function according to claim 1, wherein the memory is a battery-backed-up RAM.