JP2001024149A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a semiconductor device having logic function and memory function by mounting a memory semiconductor chip on a logic semiconductor chip and containing the memory semiconductor chips entirely or partially on a substrate. SOLUTION: External connection terminals 5, a wiring pattern 7 and an opening 6 are provided on a substrate 4 and the external connection terminals 5 are connected electrically with the wiring pattern 7. The opening 6 is formed of a through hole or a counterbore having an area equal to or wider than that of a memory semiconductor chip 3 and a part thereof is contained in the opening 6. Since the memory semiconductor chip 3 is contained in the substrate 4, the semiconductor device can be made thin correspondingly. The space in the opening 6 where the memory semiconductor chip 3 is not present is filled with an insulating filler thus protecting the memory semiconductor chip 3. The memory semiconductor chip 3 is mounted on the wiring plane of a logic semiconductor chip 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a miniaturized system semiconductor device having one or more memory semiconductor chips mounted on a logic semiconductor chip.

[0002]

2. Description of the Related Art In recent years, with the miniaturization and high integration of semiconductor elements, semiconductor devices called a system semiconductor in which both a logic circuit and a memory are integrated on one chip have been developed.

A logic circuit and a memory circuit in a system semiconductor device are collectively designed using a computer.
According to a design method using a computer, a complicated circuit pattern can be designed with high accuracy, so that a logic circuit and a memory circuit are provided as one fine integrated circuit.

[0004]

However, since the above-mentioned integrated circuit has a miniaturized structure, it is difficult to individually inspect a logic function and a memory function.

If the integrated circuit does not have a desired function, it is difficult to identify the cause. This is because it is difficult to individually test the logic function and the memory function on the integrated circuit. Even if the cause can be identified, it is difficult to individually modify the logic function and the memory function. for that reason,
The yield of the system semiconductor device is lower than when the logic circuit and the memory circuit are individually designed.

Furthermore, even when a small-scale circuit change such as an increase in the capacity of a memory is performed, it is necessary to redesign the entire integrated circuit, and there is also a problem that the specification change is not easy.

As a method of solving the problem of the system semiconductor device, a configuration in which a logic circuit and a memory circuit are realized by separate semiconductor chips can be considered.

However, when these individually designed chips are mounted on a substrate, a mounting area is required by the number of chips, so that the size of the device becomes large.

On the other hand, a method of laminating a plurality of chips on a substrate is conceivable. However, such a laminated structure increases the height of the device.

Accordingly, an object of the present invention is to provide a semiconductor device having a logic function and a memory function and suitable for miniaturization.

[0011]

According to a first aspect of the present invention, there is provided a substrate having a plurality of external electrodes connected to a wiring pattern, and a wiring pattern mounted on the substrate. And a memory semiconductor chip mounted on a wiring surface of the logic semiconductor chip in a region where the substrate does not exist, with the wiring surface facing the logic semiconductor chip.

According to a second aspect of the present invention, the substrate has a counterbore-shaped recess having an area larger than an area of the memory semiconductor chip, and at least a part of the memory semiconductor chip is housed in the recess. It is characterized by being performed.

The invention according to claim 3 is characterized in that another memory having a function different from that of the memory semiconductor chip is further mounted on the wiring surface of the logic semiconductor chip.

Further, the invention according to claim 4 is characterized by further comprising a heat sink fixed to a package surface of the logic semiconductor chip.

According to a fifth aspect of the present invention, there is provided a semiconductor device, comprising: a tape substrate provided on a package surface of the memory semiconductor chip and connected to a wiring pattern of the substrate; A second logic semiconductor chip disposed upward with its package surface facing and connected to the wiring pattern of the tape; and a second memory semiconductor chip mounted on the wiring surface of the second logic semiconductor chip And wherein the second logic semiconductor chip is connected to a wiring pattern of the tape substrate via a wire.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Summary of the Invention) In the present invention, a semiconductor chip having a memory function is mounted on a semiconductor chip having a logic function, and both miniaturization and thinning of the device are achieved. This configuration has been conceived by focusing on the fact that the chip size is larger when the logic function is realized than when the memory function is realized.

Preferably, an opening is provided in the substrate, and a semiconductor chip having a memory function is accommodated in the opening to reduce the thickness of the device.

It is preferable that two or more memory semiconductor chips having different functions are mounted on the logic semiconductor chip to achieve a multifunctional device.

(Embodiment) Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. 1, 2 and 3. FIG.
FIG. 1B is a cross-sectional view taken along the line AA in FIG.

As shown in FIG. 1, the substrate 4 includes external connection terminals 5, a wiring pattern 7 and an opening 6, and the external connection terminals 5 and the wiring pattern 7 are electrically connected.

The opening 6 is formed by a through hole having a size larger than the area of the memory semiconductor chip 3 or a counterbore-shaped concave as shown in FIG. Is stored. As a result, the device can be made thinner by the amount that the memory semiconductor chip 3 and the substrate overlap in the thickness direction.

A space in the opening 6 where the memory semiconductor chip 3 does not exist may be filled with an insulating filler (not shown) to protect the memory semiconductor chip 3.

The memory semiconductor chip 3 is mounted on the wiring surface of the logic semiconductor chip 2. At this time, the wiring surface of the memory semiconductor chip 3 is disposed toward the logic semiconductor chip 2, and the memory semiconductor chip 3 and the logic semiconductor chip 2 are electrically connected by the bumps 8 interposed between these wiring surfaces. Connected. The connection by the bumps 8 is performed by direct bonding.

By this direct bonding, the wiring surface of the logic semiconductor chip 2 and the memory semiconductor chip 3
The structure shown in FIG. 1 in which the wiring surfaces face each other is achieved.

At this time, a flash memory semiconductor chip,
It is preferable that a plurality of memory semiconductor chips 3 having different functions, such as a DRAM memory semiconductor chip and an SRAM semiconductor chip, be mounted on the logic semiconductor chip 2. By using a plurality of memory semiconductor chips 3 having different functions, the device can be made multifunctional.

The logic semiconductor chip 2 is electrically connected to the wiring pattern 7 on the substrate 5 via the bump 8. As a result, the logic semiconductor chip 2 and the external connection terminal 5 of the substrate 4 are electrically connected via the wiring pattern 7.

As shown in FIG. 3, it is preferable to dispose a heat sink 9 on the package surface of the logic semiconductor chip 2. This is because the package logic semiconductor chip 2 generates more heat than the memory semiconductor chip 3. Since there is no other member to be mounted on the package surface of the logic semiconductor chip 2, it is possible to secure a large area.

Therefore, a sufficient heat radiating area can be ensured, and a large amount of heat generated in the logic semiconductor chip 2 can be removed by the heat radiating plate 9.
Can be suitably released from

As described above, the present invention has a structure in which the memory semiconductor chip and the substrate are mounted on the wiring surface of the logic semiconductor chip, so that a small and thin device can be obtained. Further, in the present invention, since the logic function and the memory function are realized by separate chips, the functions of the logic and the memory can be individually tested, and the specifications of the functions can be individually changed.

FIG. 4 shows the structure of a semiconductor device according to the second embodiment of the present invention. This embodiment is an example in which another combination of a logic and a memory semiconductor chip is additionally mounted.

The second memory semiconductor chip 13 is mounted with the wiring surface facing the second logic semiconductor chip 12,
These are electrically connected via the bumps 8.

The second logic semiconductor chip 12 has an area smaller than the opening 6, and its pattern surface is provided on the tape substrate 11. The second logic semiconductor chip 12 is electrically connected to a wiring pattern formed on the tape substrate 11 via the wire 10. The tape substrate 11 is fixed to the substrate 4, and the wiring of the tape substrate 11 is electrically connected to the wiring pattern 7 of the substrate 4.

The opening 6 of the present embodiment accommodates all or a part of the memory semiconductor chip 3, the tape substrate 11, the wires 10, the second logic semiconductor chip 12, and the second memory semiconductor chip 13, and accommodates them. As a result, the device can be made thinner.

Further, the second logic semiconductor chip 12
The second logic semiconductor chip 12 is fixed on a tape via an elastomer in order to absorb the thermal stress generated by the heat generated by the second memory semiconductor chip 13 and the bump between the second memory semiconductor chip 13 and the second logic semiconductor chip 12 is formed. It is desirable to fill the space that does not exist with an elastomer.

[0035]

According to the present invention, there is provided a system semiconductor device which is effective in reducing the size of a package by mounting a memory semiconductor chip on a logic semiconductor chip and further housing all or a part of the memory semiconductor chip on a substrate. Can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the structure of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing another structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment of the present invention.

[Description of Signs] 1 ... System semiconductor 2 ... Logic semiconductor chip 3 ... Memory semiconductor chip 4 ... Substrate 5 ... External connection terminal 6 ... Opening 7 ... Wiring pattern 8 ... Bump 9 ... Heat radiation plate 10 ... Wire 11 ... Tape substrate 12 ... Second logic semiconductor chip 13... Second memory semiconductor chip

Claims (5)

[Claims] A substrate having a plurality of external electrodes connected to a wiring pattern; a logic semiconductor chip mounted on the substrate and connected to the wiring pattern of the substrate; and a wiring surface of the logic semiconductor chip. And a memory semiconductor chip mounted with its wiring surface facing a region where the substrate does not exist. 2. The semiconductor according to claim 1, wherein the substrate has a counterbore-shaped recess having an area larger than an area of the memory semiconductor chip, and at least a part of the memory semiconductor chip is housed in the recess. apparatus. 3. The semiconductor device according to claim 1, wherein another memory having a function different from that of said memory semiconductor chip is further mounted on a wiring surface of said logic semiconductor chip. 4. The semiconductor device according to claim 1, further comprising a heat sink fixed to a package surface of said logic semiconductor chip. 5. A tape substrate provided on a package surface of the memory semiconductor chip and connected to a wiring pattern of the substrate, the package surface being directed above the memory semiconductor chip via the tape. A second logic semiconductor chip disposed and connected to the wiring pattern of the tape; and a second memory semiconductor chip mounted on a wiring surface of the second logic semiconductor chip, 5. The semiconductor device according to claim 1, wherein the second logic semiconductor chip is connected to a wiring pattern of the tape substrate via a wire.