JP2001023983A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device, having a microfabricated pattern structure and low-resistance metal interconnections on a base insulating layer formed on a silicon substrate, as well as a method for manufacturing the same. SOLUTION: This semiconductor device has, on an insulating-film base layer 2 of a silicon substrate 1, metal interconnection layers and an insulating layer 6 in grooves between the adjacent metal interconnection layers as a microfabricated pattern. In this semiconductor device, the metal interconnection layer is a multi-level metal interconnection layer which forms at least a second metal interconnection film 7 on a first metal interconnection film 3. The thickness of the multi-level metal interconnection layer is set to a value in a vicinity of 2, in terms of the aspect ratio that expresses the thickness by the ratio of the depth of a pattern groove, with respect to a prescribed metal interconnection layer width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a miniaturized pattern structure, wherein a low-resistance metal wiring is formed on a base insulating layer on a silicon substrate. The present invention relates to a semiconductor device having a layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art Along with the high integration, miniaturization, high functionality, and high performance of a semiconductor integrated circuit, the design rules of a metal wiring film formed on a silicon substrate have been miniaturized, the resistance of the metal wiring film has been reduced, and the electric resistance has been reduced. There is an increasing demand for improved resistance to migration (EM: phenomenon in which metal atoms move due to electric current).

Therefore, conventionally, in order to reduce the resistance of the metal wiring film and improve the EM resistance, it is effective to increase the thickness of the metal wiring layer. As other measures, application of a new wiring material is also being considered. For example, in the case of a copper wiring film, the resistance is 2/3,
The EM resistance is improved by about one to two digits. However, copper wiring is not suitable for miniaturization due to the difficulty of processing technology, and no other suitable wiring material has been found, so that it is difficult to apply a new wiring material.

[0004] Therefore, there is a need for a manufacturing method that can simultaneously miniaturize a metal wiring layer and increase its thickness using a conventional aluminum alloy wiring film. That is, it is required that the aspect ratio of the metal wiring film be further increased under the miniaturized structure (or formation) of the semiconductor device.

In the prior art, after a desired aluminum alloy wiring film is formed by a sputtering method or a CVD method, a photoresist is patterned by a photolithography technique, and anisotropic etching is performed using the photoresist as a mask to form a metal wiring. To form In such a conventional method, in order to realize miniaturization, if the thickness of the metal wiring layer is simply increased, for example, by a single layer while maintaining the design rule (reference), the aspect ratio of the etching region increases. Therefore, insufficient etching of the metal wiring layer, side etching,
Generally, problems such as charge damage due to electronic shading occur (see FIG. 4).

[0006]

Under the circumstances described above, in order to achieve high integration, miniaturization, high functionality, and the like of a semiconductor device, the conditions under which a fine structure pattern of the semiconductor device is manufactured. In addition, it has become an important issue to reduce the resistance of the metal wiring layer.

[0007] For this purpose, conventionally, an attempt has been made to increase the thickness of the metal wiring layer, that is, to increase the aspect ratio of the metal wiring layer. However, in the conventional method, the film thickness is almost the same as the metal wiring layer design rule. For example, as a design rule for a metal wiring layer, when the thickness is 0.5 μm, the limit of the thick film is O.D. 5 μm. Therefore, it is extremely difficult to increase the aspect ratio of the metal wiring layer to 1 or more, and in general, the actual situation is that miniaturization and thickening of the metal wiring layer are not simultaneously achieved.

Therefore, an object of the present invention is to use a conventional aluminum alloy or the like which is conventionally known as a metal wiring material, and to obtain the same under the conditions for miniaturizing a semiconductor device. It is an object of the present invention to provide a semiconductor device having a low resistance metal wiring layer and a method of manufacturing the same.

[0009]

Means for Solving the Problems In view of the above problems, the present inventor has made intensive studies and, as a result, has focused on multilayer film formation of a metal wiring layer through processing steps such as a lithography process, a pattern mask and an etching removal. As a result of various studies, a method for thickening the metal wiring film under the miniaturized pattern was found, and the present invention was completed.

That is, the present invention relates to a semiconductor device having a thick metal wiring layer having a fine pattern structure with an insulating film on a silicon substrate as a base and an insulating layer in a pattern groove formed between the metal wiring layers. The metal wiring layer has a fine structure capable of reducing the resistance of the metal wiring layer by making the metal wiring layer finer and thicker by multi-layer film formation, that is, by increasing the aspect ratio of the metal wiring layer.

For this purpose, the thick metal wiring layer is formed by the first metal wiring layer.
A multilayer metal wiring film formed by laminating at least a second layer metal wiring film on a layer metal wiring film, wherein the thickness of the multilayer metal wiring film is determined with respect to a predetermined metal wiring film width at the time of pattern formation. An aspect ratio represented by a ratio of the pattern groove depth (depth / width), a thickness close to at least 2, and a metal wiring film as a fine structure pattern having a high aspect ratio by multilayer film formation; A semiconductor device is provided.

By making the metal wiring film a thick film having a high aspect ratio as described above, it is possible to reduce the resistance, to improve the EM resistance, to achieve high integration and fineness as an LSI semiconductor device. This is a semiconductor device that enables higher performance and higher performance.

Further, according to the present invention, as a method for manufacturing such a semiconductor device, a multi-layered metal wiring layer and a fine-structure pattern groove formed between the wiring layers are formed on an insulating film base on a silicon substrate. A method of forming an insulating film having the same height as the thickness of the thick metal wiring layer is provided, comprising the following steps (1) to (5). That is, (1) forming a first layer material of a metal wiring film on the substrate,
Next, a silicon nitride film is stacked and formed, and the silicon nitride film is removed by anisotropic etching with a predetermined metal wiring layer pattern mask via a photoresist film,
A pre-structure of a pattern groove for forming an inter-metal-wiring insulating film is formed. (2) Next, using the remaining silicon nitride film as a mask pattern, the first layer material of the metal wiring film on the groove portion obtained in the step (1) is removed by anisotropic etching to form the insulating layer. To complete the pattern groove. (3) Then, an insulating material is coated on the entire surface including the inside of the pattern groove, and is flattened so as to match the remaining silicon nitride film surface below the metal wiring film pattern portion. An insulating layer is formed. (4) Next, the entire silicon nitride film still remaining in the previous step is selectively removed by etching, leaving the first layer of the metal wiring in the metal wiring film pattern portion.
A pattern groove for forming a layer is formed. (5) Next, a second layer material of the metal wiring film is coated on the entire surface including the inside of the pattern groove formed in the step (4). Next, a multi-layered metal wiring layer composed of at least two layers is formed by flattening so as to match the surface of the metal wiring insulating layer formed in the previous step (3).

As described above, according to the present invention, the silicon substrate has a fine structure pattern, and the formed metal wiring film is a thick film having a high aspect ratio of about 2 as the aspect ratio. A semiconductor device having a ratio is obtained. Further, in the manufacturing method according to the present invention which enables this, a lithography technique is performed on the first-layer metal wiring film as a manufacturing process for forming a multi-layered metal wiring film so as to make the film thicker. An intermediate step of forming a silicon nitride film layer to be finally removed through a pattern mask process is a remarkable feature different from the conventional method.

Therefore, through this intermediate step, at least the second-layer metal wiring film is formed into a multilayer on the first-layer metal wiring film. In the present invention, this intermediate step is repeated. Thereby, it is possible to further increase the number of layers and the thickness.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device having a multi-layer thick film and a low-resistance metal wiring layer formed under the above-described fine structure pattern conditions according to the present invention and a method of manufacturing the same will be further described. .

According to the present invention, in the above-described manufacturing method, a predetermined metal wiring film width can be appropriately set to a rule of miniaturization of about 0.35 μm or more and about 0.5 μm or less. Below this lower limit, it is difficult to obtain a high aspect ratio, and rules exceeding the upper limit are not sufficient to satisfy miniaturization, especially ultrafineness.

Further, in the manufacturing method of the present invention, as described above, the depth of the pattern groove for forming the insulating layer disposed between the metal wiring films can be adjusted by changing the depth of the silicon substrate in the intermediate step for forming the multilayer metal wiring layer. First formed on the insulating film base
Forming a layer so as to correspond to the thickness of the laminated structure of the metal wiring film and the silicon nitride film of the layers, and forming the layer so as to correspond to the thickness of the multilayer metal wiring layer formed in at least two layers. It is assumed that.

Further, in connection with the above-mentioned pattern groove depth,
In the laminated structure of the first layer of the metal wiring layer and the silicon nitride film layer already described above, it is preferable that each film thickness is at least about 0.5 μm. In the present invention, the material of the metal wiring film is not particularly limited, but conventionally known aluminum or aluminum alloy which does not have special characteristics and can be suitably used.

In the present invention, the film thickness of the inter-metal wiring insulating layer formed in the pattern groove, the film thickness of the multilayer metal wiring layer forming the groove, and the like are determined through the above-described manufacturing steps. Thereby, the film thickness can be made to be at least around 1 μm or more than 1 μm as necessary.

In the present invention, the second-layer metal wiring film material described above may be, for example, as long as it does not significantly impair the adhesion and compatibility with the first-layer metal wiring material.
Examples thereof include copper, tungsten, silver, gold, aluminum, and aluminum alloys.
Seeds can be used.

A manufacturing embodiment of a semiconductor device having a low-resistance metal wiring film made of a multilayer film having a high aspect ratio will be described in more detail with reference to FIGS.

1 (a) to 1 (d), for example, as shown in FIG. 1 (b), an Al, Al alloy, preferably an Al alloy film is formed on a silicon substrate 1 on which a base insulating film 2 is provided. A first metal wiring layer 3 is formed by a sputtering method, and then a silicon nitride film 4 is stacked. The thickness of the first metal wiring film is about 0.5 μm when the design rule of the metal wiring is 0.5 μm. Here, a silicon nitride film 4 formed by a CVD method on the first metal wiring film 3
Is formed to a thickness of about 0.5 μm. This silicon nitride film is used as an etching mask when anisotropically etching the first metal wiring film.

Next, after a photoresist 5 is spin-coated on the silicon nitride film 4 by photolithography, the silicon nitride film is anisotropically etched by a predetermined patterning using the photoresist as a mask (FIG. 1).
(C)). Next, after the remaining photoresist is removed, as shown in FIG. 1D, the first metal wiring film is anisotropically etched using the silicon nitride film 4 as a mask to form a metal wiring interlayer insulating layer. A high aspect groove to be formed is formed.

Here, a multi-layered etching process is performed under the above-described laminated film formation and fine patterning as shown in FIGS. 1A to 1D, so that the thick metal wiring layer of the conventional method can be formed. In the formation, insufficient etching, side etching, and the like, which occur between the thick metal wiring layers, can be prevented.

That is, referring to FIG. 4 showing insufficient etching, side etching, and the like, which tend to occur in the step of forming and forming a thickened metal wiring layer by the conventional method, the metal wiring layer 13 shown in FIG. FIG. 1 in the present invention example
The thickness of the first metal wiring layer 3 + silicon nitride film 4 shown in FIG. 3D is the thickness of the metal wiring layer intended for both. Therefore, as in the conventional method shown in FIG. 4, a predetermined mask patterning and anisotropic etching of the metal wiring layer 13 through a photoresist film thereover by photolithography technology to obtain a thick film. Therefore, the aspect ratio of the etching area under miniaturization patterning,
Extremely high, insufficient etching 15 and side etch 1
6 occurs.

However, as already described in the present invention, although not shown, the photoresist 5 is coated on the silicon nitride film 4 shown in FIG. 1) and the step of FIG. 1 (d), under the same miniaturization pattern conditions, despite the fact that the trench is a high aspect groove between metal wiring layers corresponding to a thicker metal wiring layer, There is no insufficient etching or side etching as shown. That is, in the conventional method, as is apparent from FIG. 4, the thick metal wiring film targeted by the present invention is not made a single layer to have a predetermined thickness. At this stage, in the present invention, it can be formed by etching and removing the first-layer metal wiring film corresponding to, for example, about 厚 of the target thickness value.

Therefore, as shown in FIG. 2E, a silicon oxide film 6 is formed by a CVD method while the silicon nitride film 4 is left. Thereby, the inside of the pattern groove between the metal wirings shown in FIG. 1D can be filled with the predetermined insulating material. Next, the silicon oxide film thus formed on the entire surface is ground and flattened by a commonly used CMP process so that the surface of the silicon nitride film appears, and FIG. As shown in (1), an insulating film between metal wirings is formed on a silicon substrate based on a predetermined miniaturized pattern. As described above, the thickness of the insulating film formed in this manner corresponds to the combined thickness of the first-layer metal wiring film 3 and the silicon nitride film 4 still remaining thereon.

Then, although not shown, as shown in FIG. 2 (f), the silicon nitride film 4 remaining stacked on the first metal wiring film 3 is selectively removed by anisotropic etching to obtain the first metal wiring film 3. The surface of the layer metal wiring film appears, and a pattern groove for burying the second layer metal wiring film is formed between the already formed metal wiring insulating films 6. Then, as shown in FIG. 2 (g), the groove structure is coated with a second-layer metal wiring film material 7 by sputtering or CVD so as to fill the groove and cover the entire surface. Then, similarly to the normal CMP
In the treatment, the silicon oxide film surface of the insulating film is ground so as to appear, and the entire surface is flattened.

As a result, as shown in FIG.
A multilayer thick metal wiring film 8 is formed by laminating the second metal wiring film 7 on the layer metal wiring film 3. As a result, a metal wiring film having a thickness of 1.0 μm is formed by this embodiment under the miniaturization condition of 0.5 μm in the wiring design rule. As a result, this wiring film is formed as a fine thick film structure having an aspect ratio of 2.

Further, as already described, even if a high aspect ratio thick metal wiring film is formed under a miniaturized pattern condition as in the conventional example shown in FIG.
In addition, it can be manufactured without generating the side etch 16. Therefore, by combining multi-stage film formation, multi-stage etching, and the like, a third-layer metal wiring film can be further stacked and formed on a second-layer metal wiring film. It is possible to form a layer.

As is apparent from the above, in order to make the metal wiring layer a multilayer thick film under the fine structure pattern, in the present invention, a silicon nitride film is formed on the first metal wiring layer as an intermediate material. The use of the membrane is also a feature in manufacturing.

Therefore, in the present invention, a SiON film, a SiOF film, an HSQ
A low-dielectric-constant insulating film such as a film (hydrogen-containing SOG film), an organic SOG film, or an organic polymer film can be appropriately used as appropriate. Here, in particular, the former SiON film becomes an anti-reflection film in a photolithography process, so that the resolution is improved. As a result, it is possible to realize a thick film even with a fine design rule of 0.35 μm or less. it can.

[0034]

As described above, according to the present invention, the metal wiring layer constituting the fine structure pattern is formed in a large number of times in multiple steps through an intermediate material such as a silicon nitride film in the manufacturing process. By forming a film, a metal wiring layer having a high aspect thickness can be formed under a miniaturized structure from a metal wiring layer which was impossible by the conventional method.

Moreover, by interposing such an intermediate material, ordinary lithography technology-pattern mask-etching process and the like can be effectively combined, so that the metal wiring layer can be easily multi-layered and thickened. In addition, the present invention provides a semiconductor storage having a low-resistance metal wiring layer formed of a finely-divided thick film and a method for manufacturing the same by effectively preventing or suppressing problems such as insufficient etching and side etching during anisotropic etching which are found in conventional methods. can do.

As a result, the resistance of the metal wiring layer can be reduced and the electromigration resistance can be improved while maintaining high integration and miniaturization of the semiconductor device, and charge damage due to electron shading can be reduced as compared with the conventional method. It is.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device for forming a thick metal wiring layer under a fine structure pattern according to the present invention.

FIG. 2 is a conceptual cross-sectional view showing a continuation of the manufacturing process shown in FIG.

FIG. 3 is a conceptual cross-sectional view of a semiconductor device having a thick-film multilayer metal wiring layer of the present invention obtained by the manufacturing steps shown in FIGS. 1 and 2;

FIG. 4 is a conceptual cross-sectional view of a semiconductor device showing a conventional method for forming a thick metal wiring layer by forming a single layer and its problems.

[Explanation of symbols]

1, 11: silicon substrate, 2, 12: base insulating film,
3 ... First layer of metal wiring film, 4 ... Silicon nitride film, 5, 14 ... Photoresist film, 6 ... Silicon oxide film or metal wiring interlayer insulating film, 7 ... Multilayer The second layer of the metal wiring film, 8: Multi-layer metal wiring layer, 13: Thick single-layer metal wiring layer, 15: Insufficient etching (residue), 16: Side etch, 17 ..Charge damage due to electronic shading

Claims (11)

[Claims] 1. A semiconductor device in which an insulating layer is arranged in a pattern groove between a metal wiring layer and a metal wiring layer as a fine structure pattern on an insulating film base of a silicon substrate, wherein the metal wiring layer is formed of a metal of a first layer. A multilayer thick metal wiring layer for forming at least a second metal wiring film on the wiring film, wherein the thickness of the multilayer metal wiring layer is a ratio of the pattern groove depth to a predetermined metal wiring layer width ( A semiconductor device having an aspect ratio represented by (depth / width) of at least about 2. 2. The method according to claim 1, wherein the predetermined metal wiring layer width is 0.35 μm.
2. The semiconductor device according to claim 1, wherein the distance is not less than about m and not more than about 0.5 μm. 3. A first layer metal formed on said base in an intermediate step for forming said multilayer metal wiring layer, wherein said pattern groove depth for forming said insulating film disposed between said metal wiring layers is formed. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a thickness corresponding to a thickness of a stacked structure of a wiring film and a silicon nitride film and a thickness of the multilayer metal wiring layer formed in multiple layers. 4. In a laminated structure of the first metal wiring layer of aluminum or aluminum alloy and the silicon nitride film related to the depth of the pattern groove, each of the layer thicknesses is set to at least about 0.5 μm. Claim 3 characterized by the following:
3. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the thickness of the insulating layer between metal wirings formed in the pattern groove is at least about 1 μm. 6. The method according to claim 1, wherein said multilayer metal wiring layer has a thickness of at least one.
2. The semiconductor device according to claim 1, wherein the distance is set to about μm. 7. The semiconductor device according to claim 1, wherein the second-layer metal wiring film is any one selected from the group consisting of copper, tungsten, silver, and gold. 8. A fine structure pattern of a multi-layer thick metal wiring layer and a metal wiring inter-layer insulating layer in which a metal wiring film composed of at least two layers is laminated as a fine pattern structure on an insulating film base on a silicon substrate. (1) forming a first layer material of a metal wiring film on the substrate,
Next, a silicon nitride film is laminated and further formed through a photoresist, and the silicon nitride film is removed by anisotropic etching with a predetermined metal wiring film pattern mask to form the metal wiring insulating film. Forming a pre-structure of the groove; and (2) using the remaining silicon nitride film as a mask pattern, and further anisotropically etching the first layer material of the metal wiring film corresponding to the groove portion (or the pre-groove structure). Removing and forming a pattern groove for the insulating layer; and (3) an insulating material is coated on the entire surface including the inside of the pattern groove, and the surface of the silicon nitride film below the portion of the metal wiring film pattern remaining. Forming the above-mentioned metal-to-metal wiring insulating layer by flattening according to: Removing the nitride film by selective etching to form a pattern groove for applying the second layer of the metal wiring film; and (5) then forming a second layer material of the metal wiring on the entire surface including the inside of the pattern groove. Forming a multi-layer metal wiring film composed of at least two layers by flattening the surface to match the surface of the inter-metal wiring insulating film formed in the step (3) after coating. A method for manufacturing a semiconductor device, comprising forming a thick multilayer metal wiring film below. 9. A multi-layer thick metal wiring layer having an aspect ratio of the multi-layer metal wiring layer thickness as an aspect ratio expressed by a ratio (depth / width) of the pattern groove depth to a predetermined metal wiring layer width. 9. The method as claimed in claim 8, wherein
13. The method for manufacturing a semiconductor device according to item 5. 10. A second-layer metal wiring material is laminated and formed in said pre-groove structure, and is flattened in accordance with the surface of said inter-metal-wiring insulating film to have a layer thickness of at least about 1 μm. The method for manufacturing a semiconductor device according to claim 8, wherein: 11. The method according to claim 1, wherein the insulating film between metal wires formed in the step (3) is made of a silicon oxide material and has a thickness of at least 1 μm.
The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is formed with a layer thickness near m.