JP2001023917A - Semiconductor device having suppressed fluctuation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the fluctuation of the numbers of impurity atoms included in respective semiconductors, by implanting single ion into each semiconductor by specific plural times a single ion generated through a single-ion implanting apparatus. SOLUTION: In a silicon chip 2 present in a silicon wafer 1, a MOSFET integrated circuit 3 are included. Accompanied by fining a semiconductor device in the direction of an arrow 5, a channel region 4 of a MOSFET of the constituent of each MOSFET integrated circuit 3 is fined into the ones shown by 4-1, 4-2, 4-3, and variation of the numbers of impurity atoms 11 included in the respective channel region 4 is generated in the direction of the arrow 5. In the particularly fined channel region shown by 4-3, there are the one having the impurity atoms 11 and the one having no impurity atom 11. A single ion 8 generated through a single-ion implanting apparatus 7 is implanted by specific plural times into each fined channel region shown by 4-3 to correct the fluctuation of the numbers of the impurity atoms 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memory) constituting a semiconductor large-scale integrated circuit.
y), SRAM (Static Randam Access Memory), EE
PROM (ElectricalErasable Programmable Read Onl)
y Memory), Flash memory, CMOS (Complementary M
etal Oxide Semiconductor), Bi-CMOS (Bipolar
CMOS), FRAM (Ferroelectric Randam Access)
Memory), a bipolar transistor, or a MESFET, MOSFET,
Partially depleted SOIMOSFET, fully depleted SOIMO
SFET, a device for a pixel constituting an image sensor such as a CCD or a CID, a two-dimensional electron gas device, a single electron transistor, a quantum wire, a quantum box, a quantum dot device, a laser diode (LD), A light emitting device such as an LED, or a light receiving device, or a light emitting-receiving device, or a compound semiconductor device such as a heterojunction bipolar transistor;
Or, in the field of superconducting elements such as Josephson elements, etc., or all kinds of semiconductors, superconductors, resistors, inductors, capacitors, diodes, three-terminal devices, four-terminal devices, etc. The present invention relates to a semiconductor device in which fluctuation of the number of impurity atoms contained in a semiconductor is suppressed by implanting generated single ions one by one into the semiconductor.
All semiconductor devices that are expected to improve performance by suppressing fluctuations in the number of impurity atoms contained in the semiconductor are included.

[0002]

2. Description of the Related Art SIA Roadmap (The National Tec
hnology Road-Map for Semiconductors, Semiconductor
According to Industry Association, San Jose, CA, 1997 revision), the number of impurity atoms contained in the channel region of a 100 nm MOSFET is several hundred. The fluctuations are several tens, which seriously affects the operation and function of the semiconductor device and the yield of a system such as a large-scale integrated circuit composed of micro semiconductor devices. Therefore, 1
Impurity control on the order of zero is required. With the conventional ion implantation technology and impurity diffusion technology, it has been impossible to suppress such fluctuations in the number of impurity atoms on the order of ten atoms.

[0003] On the other hand, research for investigating the fluctuation of impurities theoretically or experimentally has increased in recent years. However, there have been very few proposals on techniques effective for suppressing fluctuations.

[0004] In 1991, Iwao Ohdomari, Masaaki Sugimori, Junichi Murayama, Huangmei plantation, Noritake Katsushi, Takashi Matsukawa and Hiroaki Shimizu were the first in the world to extract a single ion and a given number of arbitrary ions with good controllability. Experimentally successful. That is, 7-7
No. 5156, “Ion irradiation apparatus and method” (Patent No. 205)
No. 1859 (Registration date: May 10, 1996)
Day)). Similarly, US Pat. No. 5,331,161 (registered July 1, 1994)
9th).

Further, in 1993, by Iwao Ohdomari, in an ion implantation apparatus using a focused ion beam (FIB) or a micro-ion beam (MIB) using an ion microprobe, particularly, a target portion is irradiated with ions 1 with a predetermined irradiation accuracy. A single ion device and method capable of implanting a single ion or a controlled number of ions with high precision or a controlled predetermined number of ions have been developed and disclosed in Japanese Patent No. 2731886 (registered date 1997 (1997)). ) Dec. 26) "Single Ion Implantation Apparatus and Method". Similarly, U.S. Pat.
No. 9,203 (registered July 23, 1996).

[0006] Subsequent to the above two prior arts, instead of the chopping method of chopping a focused ion beam to extract single ions, a new voltage is applied to a single ion extraction aperture by applying a pulse voltage to extract single ions. A high-definition single ion implantation apparatus and method based on the method were also invented by Iwao Ohdomari, Yoshihiro Shinada, Huang Ming, and Atsushi Ishikawa, and filed in Japanese Patent Application No. 11-187323 (filing date: July 1999 (1999)). 1) High-definition single ion extraction method and high-definition single ion implantation apparatus and method to which the method is applied are disclosed.

The single ion implantation technique (SII) is an effective technique for suppressing the fluctuation of impurities.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a single ion generated by a single ion implanter is implanted into a semiconductor by single ion implantation to suppress fluctuations in the number of impurity atoms contained in the semiconductor. Is to do.

Another object of the present invention is to extract single ions using a single ion implantation apparatus based on a chopper method or an electric field control method as a single ion extraction method, and perform single ion implantation one by one. Another object of the present invention is to provide a semiconductor device in which fluctuations in the number of impurity atoms are suppressed.

Another object of the present invention is to realize a MOSFET in which single ions are implanted one by one into a channel region of a MOSFET by a single ion implantation method to perform a channel doping for threshold setting to suppress fluctuation. It is an object of the present invention to provide an improved semiconductor device.

Another object of the present invention is to provide an nMOSFET and a pMOSFET by a single ion implantation method.
CMOSFET in which single ions are implanted one by one into the channel region of FIG.
And to provide a semiconductor device in which fluctuation is suppressed.

It is another object of the present invention to provide a semiconductor device in which fluctuations are suppressed from the beginning, by performing a threshold setting channel doping by a single ion implantation method after an element isolation step, before or after forming a gate oxide film. And to provide a semiconductor device in which fluctuation is suppressed.

Another object of the present invention is to evaluate the initial characteristics after forming the gate, source and drain electrodes, specify the location and amount of fluctuation, and perform single ion implantation through the gate electrode under high energy conditions. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which fluctuations are suppressed in order to correct electric characteristics of a semiconductor device in which fluctuations have occurred in advance.

[0014]

The structure of the present invention to achieve the above object is as follows. That is, a single ion implanted by a single ion implanter is implanted into a semiconductor to suppress the fluctuation of the number of impurity atoms contained in the semiconductor by implanting a single ion into the semiconductor. Having.

Alternatively, the fluctuation of the number of impurity atoms contained in the channel region is suppressed by implanting a single ion generated by the single ion implantation apparatus into the channel region of the MOSFET. It has a configuration as a suppressed semiconductor device.

Alternatively, single ions generated by a single ion implanter are implanted into the n-channel region and the p-channel region of the CMOSFET, respectively.
The semiconductor device has a configuration in which fluctuation of the number of impurity atoms included in each of the channel regions is suppressed, and the fluctuation is suppressed.

Alternatively, a single ion generated by a single ion implantation apparatus is implanted into a semiconductor by single ion implantation, thereby suppressing fluctuation of the number of impurity atoms contained in the semiconductor and correcting the number of impurity atoms in the semiconductor. Characterized in that conductance or inductance or capacitance has been made uniform by
The semiconductor device has a configuration in which fluctuation is suppressed.

Alternatively, in a semiconductor device in which the fluctuation of the number of impurity atoms contained in the channel region is suppressed by implanting single ions generated by a single ion implantation device into the channel region of the MOSFET, The step of implanting a single ion is performed through the gate oxide film after the formation of the gate oxide film, and the threshold setting channel doping is performed by the single ion implantation. Having a configuration.

Alternatively, in a semiconductor device in which fluctuation of the number of impurity atoms contained in the channel region is suppressed by implanting single ions generated by a single ion implantation device into a channel region of the MOSFET, The step of implanting a single ion is performed after the element isolation step and before the formation of the gate oxide film, and the threshold setting channel doping is performed by the single ion implantation. It has a configuration as a suppressed semiconductor device.

Alternatively, single ions generated by a single ion implanter are implanted into the n-channel region and the p-channel region of the CMOSFET, respectively, to thereby reduce the number of impurity atoms contained in the n-channel region and the p-channel region, respectively. The step of implanting single ions into the n-channel region and the p-channel region is performed after the element isolation step and before forming the gate oxide film. Accordingly, the semiconductor device has a configuration as a semiconductor device in which fluctuation is suppressed, characterized in that threshold setting n-channel doping and p-channel doping are respectively performed.

Alternatively, in a semiconductor device in which fluctuation of the number of impurity atoms contained in the channel region is suppressed by implanting single ions generated by a single ion implantation device into the channel region of the MOSFET, In the step of single ion implantation, after forming the gate, source and drain electrodes, the electrical characteristics are evaluated to determine the location and amount of fluctuation,
The semiconductor device has a configuration as a semiconductor device in which fluctuation is suppressed, which is performed through the gate electrode under a high energy condition.

Alternatively, single ions generated by a single ion implanter are implanted into the n-channel region and the p-channel region of the CMOSFET, respectively, to thereby reduce the number of impurity atoms contained in the n-channel region and the p-channel region. In the semiconductor device in which the fluctuation of the current is suppressed, the step of implanting a single ion into each of the n-channel region and the p-channel region is performed by evaluating the electrical characteristics after forming the gate, source, and drain electrodes of the CMOSFET and evaluating the location and amount of the fluctuation. After that, the method is performed through the gate electrode under a high energy condition, and has a configuration as a semiconductor device in which fluctuation is suppressed.

The application range of the present invention is extremely wide. For example, DRAM, SRA constituting a semiconductor large-scale integrated circuit
M, EEPROM, Flash memory, CMOS, Bi-C
Transistor for controlling MOS and FRAM, or bipolar transistor, thyristor, GTO, IGB
T or MESFET, MOSFET, partially depleted S
OIMOSFETs, fully depleted SOIMOSFETs, pixel devices constituting image sensors such as CCDs and CIDs, two-dimensional electron gas devices, single electron transistors, quantum wires, quantum boxes,
Quantum dot device or laser diode (L
D), a light emitting device such as an LED, or a light receiving device;
Alternatively, a light-emitting / light-receiving device, a compound semiconductor device such as a heterojunction bipolar transistor, or a superconducting element such as a Josephson device, or a resistor, an inductor, a capacitor, a diode, or a three-terminal generally using any semiconductor or superconductor. It can be applied to devices, four-terminal dehice, etc. In particular, all semiconductor devices that are expected to improve performance by suppressing fluctuations in the number of impurity atoms contained in the semiconductor by implanting single ions one by one into the semiconductor by single ions generated by the single ion implantation technique. Is included.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram schematically showing the principle of operation of a semiconductor device according to the present invention in which fluctuation is suppressed. It schematically illustrates the fluctuation of impurity atoms due to miniaturization of a semiconductor device and the state of fluctuation correction by a single ion implantation method. That is, in FIG. 1, 1 is a silicon wafer, 2 is a silicon chip, 3 is a MOSFET integrated circuit, 4-1, 4-2, 4-3 are channel regions, 5,
6 and 9 are arrows for explanation, 7 is a single ion implanter (schematic display), and 8 is a single ion.

Referring to FIG. The silicon chips 2 in the silicon wafer 1 include the MOSFET integrated circuits 3, and the channel regions 4 of the MOSFETs constituting these MOSFET integrated circuits 3 are accompanied by miniaturization of the semiconductor device in the direction indicated by the arrow 5. , 4-1 and 4-
It is miniaturized as shown in 2, 4-3. Black circles (●) schematically show the impurity atoms 11 contained in the channel regions 4-1, 4-2, and 4-3. With the miniaturization of semiconductor devices, the impurity region atoms 11 vary in the channel. In particular, in the channel region 4-3 which is finer than the channel region 4-1, there are a channel region in which the impurity atoms 11 exist and a channel region in which the impurity atoms 11 do not exist at all.
As described above, with the miniaturization of semiconductor devices, arrows 6
As shown by, the fluctuation of the number of impurity atoms also increases. This causes variations in the electrical characteristics of the miniaturized MOSFET device, particularly the threshold voltage _Vth . Therefore, as shown by the arrow 9, the operation principle of the present invention is to correct the number of impurity atoms by the single ion implantation method. That is, a single ion implanter (schematic display) 7
Single ions 8 are implanted into each of the miniaturized channel regions 4-3 to correct fluctuations in the number of impurity atoms. The single ion 8 into which the single ion has been implanted is indicated by a white circle (○) in FIG. In the silicon wafer 1 in which the number of impurity atoms has been corrected by the single ion implantation method, the number of impurity atoms in active channel regions 4-1, 4-2, and 4-3 of a semiconductor device such as a MOSFET is made uniform. In particular, the present invention provides a technique which is extremely effective in suppressing variations in device electrical characteristics in a miniaturized MOSFET.

FIGS. 2 and 3 show a state in which the conductance is made uniform and the resistance value is trimmed as a result of performing single ion implantation into the channel region of the MOSFET in the semiconductor device of the present invention in which fluctuation is suppressed. Figure 2 shows a MOSFET to which the single ion implantation technology is applied.
3 is an SEM photograph mainly of a channel region portion. The channel width is 0.3 μm, and the source and drain regions are shown. MOSFET integrated circuit 3 in silicon chip 2 manufactured in large numbers on silicon wafer 1 shown in FIG.
FIG. 3 is a diagram schematically showing a graph in which the conductance in the channel region 4 is plotted on the horizontal axis and the frequency is plotted on the vertical axis in such a MOSFET constituting the MOSFET. Before the single ion implantation, that is, before compensating the variation of the impurity atoms in the channel region 4, the conductance varies considerably as shown in FIG. In contrast, when single ion implantation is performed on the channel region 4, variation in conductance can be suppressed as shown in FIG. That is, variation in the number of impurity atoms in the channel region 4 between MOSFETs can be suppressed to a considerable extent.

The main embodiments of the semiconductor device of the present invention in which the fluctuation is suppressed are as follows. That is, a semiconductor device in which fluctuation of the number of impurity atoms contained in a semiconductor is suppressed by implanting single ions into the semiconductor. Resistance, capacitor, inductor, diode, three-terminal device, four-terminal device, MOSFET, MESF
ET, CMOSFET, two-dimensional electron gas device, laser diode, light emitting diode, light receiving element, light receiving
Light-emitting device, image sensor device such as CCD, quantum wire, quantum box, quantum dot, device having quantum well structure, single electron transistor, bipolar transistor,
Heterojunction bipolar transistor, thyristor, GT
By applying the present invention to O, IGBT, MCT, superconducting element, and the like, a semiconductor device in which fluctuation in the number of impurity atoms is suppressed can be provided. In particular, in an integrated device, an integrated light receiving device, an integrated light emitting device, an integrated power device, and the like having a configuration in which a large number of basic unit elements are arranged, variations in characteristics of individual basic unit elements can be suppressed by the present invention. It is expected to greatly improve performance. Basic elements such as resistors, capacitors, and inductors can also be implemented by the semiconductor device of the present invention in which fluctuations are suppressed. Since such variations in the basic elements can be suppressed, application to linear integrated circuits such as A / D, D / A converters, and operational amplifiers is also effective. Alternatively, a single ion ion sensor,
Various medical sensors can be realized with high sensitivity.

With respect to a single ion implantation apparatus which is important in implementing the structure of the present invention, in principle, an ion beam is deflected by a chopper voltage applied to a deflection plate, and a single ion is passed through a slit by chopping. There are a chopping method for extraction and an electric field control method for extracting a single ion by applying a pulse voltage to a single ion extraction aperture to control an electric field in a potential distribution in an ion flow passage region. The irradiation accuracy of the chopping method has been on the submicron order so far, and the orbit of the ion beam does not fluctuate in the electric field control method, so single ion implantation with higher definition can be performed.
Aiming accuracy on the order of nanometers has been achieved.

Which single ion implantation apparatus is used can be appropriately selected depending on the dimensions of the target semiconductor device and the required dimensional accuracy. For example, when a single ion implantation technique is used to manufacture a 10 nm-order quantum wire or quantum box, an electric field control method is suitable. The electric field control method is also suitable for manufacturing a MOSFET having a channel length and a channel width on the order of 100 nm. On the other hand, in the case of micron order or submicron order, a single ion implantation apparatus based on the chopping method can be adopted.

[0030]

FIGS. 4 and 5 are schematic structural views of a single ion implantation apparatus which is an essential component when forming a semiconductor device in which fluctuations are suppressed according to the present invention. FIG. 4 shows an example employing the beam chopping method. FIG. 5 shows an example in which a pulse voltage is applied to a single ion extraction aperture to control the potential distribution in the ion flow passage region with an electric field to extract a single ion.

In an ion implantation apparatus using an ion microprobe, an ion irradiation apparatus capable of irradiating a single ion or a controlled predetermined number of ions with high accuracy to a target portion, in particular, a single ion or a controlled predetermined number of ions. And Iwao Ohdomari, Masaaki Sugimori,
It is proposed by Junichi Murayama, Huang Ming, Noritake, Takashi Matsukawa, Hiroaki Shimizu, and Japanese Patent Publication No. 7-75156, "Ion irradiation apparatus and method" (Patent No. 2051859 (registered date May 10, 1996). Day)).
Also disclosed in U.S. Pat. No. 5,331,161 (registered July 19, 1994).

Furthermore, in an ion implantation apparatus using a focused ion beam (FIB) or a micro ion beam (MIB) using an ion microprobe, one ion or a controlled number of ions is irradiated to a target portion with a predetermined irradiation accuracy. A single ion apparatus and a single ion apparatus capable of accurately implanting ions or a single ion capable of controlling a predetermined number of ions are also proposed by Iwao Ohdomari and disclosed in Japanese Patent No. 2731886 (registered date 1997 (19)
1997) (December 26). Also disclosed in U.S. Pat. No. 5,539,203 (registered Jul. 23, 1996).

A high-definition single ion implantation apparatus based on an electric field control method has been proposed and realized by Iwao Ohdomari, Yoshihiro Shinada, Huang Ming, and Atsushi Ishikawa. High-Definition Single Ion Implantation Apparatus and Method Applying Method "
Filed on July 1, 1 year.

The operation of the single ion implantation apparatus shown in FIG. 4 and FIG. 5 and the configuration of each part are described in detail in the above-mentioned prior art, so that the description is omitted. A characteristic point is that in the chopping method of FIG. 4, the chopper controller controls the voltage applied to the chopping deflection plate by the signal of the secondary electrons detected by the secondary electron detector. In the electric field control method, the chopper controller controls the voltage applied to the single ion extraction aperture based on the secondary electron signal detected by the secondary electron detector.

(Embodiment 1) FIGS. 6 and 7 show a first embodiment of the present invention.
1 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as an example of FIG. It corresponds to MOSFET of SOI structure. The gate electrode arranged at the top is shown in FIG.
And are omitted in the examples of FIG. FIG. 6 is a bird's-eye view, and FIG. 7 is a sectional structural view. 6 and 7, the channel length is 2 μm, the channel width is 1 μm, and 2 μm × 1 μm.
With respect to the channel region 4 of m, a channel region divided into small regions of 0.5 μm × 0.5 μm was set, and single ion implantation was performed to achieve uniformity and correct fluctuation of the number of impurity atoms. As will be described later, the relationship between the number of implanted ions by single ion implantation and the flat band voltage, and the relationship between the number of implanted ions and conductance were examined, and the effect of the present invention of suppressing the fluctuation of the semiconductor device was confirmed.
This will be described in detail below.

6 and 7, the substrate bias voltage V
_BG is varied from 0 to 6V. The upper gate electrode is
Although omitted as described above in FIGS. 6 and 7, the SOIMO
It is provided as an SFET. 6 and 7, 8 is a single ion, and x is the surface of the upper SiO ₂
10 is an ohmic contact for source and drain regions, 12 is an upper silicon layer, an n ⁻ layer, 13 is embedded SiO ₂ , 14 is a silicon substrate, and 15 is 0.5 μm × 0.5 μm single ion implantation region, 16 indicates the entire SIMOX substrate,
Reference numeral 7 denotes an upper SiO ₂ , and reference numerals 30 and 31 denote a source region and a drain region as n ⁺ regions formed in the upper silicon layer 12. The upper SiO ₂ 17 has a thickness of 25 nm, the upper silicon layer 12 has a thickness of 90 nm, and the buried SiO ₂ 13 has a thickness of 90 nm. Although electrodes for measuring and evaluating the conductance g by the four-probe method are also arranged in FIG. 6, it is needless to say that the electrodes are not essential to the MOSFET.

An nMOSFET (back gate MOSF) fabricated by using a SIMOX substrate 16 with divalent P ions
ET) channel region 4 (1 μm × 2 μm)
m), single ions were implanted at an acceleration energy of 60 keV. In order to avoid the influence of the device size variation, an experiment was conducted with an nMOSFET having a relatively large size, but it is apparent that a finer device may be used. As shown in FIGS. 6 and 7, 10 to 250 ions are each submicron semiconductor region (0... 0) at 0.5 .mu.m pitch using a single ion implanter.
(5 μm × 0.5 μm). The number of ions actually implanted into the channel region 4 is determined by the secondary electron detection rate and the rate of staying in the upper silicon layer 12. For details of these, see the following literature, T. Shinada, A.
Ishikawa, M. Fujita, K. Yamashita and I. Ohdomari, Jpn.
J. Appl. Phys, 38 (1999).

In order to electrically activate the implanted ions,
900 ° C., 5 min. The sample was heat-treated in N ₂ under the following conditions. Source-drain voltage V _D is a 0.1V under certain conditions, the results of evaluation of the substrate bias voltage V _BG independent of the drain current I _D in Figure 8. In FIG. 8, the parameters of the three curves correspond to the number of implanted ions [(0.5 μm) ⁻² ] of 10, 25, and 100.
The flat band voltage V _FB is evaluated by extrapolating the linear portion of the _ID- V _BG characteristic shown in FIG. 8 to the V _BG axis, and the flat band voltage V _FB and the number of implanted ions [(0.5 μm) ⁻² ] The relationship was investigated. In FIG. 8, the number of implanted ions [(0.5 μm
m) ^-2 ] are 10, 25, and 100, respectively, and the flat band voltages V _FB (V) are 3.15 V and 3.0, respectively.
6V and 2.66V can be estimated. That is, the flat band voltage V _FB decreases as the number of implanted ions increases.

FIG. 9 shows the relationship between the flat band voltage V _FB and the number of implanted ions [(0.5 μm) ⁻² ] based on such a result. From this, it was confirmed that the flat band voltage V _FB decreased linearly with the increase in the number of implanted ions. This result indicates that the control of the number of impurity atoms on the order of 10 is realized by the single ion implantation method. Slope of 9, one ion represents a decrease of contributing flat band voltage V _FB, -4.5mV / ion - could be evaluated as [(0.5μm) ^2]. This number by calculation to be described later, estimated values -6~-2mV / ion - in the range of [(0.5μm) ^2]. V _FB = 3.2 V as y-intercept in FIG.
Can be evaluated as a voltage necessary to suppress a rise in potential due to an interface state. Figure 9 shows the dose
[cm ^-2 ] is also displayed.

Next, the conductance g is determined by the four probe method.
Are shown in FIG. In order to suppress the potential rise due to the interface state, the substrate bias voltage V _BG
= 3.2 V was applied and the conductance g was measured. The conductance g [μS] and the number of implanted ions [(0.
5 μm) ⁻² ] is shown in FIG. Number of implanted ions
With the increase of [(0.5 μm) ^-2 ], the conductance g
[μS] was confirmed to increase linearly. This indicates that the control of the number of dopants on the order of 10 is realized by the single ion implantation technique. Further, from the slope of FIG. 10, the increase in conductance per ion could be evaluated as 17.9 nS / ion [(0.5 μm) ⁻² ]. This numerical value substantially coincides with a calculated value 21.9 nS / ion [(0.5 μm) ⁻² ] described later. In FIG. 10, the dose [cm ^-2 ]
Is also displayed.

In order to evaluate the effect of the substrate bias voltage V _BG on the band structure, a device simulator PI
The potential structure of the channel region 4 in the fluctuation-suppressed semiconductor device according to the first embodiment of the present invention was calculated using SCES-II. In the calculation, V _D =
The voltage was set to 0.1 V, and the three interfaces shown in FIG. 7 were obtained, namely, interface 1 upper SiO ₂ (17) / upper silicon layer (12) interface 2 upper silicon layer (12) / buried SiO ₂ (13) interface 3 It was assumed that the interface state densities in the buried SiO ₂ (13) / silicon substrate (14) were equal. Table 1 summarizes the parameters of the interface state density and the substrate bias voltage _VBG used in the simulation.

[0042]

[Table 1]

Case (1) shown in Table 1
(2), depth in the x-axis direction corresponding to case (3)
The result of calculating the potential structure for x (nm)
The results are shown in FIG. In case (1), the interface state density Nit =
0, substrate bias voltage V_BGIf = 0, case (2) is
Interface state density Nit = 5 × 10^Ten [cm^-2], Substrate via
(3), the interface state density Nit =
5 × 10^Ten [cm^-2], Substrate bias voltage V _BG= 3.2
 This corresponds to the case of [V].

In FIG. 11, the intrinsic Fermi level Ei
With reference to the potential Ec-Ei determined by the equation (1), the potential energy for electrons is conventionally displayed as positive upward. In the depth x direction, upper SiO ₂
17 thickness 25 nm / top silicon layer 12 thickness 90 n
m / buried SiO ₂ thickness 90 nm / silicon substrate 14
Displayed as Thus, it is possible to see how the potential distribution of the channel region 4 changes in the depth x (nm) direction. When there is no interface state, the potential distribution of the channel region 4 is as shown in case (1) in FIG. When the substrate bias voltage V _BG is not applied, it can be seen that the potential increases due to the presence of the interface state and the channel region 4 is depleted, as in the case (2) in FIG. In this case, the electrical characteristics of the device cannot be accurately evaluated. As shown in case (3), by applying the substrate bias voltage V _BG ,
It was found that depletion due to interface states can be suppressed. This is very important for correctly evaluating the electrical characteristics of the completely depleted small semiconductor channel region as in the case (2).

Here, I _D -V _BG characteristics will be derived. _ID
The -V _BG characteristic is given by the following equation.

[0046]

I _D = (W / L) μqnV _D (1)

Here, W is the channel width, L is the channel length, q is the unit charge, n is the electron concentration, and μ is the mobility. The total charge induced in the channel region 4 is given by the following equation.

[0048]

[Number 2] _{n = qηN D + qN DO +} C T V BG -Qit (2)

[0049] Here, N _DO impurity concentration initial value, N _D is the impurity concentration, eta is the electrical activation ratio of implanted ions, C _T is the total capacitance per unit area, Qit is the carrier trap charge. By substituting equation (2) into equation (1), the following equation is obtained.

[0050]

[Number 3] _{I D = (W / L)} μ (qηN D + qN DO + C T V BG -Qit) V D = (W / L) μC T (V BG -V FB) V D (3)

Here,

[0052]

[Number 4] _{V FB = (Qit-qηN D} -qN DO) / C T (4)

Is as follows. In the formula (4), Qit is the number of carrier traps, qηN _D is the number of implanted ions, qN _DO originally can be thought of as corresponding to the number of impurity atoms present in the sample. Equation (4) shows that the flat band voltage V _FB increases as the number of implanted ions increases. From equation (3), no current flows when V _BG <V _FB and V _BG
It can be seen that for> V _FB , the drain current _ID increases linearly with the substrate bias voltage V _BG . Based on Equation (3), it can be seen that V _FB can be obtained from the _ID- V _BG characteristics shown in FIG.

[0054] inclination ∂V _FB / ∂N _D in FIG. 9 represents a flat band voltage decrease per ion. From equation _{(4), ∂V FB / ∂N} D = -qη / C T = -6.0~-1.9mV / ion [(0.5μm) -2] where, C as determined by high-frequency CV method _{The T} value was used for the calculation.

Similarly, from the equation (1), the conductance g
Is represented by the following equation.

[0056]

[Number 5] _{g = qμηN D (W / L} ) (5)

The slope in FIG. 10 can be calculated as follows: ∂g / ∂N _D = qμη (W / L) = 21.9 nS / ion [(0.5 μm) ⁻² ]

Device simulator PISCES-II
There is good agreement between the theoretical calculations using and the experimental results. From this, the single ion implantation method has
It was shown that zero order dopants were controlled. The flat band voltage decrease per ion is -4.5 mV / ion. That is, the effect of one ion on the electrical characteristics of the semiconductor was shown. This indicates that a very small number of impurity atoms was successfully controlled by the single ion implantation method.

(Embodiment 2) Various examples can be implemented as to at what stage in the process single ion implantation is performed. After the formation of the gate oxide film, a single ion is implanted through the gate oxide film to form a semiconductor device in which the fluctuation is suppressed.

(Embodiment 3) On the other hand, a semiconductor device in which fluctuation is suppressed from the beginning can be manufactured. In this case, as in a normal semiconductor process, after the element isolation process by LOCOS and before forming the gate oxide film, threshold setting channel doping is performed by a single ion implantation method.

FIGS. 12 and 13 are schematic sectional structural views for explaining a single ion implantation step of a fluctuation-suppressed semiconductor device as a third embodiment of the present invention when a bulk CMOS is formed as a target device. . FIG. 12 corresponds to before a single ion implantation, and FIG. 13 corresponds to a single ion implantation step.

12 and 13, reference numeral 20 denotes a silicon substrate, 21 denotes a p-well region, 22 denotes an n-well region,
-1, 23-2 are regions where channels are formed, and 24 is L
4 shows an element isolation region by OCOS. 7 schematically shows a single ion implantation apparatus, and 8 shows a single ion to be implanted. Reference numerals 25 and 26 schematically show the ions implanted into the p-well region 21 and the n-well region 22 one by one. As shown in FIGS. 12 and 13, in the process of the semiconductor device in which fluctuation is suppressed as the third embodiment of the present invention, as shown in FIGS.
After the element isolation process by the method described above, and before forming a gate oxide film, threshold setting channel doping is performed by a single ion implantation method.

(Embodiment 4) FIGS. 14 and 15 are schematic diagrams for explaining a single ion implantation step of a semiconductor device in which fluctuation is suppressed as a fourth embodiment of the present invention when an SOI-CMOS is formed as a target device. FIG. 14 corresponds to a single ion implantation step, and FIG. 15 corresponds to a single ion implantation step. 14 and 15,
20 is a silicon substrate, 23-1 and 23-2 are regions where channels are formed, 24 is a device isolation region by LOCOS, 13 is buried SiO ₂ , 12 is source / drain /
5 shows an upper silicon layer in which a channel region is formed, and is a region where a p-well region 21 and an n-well region 22 are to be formed, respectively. 7 schematically shows a single ion implantation apparatus, and 8 shows a single ion to be implanted. Numerals 25 and 26 schematically show single ions implanted one by one into the p-well region 21 and the n-well region 22, respectively. In the semiconductor device in which fluctuation is suppressed as the fourth embodiment of the present invention, FIGS.
As shown in (1), after the element isolation process by LOCOS and before the formation of the gate oxide film, channel doping for threshold setting by single ion implantation is performed.

Fifth Embodiment In the third and fourth embodiments, a semiconductor device in which fluctuation is suppressed is formed from the beginning. However, single ion implantation is used to correct a semiconductor device in which fluctuation has occurred. You can also. In this case, in order to investigate the electrical characteristics of the device before correction, an electrode for detecting them is required. Therefore, after forming the gate, source, and drain electrodes, the initial characteristics are evaluated, and the location and degree of fluctuation of the number of impurity atoms are specified. Single ion implantation is performed through a gate electrode under high energy conditions.

FIGS. 16 and 17 are schematic structural views of a semiconductor device in which fluctuation is suppressed as a fifth embodiment of the present invention. FIG. 16 corresponds to a single ion implantation step, and FIG. 17 corresponds to a single ion implantation step. In the process of forming the bulk CMOS, after forming the gate, source, and drain electrodes, the initial characteristics are evaluated, and the amount and location of fluctuation of the number of impurity atoms are specified. Through this process, channel doping for threshold setting is performed by a single ion implantation method through a gate electrode under a high energy condition to correct the fluctuation of the impurity atoms in the channel region of the semiconductor device in which the fluctuation has occurred.

In FIGS. 16 and 17, nMOS, pM
A gate oxide film for forming the OS is omitted in the figure. Reference numeral 20 denotes a silicon substrate, 21 denotes a p-well region, 22 denotes an n-well region 24 denotes an element isolation region by LOCOS. Reference numerals 30 and 31 denote source / drain regions of the nMOS, and reference numerals 32 and 33 denote source / drain regions of the pMOS. 27 denotes a source electrode (nMOS side), 28 denotes a drain electrode, and 29 denotes a source electrode (pMOS side). Three
Reference numerals 4 and 35 denote gate electrodes of the nMOS and the pMOS, respectively. Numerals 36 and 37 schematically show impurity atoms existing in the channel regions of the nMOS and pMOS, respectively, and schematically show how the number of impurity atoms fluctuates. After the initial characteristics are evaluated after the formation of the gate electrodes 34 and 35, the source electrodes 27 and 29, and the drain electrode 28 to determine the amount and location of the fluctuation in the number of impurity atoms, the single ion implanter 7 generates the signal. Single ions 8 are implanted one by one under high energy conditions through gate electrodes 34 and 35. 38,3
Reference numeral 9 schematically shows the state of the ions thus implanted one by one. The number of implanted ions in single ion implantation is determined according to the amount of fluctuation of the impurity atoms, and the fluctuation of the impurity atoms is corrected.

(Embodiment 6) FIGS. 18 and 19 are schematic structural views of a semiconductor device in which fluctuation is suppressed as a sixth embodiment of the present invention, and particularly, an example in which an SOI-CMOS is formed. 18 corresponds to a single ion implantation step, and FIG. 19 corresponds to a single ion implantation step. In the sixth embodiment, as in the fifth embodiment, after forming the source electrodes 27 and 29, the drain electrode 28, and the gate electrodes 34 and 35, the initial characteristics are evaluated, and the amount and location of the fluctuation of the impurity atoms are specified. I have.
After that, single ions are implanted one by one to correct the fluctuation of the impurity atoms. Since the same reference numerals are displayed for the same components as those in FIGS. 16 and 17, the description of each part is omitted. Also,
Also in FIGS. 18 and 19, the gate oxide film is omitted and not shown.

The location of single ion implantation can be determined, for example, in a channel region, a source region, a drain region, a polysilicon gate region, and the like. In order to suppress fluctuations in device characteristics such as a threshold value by controlling impurity atoms in a semiconductor device channel, it is effective to perform a single ion implantation method as a channel doping technique. For this purpose, single ion implantation into the channel region is particularly important. DR
AM, SRAM, EEPROM, Flash memory, CMO
Single transistor for controlling S, Bi-CMOS, FRAM, MESFET (n-type, p-type), MOST (n
Type, p-type), partially depleted SOI-MOST (n-type, p-type)
Of course, single ions can be implanted into each channel region of the SOI-MOST (n-type, p-type) and compound semiconductor devices. Since the doping of the source region, the drain region, and the polysilicon is originally a relatively high dose, it may not be possible to expect a remarkable effect by controlling the impurities one by one.
However, the present invention can be implemented in resistance value trimming control or the like. This is because variation in conductance can be controlled as shown in FIG. Therefore, decrease -4.5mV / ion of the flat band voltage V _FB per ion [0.5μm) - ^2], the data of the increment 17.9nS / ion conductance g [0.5μm) ^-2] Utilizes very sensitive linear and linear I
It is also possible to implement a C operational amplifier or a highly sensitive sensor array.

Further, a single ion ion sensor, pH
Sensors and various medical sensors can be realized with high sensitivity.

Further, in the manufacture of a device for each pixel constituting an image sensor such as a CCD or a CID, if a single ion implantation technique is applied to a transfer channel region, variation in pixel sensitivity can be suppressed.
FPN (fixed pattern noise) can also be suppressed.

Further, by applying the single ion implantation technique to a two-dimensional electron gas region serving as a channel region of a two-dimensional electron gas device such as a HEMT, a semiconductor device in which quantum fluctuation is suppressed can be realized. Furthermore, quantum wires,
It can also be applied to quantum boxes, quantum dots, and superlattice structures.

In particular, in the formation of a quantum well (QW) using a 10 nm-class thin film, a semiconductor laser, a superlattice structure, a memory using a self-formed single electron (dot), a 10 nm-class edge quantum wire, and a 10 nm-class ridge wire. In addition, it is possible to realize a semiconductor device in which fluctuation is suppressed.

The structure of the semiconductor device is not limited to the planar structure, but can be applied to a vertical structure, a trench structure and the like.

In the semiconductor device of the present invention in which fluctuations are suppressed, there are many types of single ions to be implanted by single ion implantation in manufacturing the semiconductor device. The ions generated from the liquid metal ion source, the ions generated from the ion source by the gas source, the ions of the atoms serving as the dopant of the semiconductor, and the like are the ions that can be implanted as a single ion.

According to the semiconductor device of the present invention in which fluctuations are suppressed, as ions of atoms serving as a dopant of a semiconductor or various kinds of ions which can be constituted as a liquid metal ion source, for example, ions of boron (B), silicon (Si) ) Ions, phosphorus (P) ions, copper (Cu) ions, gallium (Ga) ions, germanium (Ge) ions,
As arsenic (As) ions, gold (Au) ions, or various ion species that can be configured as an ion source by a gas source, for example, hydrogen (H) ions, helium (H)
e) ion, oxygen (O) ion, argon (Ar)
One ion selected from the above-mentioned ions and the like can be used.

In particular, when a high-definition single ion implantation apparatus is used, in a single ion extraction step of extracting ions one by one, a single ion can be easily extracted by changing a pulse voltage applied to a single ion extraction aperture. In addition, since the ion beam does not deviate from an ideal orbit in principle, single ion implantation into the nanometer region can be realized, and high aiming accuracy can be realized.

[0077]

According to the semiconductor device of the present invention in which the fluctuation is suppressed, there is provided a semiconductor device in which the fluctuation of several tens of impurity atoms, which is impossible with the conventional ion implantation technology and impurity diffusion technology, is suppressed. be able to. That is, several tens of impurities can be easily controlled by the single ion implantation method. For example, 100
The number of impurity atoms contained in the channel region of the nmMOSFET is several hundreds, and the fluctuation is several tens. However, in the semiconductor device in which the fluctuation is suppressed according to the present invention, the number is several tens.
Since a single ion implantation technique for implanting individual ions is used, it is possible to suppress variations in electrical characteristics and to achieve uniform conductance in a channel region even in a very miniaturized semiconductor device. Thus, the control of the flat band voltage V _{FB and} the control of the threshold voltage can be performed with the sensitivity per one ion.

According to the semiconductor device of the present invention in which the fluctuation is suppressed, the effect of one ion on the semiconductor electrical characteristics can be grasped. Therefore, the electrical characteristics based on the control of the very small number of impurity atoms can be understood. Uniformity can be achieved.

According to the semiconductor device of the present invention in which the fluctuation is suppressed, the threshold setting channel doping by the single ion implantation method is performed after the element isolation step in the process, before or after the formation of the gate oxide film, and the fluctuation is suppressed from the beginning. A suppressed semiconductor device can also be provided.

Alternatively, according to the semiconductor device of the present invention in which the fluctuation is suppressed, the initial characteristics are evaluated after the formation of the gate, source, and drain electrodes, and the location and amount of the fluctuation in the number of impurity atoms are specified. By performing through a gate electrode under single ion implantation and high energy conditions,
The characteristics of the semiconductor device in which the fluctuation has occurred can be corrected in advance.

According to the semiconductor device of the present invention in which the fluctuation is suppressed, the channel region is divided into minute regions after the single ion implantation step, and the number of impurity atoms contained therein is controlled. Fluctuations in the number of impurity atoms as a whole can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an operation principle of a semiconductor device in which fluctuation is suppressed according to the present invention.

FIG. 2 shows a MOSF to which a single ion implantation technique is applied.
SEM photo of ET mainly channel region

FIG. 3 is a schematic view showing a state where conductance is made uniform as a result of performing single ion implantation into a channel region of the MOSFET shown in FIG. 2 in the semiconductor device in which fluctuation is suppressed according to the present invention;

FIG. 4 is a schematic configuration diagram of a single ion implantation apparatus based on a beam chop method for manufacturing a semiconductor device in which fluctuation is suppressed according to the present invention.

FIG. 5 is a schematic configuration diagram of a single ion implantation apparatus based on an electric field control method for manufacturing a semiconductor device in which fluctuation is suppressed according to the present invention.

FIG. 6 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a first embodiment of the present invention, and shows an n-type SOI structure.
Bird's-eye view corresponding to MOSFET

FIG. 7 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a first embodiment of the present invention, and shows an n-type SOI structure.
Sectional structure diagram corresponding to MOSFET

FIG. 8 is a diagram illustrating a fluctuation-suppressed semiconductor device according to a first embodiment of the present invention;
m) ^-2 ] source-drain current I _D
Diagram showing the relationship between [μA] and the substrate bias voltage V _BG [V]

FIG. 9 is a diagram showing the relationship between the flat band voltage V _FB [V] obtained from the _ID- V _BG characteristics and the number of implanted ions (pieces) [(0.5 μm) ⁻² ].

FIG. 10 is a diagram showing a semiconductor device in which fluctuation is suppressed as a first embodiment of the present invention; conductance g [μS] obtained by a four-point probe method and the number of implanted ions (pieces) [(0.5 μm);
m) ^-2 ]

FIG. 11 is a diagram illustrating a simulation result of a potential distribution in a depth x direction of a channel region in a semiconductor device in which fluctuation is suppressed as the first embodiment of the present invention;

FIG. 12 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a third embodiment of the present invention, which is a bulk CMO.
Example of manufacturing a semiconductor device in which fluctuation is suppressed from the beginning when forming S (before single ion implantation)

FIG. 13 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a third embodiment of the present invention, and is a bulk CMO.
Example of manufacturing a semiconductor device in which fluctuation is suppressed from the beginning when forming S (single ion implantation step)

FIG. 14 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a fourth embodiment of the present invention, which is an SOI-CM
Example of manufacturing a semiconductor device in which fluctuation is suppressed from the beginning when forming an OS (before single ion implantation)

FIG. 15 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a fourth embodiment of the present invention, which is an SOI-CM.
Example of manufacturing a semiconductor device in which fluctuation is suppressed from the beginning when forming an OS (single ion implantation step)

FIG. 16 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a fifth embodiment of the present invention, which is a bulk CMO.
Example in which single ion implantation is used to correct a semiconductor device having fluctuations in the process of forming S (before single ion implantation)

FIG. 17 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a fifth embodiment of the present invention, which is a bulk CMO.
Example in which single ion implantation is used to correct a semiconductor device having fluctuations in the process of forming S (single ion implantation step)

FIG. 18 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a sixth embodiment of the present invention;
Example in which single ion implantation is used to correct a semiconductor device having fluctuations in the process of forming an OS (before single ion implantation)

FIG. 19 is a schematic configuration diagram of a semiconductor device in which fluctuation is suppressed as a sixth embodiment of the present invention, which is an SOI-CM
Example in which single ion implantation is used to correct a semiconductor device having fluctuations in the process of forming an OS (single ion implantation step)

[Description of sign]

DESCRIPTION OF SYMBOLS 1 Silicon wafer 2 Silicon chip 3 MOSFET integrated circuit 4,4-1,4-2,4-3 Channel region 5 Arrow (miniaturization of a semiconductor device) 6 Arrow (increase in fluctuation of the number of impurity atoms) 7 Single ion implanter (Schematic display) 8 Single ion (○: white circle) 9 Arrow (correction of impurity atom number by single ion implantation method) 10 Ohmic contact 11, 36, 37 Impurity atom (●: black circle) 12 Upper silicon layer 13 Embedded SiO ₂ 14, 20 silicon substrate 15 single ion implantation region 16 SIMOX substrate 17 upper SiO ₂ 21 p well region 22 n well region 23-1, 23-2 region where channel is formed 24 device isolation region by LOCOS 25, 26, 38, 39 Single ion-implanted ions (O: white circle) 27 and 29 of the source electrode 28 drain electrode 30, 31 nMOS source / drain regions 32, 33 pMOS source / drain region

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 7, 1999 (July 7, 1999)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memory) constituting a semiconductor large-scale integrated circuit.
y), SRAM (Static Random Access Memory), EE
PROM (ElectricalErasable Programmable Read Onl)
y Memory), Flash memory, CMOS (Complementary M
etal Oxide Semiconductor), Bi-CMOS (Bipolar
CMOS), FRAM (Ferroelectric Random Access)
Memory), a bipolar transistor, or a MESFET, MOSFET,
Partially depleted SOIMOSFET, fully depleted SOIMO
SFET, a device for a pixel constituting an image sensor such as a CCD or a CID, a two-dimensional electron gas device, a single electron transistor, a quantum wire, a quantum box, a quantum dot device, a laser diode (LD), A light emitting device such as an LED, or a light receiving device, or a light emitting-receiving device, or a compound semiconductor device such as a heterojunction bipolar transistor;
Or, in the field of superconducting elements such as Josephson elements, etc., or all kinds of semiconductors, resistors, inductors, capacitors, diodes, three-terminal devices, four-terminal devices, etc. using superconductors. A semiconductor device in which fluctuation of the number of impurity atoms contained in a semiconductor is suppressed by implanting generated single ions one by one into the semiconductor,
All semiconductor devices that are expected to improve performance by suppressing fluctuations in the number of impurity atoms contained in the semiconductor are included.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction contents]

[0042]

[Table 1]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

The location of single ion implantation can be determined, for example, in a channel region, a source region, a drain region, a polysilicon gate region, and the like. In order to suppress fluctuations in device characteristics such as a threshold value by controlling impurity atoms in a semiconductor device channel, it is effective to perform a single ion implantation method as a channel doping technique. For this purpose, single ion implantation into the channel region is particularly important. DR
AM, SRAM, EEPROM, Flash memory, CMO
Single transistor for controlling S, Bi-CMOS, FRAM, MESFET (n-type, p-type), MOST (n
Type, p-type), partially depleted SOI-MOST (n-type, p-type)
Of course, single ions can be implanted into each channel region of a fully depleted SOI-MOST (n-type, p-type) and compound semiconductor device. Since the doping of the source region, the drain region, and the polysilicon is originally a relatively high dose, it may not be possible to expect a remarkable effect by controlling the impurities one by one.
However, the present invention can be implemented in resistance value trimming control or the like. This is because variation in conductance can be controlled as shown in FIG. Therefore, the data of the decrease of the flat band voltage V _FB per ion -4.5 mV / ion [0.5 μm) ^-2 ] and the increase of the conductance g of 17.9 nS / ion [0.5 μm) ^-2 ] Utilizes very sensitive linear and linear I
It is also possible to implement a C operational amplifier or a highly sensitive sensor array.

Claims (9)

[Claims] 1. A semiconductor device in which fluctuation of the number of impurity atoms contained in a semiconductor is suppressed by implanting a single ion into a semiconductor by a single ion generated by a single ion implantation apparatus. . 2. The method according to claim 1, wherein a single ion generated by the single ion implanter is implanted into the channel region of the MOSFET by single ion implantation, thereby suppressing the fluctuation of the number of impurity atoms contained in the channel region. Semiconductor device. 3. The method according to claim 1, wherein a single ion generated by the single ion implanter is implanted into the n-channel region and the p-channel region of the CMOSFET, respectively, to thereby reduce the number of impurity atoms contained in the n-channel region and the p-channel region. A semiconductor device in which fluctuation is suppressed, characterized in that fluctuation of fluctuation is suppressed. 4. The method according to claim 1, wherein a single ion generated by the single ion implanter is implanted into the semiconductor by single ion implantation, thereby suppressing fluctuation of the number of impurity atoms contained in the semiconductor and correcting the number of impurity atoms in the semiconductor. A semiconductor device in which conductance, inductance, or capacitance is made uniform, wherein fluctuation is suppressed. 5. A semiconductor device in which a single ion generated by a single ion implanter is implanted into a channel region of a MOSFET by single ion implantation to suppress fluctuations in the number of impurity atoms contained in the channel region. A semiconductor device in which fluctuation is suppressed, wherein the step of performing ion implantation is performed through the gate oxide film after the formation of the gate oxide film, and threshold value channel doping is performed by the single ion implantation. 6. A semiconductor device in which fluctuations in the number of impurity atoms contained in the channel region are suppressed by implanting single ions generated by a single ion implantation device into a channel region of a MOSFET. The step of implanting ions is performed after the element isolation step and before the formation of the gate oxide film, and the threshold setting channel doping is performed by the single ion implantation,
Semiconductor device with reduced fluctuation. 7. The method according to claim 7, wherein a single ion generated by the single ion implanter is implanted into the n-channel region and the p-channel region of the CMOSFET, respectively, to thereby reduce the number of impurity atoms contained in the n-channel region and the p-channel region. In the semiconductor device in which the fluctuation is suppressed, the step of implanting a single ion into each of the n-channel region and the p-channel region is performed after the element isolation step and before the formation of the gate oxide film. A fluctuation-suppressed semiconductor device, characterized in that threshold setting n-channel doping and p-channel doping are respectively performed. 8. A semiconductor device in which fluctuations in the number of impurity atoms contained in the channel region are suppressed by implanting single ions generated by a single ion implantation device into a channel region of a MOSFET. The ion implantation step is characterized in that the electrical characteristics are evaluated after the formation of the gate, source, and drain electrodes, the location and amount of the fluctuation are specified, and then the ion implantation is performed through the gate electrode under high energy conditions. Semiconductor device. 9. The method according to claim 1, wherein a single ion generated by the single ion implanter is implanted into the n-channel region and the p-channel region of the CMOSFET, respectively, to thereby reduce the number of impurity atoms contained in the n-channel region and the p-channel region, respectively. In the semiconductor device in which the fluctuation is suppressed, the step of implanting a single ion into each of the n-channel region and the p-channel region includes evaluating the electrical characteristics after forming the gate, source, and drain electrodes of the CMOSFET to determine the location and amount of the fluctuation. A semiconductor device in which fluctuation is suppressed, which is performed through the gate electrode under a high energy condition after the identification.