JP2001023390A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an access time by shortening a transmission delay time of a read-out path of a static RAM and the like adopting a shift relieving system. SOLUTION: An output latch of a unit output circuit UOC0 of a data input/ output circuit IO0 is constituted of a pair of CMOS inverters V8 and V9. An output redundant switch ORS0 of a redundant switch RS0 is basically configured of a NAND gate NA1 receiving an output signal OL and the non-inversion signal of a redundant switch control signal RCO0 corresponding to the OL, a NAND gate NA2 receiving the OL and the inversion signals of the RCO0, a gate G1 receiving an output signal of the NAND gate NA1 at the time of non-relieving and transmitting an output signal of a unit sense amplifier USA0 corresponding to a unit output circuit UOC0, and a gate G2 receiving an output signal of NA2 at the time of relieving, and transmitting an output signal of a unit sense amplifier USA1 of a post stage or a redundant unit sense amplifier USAR to a unit output circuit UOC0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, an on-chip type static RAM (random access memory) which is mounted as a cache memory in a logic integrated circuit device such as a single chip microcomputer and employs a shift relief system. ) And a technique that is particularly effective for use in shortening the access time.

[0002]

2. Description of the Related Art There is a static RAM in which a memory array having CMOS (complementary MOS) cells arranged in a lattice is a basic component. In addition, there is a logic integrated circuit device such as a single-chip microcomputer in which such a static RAM is mounted as a macro cell and used for a cache memory or the like.

On the other hand, for example, one redundant element is provided in correspondence with a predetermined number of normal elements arranged in order with each other, this redundant element is positioned after the normal element, and any abnormality is detected in any one of the normal elements. In the case where the normal element and the redundant element in the subsequent stage are disabled, the normal element and the redundant element in the subsequent stage are shifted one by one and connected to the next-stage circuit, thereby relieving the disabled normal element by the redundant element.

[0004]

Prior to the present invention, the present inventors have developed an on-chip static RAM mounted as a macro cell in a logic integrated circuit device such as a single-chip microcomputer and employing a shift relief system. Engaged in the development and noticed the following issues: That is, the static RAM includes a plurality of memory mats, and each of the memory mats includes a memory array including, for example, 76 sets of complementary bit lines including non-inverted and inverted bit lines. Complementary bit lines forming the memory array of each memory mat are divided into 19 bit line groups in units of four sets, and the four sets of complementary bit lines forming each bit line group are divided into corresponding unit columns of a column switch. Each is alternatively connected to an input terminal of a corresponding unit sense amplifier of the sense amplifier via a switch.

Output signals SO0 to SOH and SOR of 19 unit sense amplifiers including a redundant sense amplifier
(In this specification, for example, an additional number exceeding 10, such as an output signal of 18 unit sense amplifiers, which are normal elements of a sense amplifier, may be represented by an alphabet. For example, a redundant unit sense amplifier of a sense amplifier may be used. The name of the output signal or the like is suffixed with the letter R. The same applies hereinafter), as represented by the output signal SO1 in FIG. 7, for example, the first of the output redundancy switch ORS1 corresponding to the redundancy switch RS0. To the input terminal of
It is supplied to the second input terminal of the output redundancy switch ORS0 at the preceding stage. Also, output redundancy switches ORS0 to ORS
Output terminals such as S1 are coupled to corresponding input terminals of unit output circuits UOC0 to UOC1 of data input / output circuit IO0, and output terminals of these unit output circuits are coupled to corresponding output data buses DOB0 to DOB1 and the like. Is done.

The output redundant switch O of the redundant switch RS0
As represented by the output redundancy switch ORS0, RS0 to ORS1 and the like are transfer gates provided between a first input terminal thereof, ie, a sense amplifier output signal line SO0, and an output terminal thereof, ie, an input terminal of a unit output circuit UOC0. G7, its second input terminal, ie, sense amplifier output signal line SO1, and its output terminal, ie, unit output circuit UO
And a transfer gate G8 provided between the input terminal C0 and the input terminal of C0. The unit output circuits UOC0 to UOC1 of the data input / output circuit IO0 are the unit output circuits UOC0 to UOC0.
, One input terminal of which is cross-coupled to each other to form a NAND gate N
A3 and NA4, and an inverter V18 receiving the output signal of NAND gate NA4 and having its output terminal coupled to output data bus DOB0.

The corresponding redundant switch control signal RC00 is supplied to the gates of the N-channel MOSFET of the transfer gate G7 of the output redundant switch ORS0 and the P-channel MOSFET of the transfer gate G8, and the P-channel MOSFET of the transfer gate G7 is supplied.
N-channel MOSF of T and transfer gate G8
An inverted signal from the inverter V15 is supplied to the gate of the ET. The inverted output control signal OLB is connected to the other input terminal of the NAND gate NA3 constituting the unit output circuit UOC0 via inverters V16 and V17.
(Here, a so-called inverted signal or the like which is selectively set to a low level when it is made valid is represented by adding a B to the end of its name. The same applies hereinafter), and the other input of the NAND gate NA4 is supplied. Terminal is unit output circuit UOC0
To the input terminal.

As a result, the transfer gate G7 of the output redundant switch ORS0 is selectively turned on when the corresponding redundant switch control signal RC00 is set to the valid level, that is, the high level, and the transfer gate G7 of the corresponding unit sense amplifier of the sense amplifier is turned on. Output signal SO0 is transmitted to corresponding unit output circuit UOC0 of data input / output circuit IO0. The transfer gate G8 is selectively turned on when the corresponding redundant switch control signal RC00 is set to the invalid level, that is, low level, and outputs the output signal SO1 of the unit sense amplifier at the next stage of the sense amplifier to the data input / output circuit IO0. To the corresponding unit output circuit UOC0.
Further, the output latch composed of the NAND gates NA3 and NA4 of the unit output circuit UOC0 outputs the inverted output control signal OL.
In response to the valid level of B, that is, the low level, the output signal SO0 or SO1 of the first or second unit sense amplifier transmitted through the output redundancy switch ORS0 is taken in and held, and the corresponding output data bus DOB
Output to 0.

As a result of the above, for example, if any abnormality is detected in the first unit sense amplifier or the corresponding complementary bit line of the memory array and becomes unusable, the output signals SO1 to SO1 of the second and subsequent unit sense amplifiers become unavailable. SOH and SOR are sequentially shifted and transmitted to unit output circuits UOC0 to UOCH. Therefore, the unusable regular element including the first-stage unit sense amplifier is substantially replaced with a redundant element including a redundant unit sense amplifier, thereby producing a static RAM and a product of a logic integrated circuit device equipped with the static RAM. The yield will be improved.

However, unit output circuits UOC0 to UOC
The output latches composed of NAND gates NA3 and NA4 such as 1 have a relatively low state transition speed because they are cross-coupled to each other through another input terminal to which the input signal or the inverted output control signal OLB is not directly supplied. Combined with the fact that G7 and G8 are provided in series, the transmission delay time of the read path including the output redundant switch and the unit output circuit becomes relatively long. As a result, the access time of the static RAM is restricted, and the logic cycle of the logic integrated circuit device equipped with the static RAM and the machine cycle of a computer system or the like including the static RAM are also restricted.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce a transmission delay time of a read path including an output redundant switch and a unit output circuit such as a static RAM using a shift relief system.
Faster access time for static RAM, etc.
It is an object of the present invention to speed up a machine cycle of a logic integrated circuit device or the like in which this is mounted as a macro cell.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a static RAM or the like which is mounted as a macro cell in a logic integrated circuit device or the like and employs a shift relief method, an output latch of each unit output circuit of the data input / output circuit is constituted by a pair of inverters directly cross-coupled to each other. A first NAND gate receiving an output control signal at one input terminal thereof and receiving a non-inverted signal of a redundant switch control signal corresponding to the other input terminal thereof; A second NAND gate receiving an output control signal at its terminal and receiving an inverted signal of a redundant switch control signal corresponding to the other input terminal; and selectively receiving a valid level of the output signal of the first NAND gate during non-repair to selectively turn on State, and outputs the first signal for transmitting the output signal of the corresponding unit sense amplifier to the corresponding unit output circuit. A second gate for transmitting the output signal of the subsequent unit sense amplifier or the redundant unit sense amplifier to the corresponding unit output circuit in response to the effective level of the output signal of the second NAND gate at the time of repair; And a transfer gate.

According to the above-mentioned means, the output latch of each unit output circuit of the data input / output circuit is constituted by a pair of inverters directly cross-coupled to each other, so that the state transition can be speeded up. Gate control based on the output control signal and the redundant switch control signal can be integrated into the first and second NAND gates, and the gate control operation can be speeded up. As a result, the transmission delay time of the read path including the output redundant switch and the unit output circuit is shortened, and the static RAM that adopts the shift relief method is provided.
And the like, and the machine cycle of a logic integrated circuit device or the like in which this is mounted as a macro cell can be shortened.

[0015]

FIG. 1 is a block diagram showing one embodiment of a static RAM (semiconductor memory device) to which the present invention is applied. FIG. 2 is a block diagram of one embodiment of a memory array and peripheral portions included in the static RAM of FIG. 1, and FIG. 3 is a block diagram of one embodiment of the memory mat MAT0. Have been. First, an outline of the configuration and operation of the static RAM of this embodiment and the memory mats MAT0 to MATp will be described with reference to these drawings.

The static RAM of this embodiment
Although it is not particularly limited, it is mounted as a macro cell in a logic integrated circuit device serving as a single-chip microcomputer and functions as, for example, a cache memory. The circuit elements constituting each block in FIGS. 1 and 2 are as follows:
Along with circuit elements constituting other blocks (not shown) of the logic integrated circuit device, a well-known MOSFET (metal oxide semiconductor type field effect transistor; in this specification, MO
It is formed on a single semiconductor substrate surface such as single crystal silicon by an integrated circuit manufacturing technique (SFET is a generic name of insulated gate field effect transistors). Further, in FIG. 3, a specific description will be given by taking the memory mat MAT0 as an example. However, since the other memory mats MAT1 to MATp have the same configuration as the memory mat MAT0, it should be analogized.

Referring to FIG. 1, the static type RAM of this embodiment is not particularly limited, but has a memory array MARY arranged to occupy most of the required layout area.
And a write amplifier WA, a column switch CS, a sense amplifier SA, a redundant switch RS, and a data input / output circuit IO serving as peripheral circuits. The static type RAM includes an X address decoder XD, a Y address decoder YD, an X-system redundant circuit RX, and a Y-system redundant circuit Y.
R, an X address buffer XB, a Y address buffer YB, and a timing generator TG.

In this embodiment, the static RA
M memory array MARY, write amplifier WA, column switch CS, sense amplifier SA, redundant switch RS
In addition, as shown in FIG. 2, the peripheral portion including the data input / output circuit IO is actually divided into p + 1 pieces to form the memory mats MAT0 to MATp. Therefore, each of the memory mats MAT0 to MATp includes a memory array MARY0 to MARYp obtained by dividing the memory array MARY in the word line extending direction, and a write amplifier W.
A, column switches CS, sense amplifiers SA, redundant switches RS, and write amplifiers WA0 to WAp each having a divided data input / output circuit IO, column switches CS0 to CSp, sense amplifiers SA0 to SAp, redundant switches RS0 to RSp, and data. Input / output circuit IO
0 to IOp.

Here, memory mats MAT0-MATp
Are represented by m + 1 word lines W0 to Wm arranged in parallel in the horizontal direction in the drawing, as represented by the memory array MARY0 of the memory mat MAT0 in FIG. 4 × 19 pairs, that is, a total of 76 pairs of complementary bit lines B00 to B03 to BH0 to BH3 and BR0 to BR3 arranged in parallel to the vertical direction in the figure. At the intersection of these word lines and complementary bit lines, a latch circuit composed of a pair of CMOS inverters cross-coupled has a basic element of 76 × (m
+1) static memory cells MC are arranged in a lattice shape.

Complementary bit lines B00 to B03 to BH0 to BH3 and B constituting memory array MARY0
R0 to BR3 are divided into 19 bit line groups in units of four sets. Of these, the complementary bit lines B00 to B03 to BH0 to BH3 forming the first to eighteenth bit line groups are so-called normal elements. Further, the complementary bit lines BR0 to BR3 forming the nineteenth bit line group are so-called redundant elements, and are provided for bit line defect repair in units of four sets. Memory array MA
RY0 further includes a predetermined number of redundant word lines (not shown), but the X-system redundant circuit R
Specific illustration and description of the related circuits including X are omitted.

Memory array MA of memory mat MAT0
The word lines W0 to Wm constituting RY0 are extended rightward to pierce the other memory arrays MARY1 to MARYp, and are coupled to the X address decoder XD on the left side, and are selectively set to the selection level. You. The X address decoder XD has i
A 1-bit internal X address signal X0 to Xi is supplied, and a redundant word line selection signal of a predetermined bit is supplied from the X-related redundant circuit RX. Also, the X-system redundant circuit RX
Are supplied with internal X address signals X0 to Xi from an X address buffer XB. The X address buffer XB is supplied with i + 1-bit X address signals AX0 to AXi via address input terminals AX0 to AXi, and is also supplied with an internal control signal AL from the timing generation circuit TG.

The X address buffer XB is connected to the address input terminals AX0 to AX0 from the access unit of the logic integrated circuit device.
X address signals AX0-AX supplied via AXi
i is fetched and held in accordance with the internal control signal AL, and based on these X address signals, internal X address signals X0 to Xi composed of a non-inverted signal and an inverted signal, respectively, are formed to form an X address decoder XD and an X-system redundant signal. Circuit R
Supply X. The X-related redundant circuit RX holds a defective address assigned to each redundant word line of the corresponding memory array MARY, and also stores the defective address and an internal X address signal X0 supplied at the time of access.
Xi is compared and compared bit by bit. As a result, when all bits match in both addresses, the corresponding bit of the redundant word line selection signal for X address decoder XD is selectively set to the effective level.

The X address decoder XD has internal X address signals X0 to X supplied from an X address buffer XB.
In addition to decoding i, the word line or the redundant word line of the memory array MARY0 is selectively set to a selection level based on the decoding result and the redundant word line selection signal supplied from the X-system redundant circuit RX.

Next, as shown in FIG. 3, the complementary bit lines B00 to B03 to BH0 to BH3 and BR0 to BR3 forming the memory array MARY0 of the memory mat MAT0 have write amplifiers WA thereunder as illustrated in FIG.
0, which are coupled to the output terminals of the corresponding unit write amplifiers UWA, and selectively set by the corresponding unit column switches UCS0 to UCSH and UCSR of the column switch CS0, that is, the set of 19 pairs in total, that is, the corresponding set of the sense amplifiers SA0. Unit sense amplifiers USA0 to USA
H and USAR.

Here, the write amplifier WA0 is connected to the complementary bit lines B00 to B03 to B03 of the memory array MARY0.
It includes 76 unit write amplifiers UWA provided corresponding to H0 to BH3 and BR0 to BR3. Further, the column switch CS0 has a + b, ie, 1 column switches provided corresponding to each bit line group of the memory array MARY0.
The sense amplifier SA0 includes nine unit column switches UCS0 to UCSH and UCSR, and the sense amplifier SA0 includes a bit line group of the memory array MARY0, that is, a unit provided corresponding to the unit column switches UCS0 to UCSH and UCSR of the column switch CS0. It includes 18 unit sense amplifiers USA0 to USAH and b, that is, one redundant unit sense amplifier USAR.

Needless to say, the unit column switches UCS0 to UCSH of the column switch CS0 and the unit sense amplifiers USA0 to USAH of the sense amplifier SA0.
Corresponds to a normal element, and the unit column switch UCSR of the column switch CS0 and the unit sense amplifier USAR of the sense amplifier SA0 correspond to a redundant element. Also, the unit sense amplifiers USA0 to USA of the sense amplifier SA0
H are ordered in that order, and the unit sense amplifier U
The SAR is positioned at the last stage.

On the other hand, the redundant switches RS0 of the memory mat MAT0 have 18 output redundant switches ORS0 to ORSH provided corresponding to the regular elements of the sense amplifier SA0, ie, the unit sense amplifiers USA0 to USAH.
And input redundancy switches IRS0 to IRSH,
The data input / output circuit IO0 includes 18 unit output circuits UOC0 to UOCH and a unit input circuit U provided corresponding to these output redundant switches and input redundant switches.
IC0 to UICH.

Unit input circuit U of data input / output circuit IO0
Input terminals of IC0 to UICH are coupled to corresponding input data buses DIB0 to DIBH, and their output terminals are connected to corresponding input redundant switch IRS0 of redundant switch RS0.
ＩＲIRSH. The input terminals of these input redundant switches IRS0 to IRSH are connected to the unit column switches UCS0 to UC of the column switch CS0.
It is selectively connected to the input terminals of the 18 unit write amplifiers UWA of the write amplifier WA0 via SH and UCSR, and each unit write amplifier U of the write amplifier WA0.
The output terminals of WA are coupled to corresponding complementary bit lines of memory array MARY0.

On the other hand, the input terminals of the unit sense amplifiers USA0 to USAH and USAR of the sense amplifier SA0 are connected to the unit column switch UCS of the column switch CS0.
0 to UCSR and selectively connected to 19 sets of complementary bit lines of the memory array MARY0. Further, its output terminal is coupled to the first input terminal of the corresponding output redundancy switch ORS0-ORSH of the redundancy switch RS0, and is coupled to the second input terminal of the output redundancy switch ORS0-ORSH of the preceding stage. Output redundancy switch ORS
Output terminals 0 to ORSH are coupled to input terminals of corresponding unit output circuits UOC0 to UOCH of data input / output circuit IO0, and output terminals of each unit output circuit are coupled to corresponding output data buses DOB0 to DOBH. .

Write amplifier WA of memory mat MAT0
0, a corresponding internal control signal WE from a write amplifier control circuit (not shown).
00 to WE03 to WEH0 to WEH3 and WE
R0 to WER3 are supplied. Also, unit column switches UCS0 to UCSH of the column switch CS0
And UCSR has 4 bits from Y address decoder YD.
Bit line selection signals YS0 to YS3 of bits are commonly supplied. Further, corresponding redundant switch control signals RC00 to RC0H are supplied from Y-related redundant circuit YR to output redundant switches ORS0 to ORSH of redundant switch RS0, and output control signal OL is commonly supplied from timing generating circuit TG. , Input redundant switches IRS0 to IRS0
IRSH includes a corresponding redundant switch control signal RC00.
ＲＣRC0H are supplied. The input control signal IL is commonly supplied from the timing generation circuit TG to the unit input circuits UICO to UICH of the data input / output circuit IO0.

On the other hand, the Y address buffer YB is supplied with the j + 1-bit internal Y address signals Y0 to Yj from the Y address buffer YB, and the Y system redundancy circuit Y
A predetermined bit redundant bit line selection signal is supplied from R. The Y-system redundancy circuit YR is supplied with the internal Y address signals Y0 to Yj from the Y address buffer YB. Further, the Y address buffer YB is supplied with j + 1-bit Y address signals AY0 to AYj via address input terminals AY0 to AYj, and an internal control signal AL from the timing generation circuit TG.

The Y address buffer YB is connected to address input terminals AY0 to AY0 from the access unit of the logic integrated circuit device.
Y address signals AY0 to AY supplied via AYj
j is captured and held in accordance with the internal control signal AL, and based on these Y address signals, internal Y address signals Y0 to Yj each composed of a non-inverted signal and an inverted signal are formed. YR
To supply.

The Y-system redundant circuit YR holds a defective address assigned to each redundant bit line of the corresponding memory array MARY, and converts the defective address and an internal Y address signal Y0 to Yj supplied at the time of access into a bit. Compare and match each time. As a result, when all the bits coincide with each other, the redundant bit line selection signal for the Y address decoder YD and the redundant switch control signal RC
00 to RC0H to RCp0 to RCpH are selectively set to a high level or a low level.

In this embodiment, the memory array MAR
As described above, the defect relief of the bit lines in Y0 to MARYp is performed in units of four sets of complementary bit lines, that is, bit line groups. Also, the redundant switch control signal R
Although C00 to RC0H to RCp0 to RCpH are not particularly limited, corresponding memory arrays MARY0 to MARY
When bit line defect relief is not performed in RYp,
When all the bits are set to the high level and the corresponding memory array performs the bit line defect repair, the bit corresponding to the defective bit line, that is, the bit line group including the defective bit, and all the bits thereafter are set to the low level. Is done.

The Y address decoder YD decodes the internal Y address signals Y0 to Yj and, based on the decoding result and the redundant bit line selection signal supplied from the Y-related redundant circuit YR, switches the column switches CS0 to CSp. Corresponding to the bit line selection signal for the bit line is selectively set to the effective level.

The eighteen unit input circuits of the data input / output circuits IO0 to IOp are connected to the k + via input data buses DIB0 to DIBk from the access unit of the logic integrated circuit device when the static RAM is set to the write mode.
Write data input in 1-bit units is 1
The data is fetched and stored in units of 8 bits. These write data are transmitted from the redundant switches RS0 to RSp to the eighteen unit write amplifiers of the write amplifiers WA0 to WAp via the column switches CS0 to CSp, then converted into predetermined complementary write signals, and converted into the memory array MARY0. ~ M
Data is written into the selected 18 memory cells of ARYp, for a total of k + 1 memory cells.

On the other hand, 19 of the sense amplifiers SA0 to SAp
Memory sense units MARY0 to MARYM
A read signal output from the selected 19 memory cells of ARYp via the column switches CS0 to CSp is amplified. These read signals are supplied to the redundant switch R
Data input / output circuits IO0-IOp via S0-RSp
After receiving the effective level of the output control signal OL, the output data buses DOB0 to DOB
Output from OBk to the access unit.

In this embodiment, the static type RA
M employs a shift rescue method, and includes data input / output circuits IO0 to IO0.
The 18-bit write data held by the 18 unit input circuits of the IOp is a redundant switch control signal RC00 of each input redundant switch of the redundant switches RS0 to RSp.
In response to the selective shift switching according to RC0H to RCp0 to RCpH, column switches CS0 to CSp
Is transmitted to the 18 unit column switches excluding the redundant unit column switch or the unit column switch to be relieved. The 19-bit read data that is amplified and held by each unit sense amplifier of the sense amplifiers SA0 to SAp is a redundant switch control signal RC00 to RC0H of each output redundant switch of the redundant switches RS0 to RSp.
In response to the selective shift switching according to RCp0 to RCp, 18 bits excluding the bit corresponding to the unit sense amplifier for redundancy or the unit sense amplifier to be relieved are output from each unit output of the data input / output circuits IO0 to IOp. Transmitted to the circuit.

The memory arrays MARY0 to MARYp of the memory mats MAT0 to MATp, the column switches CS0 to CSp, the sense amplifiers SA0 to SAp, the redundant switches RS0 to RSp, and the data input / output circuit IO0
The specific configuration and operation of IOp, its features, and the like will be described later in detail.

The timing generation circuit TG includes a memory enable signal MEN and a read / write signal R supplied as a start control signal from an access unit of the logic integrated circuit device.
Based on / W and the clock signal CLK, the various internal control signals, the output control signal OL, the input control signal IL, and the like are selectively generated and supplied to each unit.

FIG. 3 is a block diagram showing one embodiment of the memory mat MAT0 included in the static RAM of FIG. FIG. 4 is a partial circuit diagram of one embodiment of the redundant switch RS0 and the data input / output circuit IO0 included in the memory mat MAT0 of FIG. FIG. 4 is a conceptual diagram of an embodiment for explaining the flow of write data and read data when the memory mat MAT0 in FIG. 3 is not rescued. FIG. FIG. 2 is a conceptual diagram of one embodiment for explaining the flow of data and read data. Based on these figures, the specific configuration and operation of the memory mats MAT0 to MATp of the static RAM of this embodiment and the respective parts thereof, the flow of read data and write data during non-rescue and rescue, and their characteristics, etc. Will be described in detail.

In FIG. 4, the MOS with an arrow at its channel (back gate) portion is of the P-channel type, and is an N-channel MOSFE without the arrow.
It is shown separately from T. Also, in FIG. 3, the description about the memory mats MAT0 to MAT0 is given.
FIG. 4 illustrates the redundant switch RS0 and the data input / output circuit IO0 with the description of the redundant switch RS0 and the data input / output circuit IO0.
0 to IOp. Further, in FIG. 6, an abnormality is detected in the first bit line group of the memory array MARY0, that is, any one of the complementary bit lines B00 to B03 or its related circuit, that is, the corresponding circuit of the column switch CS0 or the sense amplifier SA0, and The flow of read data and write data will be described with an example of the case where the data cannot be read. The memory array MARY0 includes a predetermined number of redundant word lines, which has been omitted.

In FIG. 3, the memory array MARY0 of the memory mat MAT0 has (m + 1) word lines W0 to Wm arranged in parallel in the horizontal direction in the figure, and a total of 4 word lines arranged in parallel in the vertical direction in the figure. × 19 sets, that is, 76 sets of complementary bit lines B00 to B03 to BH0 to BH3 and BR0 to BR3. At the intersection of these word lines and complementary bit lines, a total of 76 × (m + 1) static memory cells MC are arranged in a lattice. As described above, a total of 76 sets of complementary bit lines constituting the memory array MARY0 are divided into 19 bit line groups in units of 4 sets. Among them, 18 bit line groups, that is, complementary bit lines B00-B03 through BH0-B
H3 is a normal element, and the remaining bit line groups, that is, the complementary bit lines BR0 to BR3, are redundant elements used at the time of repair.

Complementary bit lines B00 to B03 to BH0 to BH3 and B constituting memory array MARY0
R0 to BR3 are below the write amplifier WA0.
And the corresponding upper input terminal of the unit column switches UCS0 to UCSH of the column switch CS0 and the UCSR of the column switch CS0. The input terminal of each unit write amplifier UWA of the write amplifier WA0 is connected to the column switch CS.
0 are coupled to the upper output terminals of the corresponding unit column switches UCS0-UCSH and UCSR.

The lower input terminals of the unit column switches UCS0 to UCSH and UCSR of the column switch CS0 are connected to the corresponding input redundant switch I of the redundant switch RS0.
It is coupled to the first output terminals of RS0 to IRSH and to the second output terminals of the input redundancy switches IRS0 to IRSH at the preceding stage. Needless to say, since the input redundant switch is not provided in the preceding stage of the input redundant switch IRS0 of the redundant switch RS0, the column switch C
The lower input terminal of the unit column switch UCS0 of S0 is
The first of the input redundant switches IRS0 of the redundant switch RS0
Is connected only to the output terminal. Also, the redundant switch RS
0 is the unit column switch UC of the column switch CS0
Since there is no input redundant switch corresponding to SR,
The lower input terminal of the unit column switch UCSR of the column switch CS0 is coupled only to the second output terminal of the input redundant switch IRSH.

Input Redundant Switch I of Redundant Switch RS0
The input terminals of RS0 to IRSH are connected to the data input / output circuit IO.
0 corresponding to the output terminals of the corresponding unit input circuits UIC0 to UICH.
H input terminals correspond to the corresponding input data buses DIB0 to DIB0 to D
Bound to IBk.

On the other hand, lower output terminals of the unit column switches UCS0 to UCSH and UCSR of the column switch CS0 are coupled to input terminals of corresponding unit sense amplifiers USA0 to USAH and USAR of the sense amplifier SA0.

Unit sense amplifier U of sense amplifier SA0
Output terminals of SA0 to USAH and USAR are output redundant switches ORS0 to corresponding output switches of redundant switch RS0.
It is coupled to the first input terminal of the ORSH and to the second input terminal of the preceding output redundancy switch ORS0-ORSH. Needless to say, the redundant switch R
Since no output redundancy switch is provided in the stage preceding the output redundancy switch ORS0 of S0, the lower output terminal of the unit column switch UCS0 of the column switch CS0 is coupled only to the first output terminal of the output redundancy switch ORS0 of the redundancy switch RS0. Is done. Further, since the redundant switch RS0 is not provided with an output redundant switch corresponding to the unit column switch UCSR, the lower output terminal of the unit column switch UCSR is coupled only to the second output terminal of the output redundant switch ORSH.

Output redundant switch O of redundant switch RS0
The output terminals of RS0 to ORSH are connected to the data input / output circuit IO.
0 unit input circuits UOC0 to UOCH are coupled to the input terminals of the corresponding unit output circuits UOC0 to UOCH.
H output terminals correspond to the corresponding output data buses DOB0 to DOB.
Bound to OBk.

Each unit write amplifier UWA of the write amplifier WA0 has a corresponding write amplifier control signal WE00-WE03 through WE from a write control circuit (not shown).
H0 to WEH3 and WER0 to WER3 are supplied, respectively. The unit column switches UCS0 to UCSH and UCSR of the column switch CS0
Are commonly supplied with 4-bit bit line selection signals YS0 to YS3 from the Y address decoder YD. On the other hand, the input redundant switches IRS0-IRS of the redundant switch RS0
H and output redundant switches ORS0 to ORSH,
A corresponding redundant switch control signal R from Y-system redundant circuit YR
C00 to RC0H are commonly supplied, and the output control signal OL is commonly supplied from the timing generation circuit TG. The input control signal IL is commonly supplied from the timing generation circuit TG to the unit input circuits UICO to UICH of the data input / output circuit IO0.

Here, the unit input circuits UIC0 to UICH of the data input / output circuit IO0 are identical to the unit input circuits UI0 of FIG.
As represented by C0, an input latch in which a pair of inverters V12 and V13 are cross-coupled, and an input data bus DIB0 corresponding to a lower input / output terminal of the input latch.
Respectively, and an inverter V11 and a transfer gate G6 provided between them. Transfer gate G6
Is supplied with the input control signal IL, and the gate of the P-channel MOSFET is supplied with an inverted signal by the inverter V14.

Thus, when the static RAM is set to the write mode, the input data buses DIB0 to DIB0 to
Write data input via the IBH is transmitted to a corresponding input latch in response to the high level of the input control signal IL, and is held.

On the other hand, the input redundant switches IRS0-IRSH of the redundant switch RS0 are the input redundant switches IRS of FIG.
As represented by RS0, it includes transfer gates G3 and G4 provided between its lower input terminal and the first and second upper output terminals, respectively. As described above, the first upper output terminal of the input redundancy switch IRS0 is coupled to the input terminal of the corresponding unit write amplifier UWA of the write amplifier WA0, that is, the write amplifier input signal line WI0, and the second upper output terminal is , The input terminal of the subsequent unit write amplifier UWA, that is, the write amplifier input signal line WI
1 Further, the N-channel MOSFET of the transfer gate G3 and the P-channel MOSFET of the transfer gate G4
A substantially non-inverted signal of the corresponding redundant switch control signal RC00 is supplied to the gate of the channel MOSFET, and the P-channel MOSFET of the transfer gate G3 is supplied.
T and N-channel MOSF of transfer gate G4
The gate of the ET is supplied with the substantially inverted signal.

For these reasons, in the static RAM in the write mode, the data input / output circuit I
The write data held by the input latch of the corresponding unit input circuit UIC0 of O0 is abnormal when the corresponding redundant switch control signal RC00 is set to the high level, that is, the corresponding bit line group of the memory array MARY0 and its related circuits are abnormal. Is not detected and defect repair is not performed, the input redundant switch IR of the redundant switch RS0
The corresponding unit column switch UCS0 of the column switch CS0 as it is via the transfer gate G3 of S0.
Is transmitted to Also, the corresponding redundant switch control signal R
When C00 is set to the low level, that is, when any abnormality occurs in the corresponding or preceding bit line group of the memory array MARY0 or its related circuit and defect repair is performed, the transfer gate G4 of the input redundant switch IRS0 of the redundant switch RS0. , The unit column switch UCS1 at the subsequent stage of the column switch CS0
Is transmitted to

The shift operation of the write data in the write mode is performed in all the input redundant switches after the target bit of the redundant switch RS0 for repairing the defect, thereby realizing the shift relief using the last-stage redundant element. Is done.

The input redundant switch I of the redundant switch RS0
The 18-bit write data transmitted from RS0 to IRSH to the unit column switches UCS0 to UCSH of the column switch CS0 is one of four corresponding unit write amplifiers UWA of the write amplifier WA0 according to the bit line selection signals YS0 to YS3. Selectively transmitted to Each unit write amplifier UWA of the write amplifier WA0 has a corresponding write amplifier control signal WE00-WE0H and WE0
In response to the high level of R, it is selectively activated, and the corresponding unit column switch UCS of the column switch CS0
After the write data transmitted from 0 to UCSH is converted into a predetermined complementary write signal, the write data is transmitted to the designated memory cell MC via a corresponding pair of bit lines B00 to B03 to BH0 to BH3 and BR0 to BR3 of the memory array MARY0. Write.

As a result, when no abnormality is detected in any of the 19 bit line groups of the memory array MARY0 of the memory mat MAT0 and its associated circuits, and no defect is repaired, the corresponding input data bus DIB0 to DIB0
The 18-bit write data input via the DIBH is, as shown by the thick dashed line in FIG. 5, the corresponding unit input circuits UIC0 to UIC of the data input / output circuit IO0.
H, transmitted to the corresponding unit column switches UIC0 to UICH of the column switch CS0 via the corresponding input redundant switches IRS0 to IRSH of the redundant switch RS0, and then a total of 18 write amplifiers WA0 according to the bit line selection signals YS0 to YS3. Unit light amplifier UWA
And written to the selected memory cell.

However, when an abnormality is detected in, for example, the first bit line group or its associated circuit constituting the memory array MARY0 of the memory mat MAT0, and the defect is remedied, as shown by a thick dashed line in FIG. , Input data buses DIB0 to DIBH to corresponding unit input circuits UIC0 to UIC of data input / output circuit IO0.
After being transmitted to the corresponding input redundant switches IRS0 to IRSH of the redundant switch RS0 via H, it is shifted one by one and the unit column switch UI of the column switch CS0 is shifted.
C1 to UICR, and bit line selection signals YS0 to YS0
18 unit write amplifiers U selected according to YS3
It is transmitted to the WA and written.

Next, when the static RAM is set to the read mode, the corresponding bit lines B00 to B03 to BH0 to BH3 and BR0 to BR0 to B03 to BH0 to BH3 from a total of 76 memory cells MC coupled to the selected word line of the memory array MARY0. A read signal output to BR3 is output from a corresponding unit column switch UCS of column switch CS0.
0 to UCSH and UCSR, which are selectively selected according to bit line selection signals YS0 to YS3, and corresponding unit sense amplifiers USA0 to US0 of sense amplifier SA0.
It is transmitted to AH and amplified. The output signals SO0 to SOH and SOR of these unit sense amplifiers USA0 to USAH are transmitted to the first input terminals of the corresponding output redundant switches ORS0 to ORSH of the redundant switch RS0 and the second input terminals of the preceding output redundant switch. Is done.

Here, the output redundant switches ORS0 to ORSH of the redundant switch RS0 are not particularly limited, but as represented by the output redundant switch ORS0 of FIG. And a transfer gate G1 (first transfer gate) and a transfer gate G2 (second transfer gate) provided between them. The output signals of the corresponding NAND gates NA1 (first NAND gate) and NA2 (second NAND gate) are supplied to the gates of the P-channel MOSFETs constituting the transfer gates G1 and G2, respectively. The gate of the N-channel MOSFET constituting the transfer gate has its inverter V
2 or V3 are supplied respectively.

An output control signal OL is commonly supplied to one input terminal of the NAND gates NA1 and NA2. A corresponding redundant switch control signal RS00 is supplied to the other input terminal of the NAND gate NA1, and the inverter V1 is connected to the other input terminal of the NAND gate NA2.
Is supplied.

Unit output circuit U of data input / output circuit IO0
OC0 to UOCH include a pair of CMOS inverters V8 and V0 as represented by the unit output circuit UOC0 in FIG.
9 includes an output latch cross-coupled via a transfer gate G5, and an inverter V10 provided between a lower input / output terminal of the output latch and a corresponding output data bus DOB0. An inverted signal of the output control signal OL by the inverter V23 is supplied to the gate of the N-channel MOSFET constituting the transfer gate G5, and the non-inverted signal of the output control signal OL is supplied to the gate of the P-channel MOSFET via the inverters V23 and V24. A signal is provided.

When there is no abnormality in the corresponding bit line group of the memory array MARY0 and its associated circuits and no defect repair is performed, the output redundant switch ORS0 of the redundant switch RS0 receives the high level of the output control signal OL and receives the NAND gate NA1. Is at an effective level, that is, a low level.
1 is in the transmission state. Further, the data input / output circuit IO0
In the corresponding unit output circuit UOC0, the output control signal O
Upon receiving the high level of L, the transfer gate G5 is turned off. Therefore, the read data amplified and held by the corresponding unit sense amplifier USA0 of the sense amplifier SA0 is transmitted to the corresponding unit output circuit UOC0 of the data input / output circuit IO0 via the transfer gate G1 of the output redundancy switch ORS0. , Output control signal O
The low level of L is received and held, and output to the corresponding output data bus DOB0 via the inverter V10 serving as an output buffer.

On the other hand, when an abnormality is detected in the corresponding bit line group of the memory array MARY0 or its associated circuit and defect repair is performed, the output redundant switch ORS0 of the redundant switch RS0 receives the high level of the output control signal OL. The output signal of the NAND gate NA2 is set to an effective level, that is, a low level, and in response, the transfer gate G2 is set to a transmission state. Therefore, the read data amplified and held by the unit sense amplifier USA1 of the second stage is transmitted to the unit output circuit UOC0 of the data input / output circuit IO0 via the transfer gate G2 of the output redundancy switch ORS0 and held. At the same time, the data is output to a corresponding output data bus DOB0 via an inverter V10 serving as an output buffer. At this time, the read data amplified and held by the unit sense amplifier USA0 of the sense amplifier SA0 is regarded as invalid data and is not transmitted to the data input / output circuit IO.

The shift operation of the read data in the read mode is performed by all the input redundant switches after the target bit of the redundant switch RS0 to be repaired, thereby realizing the shift repair using the last-stage redundant element. Is done.

As a result, no abnormality is detected in any of the 19 bit line groups and the related circuits constituting the memory array MARY0 of the memory mat MAT0.
When the defect relief is not performed, the read data of the 76 memory cells MC coupled to the selected word line of the memory array MARY0 is, as shown by the thick dotted line in FIG. UCS
After receiving a quarter selection by 0-UCSH, corresponding unit sense amplifiers USA0-US0 of sense amplifier SA0
Amplified by AH and retained. Then, the corresponding output redundant switch ORS0-ORS of the redundant switch RS0.
The data is directly transmitted to the corresponding unit output circuits UOC0 to UOCH of the data input / output circuit IO via H, and output to the access unit via the corresponding output data buses DOB0 to DOBk.

However, when an abnormality is detected in the first bit line group constituting the memory array MARY0 of the memory mat MAT0 or its related circuit and defect repair is performed, the unit sense amplifier USA of the sense amplifier SA0 is used.
The read data amplified and held by the 1-USAH and the USAR is stored in the output redundant switch OR at the preceding stage of the redundant switch RS0 as shown by the thick dotted line in FIG.
After being transmitted to the unit output circuits UOC0 to UOCH of the data input / output circuit IO0 via S0 to ORSH, they are output via output data buses DOB0 to DOBk.

The static RA of this embodiment is
M, the unit output circuit UOC of the data input / output circuit IO0
Output latches provided at 0 to UOCH are constituted by CMOS inverters V8 and V9 directly cross-coupled via a transfer gate G5, and are provided at output redundant switches ORS0 to ORSH of the redundant switch RS0 to be changeover switches. Transfer gate G
1 and G2 have output control signals OL at their one input terminals.
Are selectively transmitted according to the output signal of the NAND gate NA1 or NA2 which receives the non-inverted signal or inverted signal of the redundant switch control signals RC00 to RC0H corresponding to the other input terminals.

As is well known, an output latch in which a pair of CMOS inverters V8 and V9 are directly cross-coupled
The state transition speed is faster than the output latch in which the other input terminals of the NAND gates NA3 and NA4 are indirectly cross-coupled as shown in FIG. In addition, since the gate control by the output control signal and the redundant switch control signal is integrated into the NAND gates NA1 and NA2, the speed of the gate control operation of the transfer gates G1 and G2 is increased. As a result, the redundant switch RS0
The transmission delay time of the read path including the output redundancy switches ORS0 to ORSH and the unit output circuits UOC0 to UOCH of the data input / output circuit IO0 can be shortened, so that the access time of a static RAM or the like employing the shift relief method can be shortened. This makes it possible to speed up the machine cycle of a logic integrated circuit device in which this is mounted as a macro cell.

The operation and effect obtained from the above embodiment are as follows. (1) In a static RAM or the like which is mounted as a macro cell in a logic integrated circuit device or the like and employs a shift relief method, an output latch of each unit output circuit of a data input / output circuit is connected to a pair of inverters directly cross-coupled to each other. Thus, the effect that the state transition of the output latch can be accelerated can be obtained.

(2) In the above item (1), each output redundant switch of the redundant switch receives an output control signal at one of its input terminals and outputs a non-inverted signal of a redundant switch control signal corresponding to the other input terminal. A first NAND gate for receiving the signal, an output control signal at one of its input terminals, a second NAND gate for receiving an inverted signal of the redundant switch control signal corresponding to the other input terminal, and an output of the first NAND gate during non-repair. A first transfer gate for selectively receiving an effective level of a signal and being turned on to transmit an output signal of a corresponding unit sense amplifier to a corresponding unit output circuit, and an effective level of an output signal of a second NAND gate during repair. In response, the signal is selectively turned on, and the output signal of the subsequent unit sense amplifier or redundant unit sense amplifier is supplied to the corresponding unit output circuit. With the configuration based on the second transfer gate that is reached, the gate control by the output control signal and the redundant switch control signal can be integrated into the first and second NAND gates, and the speed can be increased. Can be

(3) According to the above items (1) and (2),
The effect is obtained that the transmission delay time of the read path of the static RAM or the like including the output redundant switch and the unit output circuit can be shortened correspondingly. (4) According to the above items (1) to (3), an effect is obtained that the access time of a static RAM or the like employing the shift relief method can be shortened. (5) According to the above items (1) to (4), an effect is obtained that a machine cycle of a logic integrated circuit device or the like in which a static RAM or the like is mounted as a macro cell can be speeded up.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the block configuration of the static RAM is not restricted by the present embodiment, and the names and effective levels of the activation control signals and the internal control signals, the combination of the address signals, etc. Can be taken. In FIG. 2, memory mats MAT0-MATp
The number of bit lines of the memory arrays MARY0 to MARYp can be arbitrarily set, and the selection method using the column switch CS0 is the same.

In FIG. 3, the number b of complementary bit lines provided as redundant elements and related circuits can be two or more. In this case, each output redundant switch and input redundant switch of the redundant switch RS0 must also have a connection path between the unit sense amplifier or the unit column switch two stages downstream. On the other hand, the complementary bit lines BR0 to BR3 serving as redundant elements, the unit write amplifier UWA and the unit sense amplifier USAR can be arranged at the forefront stage. In this case, the output redundant switches ORS0 to ORSH of the redundant switch RS0 and the input redundant switch IRS0
The shift rescue direction due to ＩＲIRSH is the opposite direction to that in the present embodiment.

In FIG. 4, output redundant switches ORS0-ORSH of redundant switch RS0 and input redundant switches IRS0-IRSH, unit input circuits UIC0-UICH and unit output circuit U of data input / output circuit IO0.
The specific configuration of OC0 to UOCH, the conductivity type of the MOSFET, and the like can take various embodiments.

In the above description, mainly the case where the invention made by the present inventor is applied to a static RAM mounted as a macro cell in a logic integrated circuit device such as a single-chip microcomputer, which is the application field of the background. However, the present invention is not limited to this. For example, a static RAM that is formed as a single unit as a static RAM employing a shift relief system, other various memory integrated circuit devices, and an ASIC including these devices
(Integrated circuits for specific applications). INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor memory device adopting a shift relief method and an apparatus or system including such a semiconductor memory device.

[0077]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like which is mounted as a macro cell in a logic integrated circuit device or the like and employs a shift relief method, an output latch of each unit output circuit of the data input / output circuit is constituted by a pair of inverters directly cross-coupled to each other. A first NAND gate for receiving each output redundant switch of the redundant switch, receiving an output control signal at one input terminal thereof, and receiving a non-inverted signal of a redundant switch control signal corresponding to the other input terminal;
A second NAND gate receiving an output control signal at one of its input terminals and an inverted signal of a redundant switch control signal corresponding to the other input terminal, and receiving an effective level of an output signal of the first NAND gate during non-repair. A first transfer gate selectively turned on to transmit an output signal of a corresponding unit sense amplifier to a corresponding unit output circuit;
A second transfer gate for selectively receiving an effective level of an output signal of the second NAND gate at the time of repair to be turned on, and transmitting an output signal of a subsequent unit sense amplifier or redundant unit sense amplifier to a corresponding unit output circuit; And the basic configuration.

Thus, the output latch of each unit output circuit of the data input / output circuit is constituted by a pair of inverters directly cross-coupled to each other, so that the state transition can be speeded up, and the output control signal and Gate control based on the redundant switch control signal can be integrated into the first and second NAND gates, and the gate control operation can be speeded up. As a result, the transmission delay time of the read path including the output redundant switch and the unit output circuit is reduced,
The access time of a static RAM or the like employing the shift relief method can be shortened, and the machine cycle of a logic integrated circuit device or the like having the same as a macro cell can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a memory array and a peripheral part included in the static RAM of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a memory mat included in the static RAM of FIG. 1;

FIG. 4 is a partial circuit diagram showing one embodiment of a redundant switch and a data input / output circuit of the memory mat of FIG. 3;

FIG. 5 is a conceptual diagram showing one embodiment for explaining a data flow when the memory mat of FIG. 3 is not repaired.

FIG. 6 is a conceptual diagram showing one embodiment for explaining a data flow at the time of repairing the memory mat of FIG. 3;

FIG. 7 is a partial circuit diagram showing an example of a redundant switch and a data input / output circuit of a memory mat of a static RAM developed by the present inventors prior to the present invention.

[Explanation of symbols]

MARY: memory array, XD: X address decoder, RX: X system redundant circuit, XB: X address buffer, WA: write amplifier, CS: column switch,
YD ... Y address decoder, RY ... Y system redundant circuit,
SA ... sense amplifier, RS ... redundant switch, IO ...
... Data input / output circuit, TG ... Timing generation circuit, M
EN: memory enable signal, R / W: read / write signal, CLK: clock signal, AX0 to AXi ...
X address signals, AY0 to AYj... Y address signals,
DOB0 to DOBk... Output data bus, DIB0 to DIB
IBk: Input data bus. MAT0-MATp: Memory mat, MARY0-MARYp: Memory array, WA0-WAp: Write amplifier, CS0-CSp
... Column switches, SA0 to SAp Sense amplifiers, RS0 to RSp Redundant switches, IO0 to IOp
... Data input / output circuit. W0-Wm ... word line, B0
0 to B03 to BH0 to BH3, BR0 to BR3 ...
Complementary bit line, MC: Static memory cell, U
WA: Unit write amplifier, UCS0 to UCSH, UC
SR: Unit column switch, USA0 to USAH, U
SAR: Unit sense amplifier, ORS0-ORSH ...
Output redundant switch, IRS0 to IRSH... Input redundant switch, UOC0 to UOCH... Unit output circuit, UIC
0 to UICH unit input circuit, WE00 to WE03 to WEH0 to WEH3, WE0 to WER3 ... write amplifier control signal, YS0 to YS3 ... bit line selection signal, SO0 to SOH, SOR ... sense amplifier output signal or its Signal lines, WI0 to WIH, WIR... Write amplifier input signals or their signal lines, RC00 to RC0H to RCp0 to RCpH... Redundant switch control signals, O
L, OLB: output control signal, IL: input control signal.
V1 to V24: CMOS inverter, NA1 to NA4
... NAND gates, G1 to G11 ... transfer gates.

Claims (5)

[Claims] 1. A sense amplifier including a unit sense amplifiers arranged in order with each other, and b redundant unit sense amplifiers positioned downstream of these unit sense amplifiers, and provided corresponding to the unit sense amplifiers. In response to the output control signal and the corresponding redundant switch control signal, the output signal of the corresponding unit sense amplifier is selectively used during non-repair, and the output signal of the subsequent unit sense amplifier or redundant unit sense amplifier is selected during rescue. And a pair of CMOS inverters are directly cross-coupled with a redundant switch including a number of output redundant switches for transmitting
And an output circuit including a unit output circuits each including an output latch for receiving an output signal of the corresponding output redundancy switch. 2. The output redundant switch according to claim 1, wherein each of the output redundant switches receives the output control signal at one input terminal, and receives a non-inverted signal of the redundant switch control signal corresponding to the other input terminal. A first NAND gate; a second NAND gate receiving an output control signal at one input terminal thereof and receiving an inverted signal of the redundant switch control signal corresponding to the other input terminal; A first transfer gate for selectively turning on in response to an effective level of an output signal of the first NAND gate and transmitting an output signal of a corresponding unit sense amplifier to the corresponding unit output circuit; In response to the effective level of the output signal of the second NAND gate, the second NAND gate is selectively turned on, and the unit sense amplifier or the redundant unit The semiconductor memory device, characterized in that the output signal of Nsuanpu to said corresponding unit output circuit is intended to include a second transfer gate for transferring. 3. The semiconductor memory device according to claim 1, further comprising: a memory array including a bit line corresponding to the unit sense amplifier or the redundant unit sense amplifier in units of a predetermined number. A column switch including a + b unit column switches for selectively connecting one of a predetermined number of corresponding bit lines of the memory array and the unit sense amplifier or the redundant unit sense amplifier. A semiconductor memory device, comprising: 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device includes a predetermined number of memory mats each including the memory array, a column switch, a sense amplifier, a redundant switch, and an output circuit. A semiconductor memory device characterized in that: 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a static RAM mounted as a cache memory in a predetermined logic integrated circuit device. Semiconductor storage device.