JP2001015707A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase capacity of a capacitor formed in a trench hole, using conventional etching technology. SOLUTION: At a semiconductor substrate 10, there are formed trench hole 3, a pillar 6 formed at the bottom surface of the trench hole 3, comprises a conductive layer formed at the bottom surface toward an opening end, an insulating film 4 formed on a trench hole sidewall and a pillar surface, and at least a conductive film 9, which is embedded in the trench hole. A capacitor is formed where the semiconductor substrate and pillar are set as first electrode, the insulating film is a ferroelectric, and the conductive film is a second electrode. Since a large sidewall area in the trench hole can be assured using a pillar, a capacitor of large capacity is formed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of forming a capacitor in a trench in a semiconductor substrate and a structure of the capacitor.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device, in forming a capacitor using a deep trench hole used in a DRAM or the like, a hole reduced to the limit of lithography (Lithogrphy) is formed. Capacitors have been formed. FIG. 13 shows a semiconductor substrate on which a conventional capacitor is formed. Although a transistor and the like forming the semiconductor device are formed on the semiconductor substrate, the transistor part is omitted in this figure, and only the capacitor part is shown (FIG. 13B). Semiconductor substrate 100
Is made of, for example, a silicon semiconductor. A first insulating film and a second insulating film are stacked on the main surface of the semiconductor substrate 100. The first insulating film is a silicon nitride film (S
iN) 101, and the second insulating film is a TEOS film 1
02. The TEOS film is an insulating film made of silicon oxide obtained by a chemical vapor deposition method using a gas of tetraethoxysilane. Further, a trench hole 103 is formed in the main surface of the semiconductor substrate 100,
A dielectric film 104 is formed on the side surface. A semiconductor layer 105 such as polysilicon is formed on the TEOS film 102 and inside the trench hole. Here, a capacitor is configured in which the dielectric film 104 is a dielectric and the semiconductor substrate 100 and the semiconductor layer 105 are the first and second electrodes. By combining this capacitor with a MOS transistor formed on a semiconductor substrate, for example, DR
An AM memory element is formed.

Next, a method of forming the capacitor will be described. First, a 5-nm-thick silicon oxide film (SiO ₂ ) (not shown) is formed as a base material of a mask material on a semiconductor substrate 100, and a 220-nm-thick silicon nitride film 101 is formed thereon. 700nm thick TEO
The S film 102 is stacked. Then, these laminates are used as a mask material. TEO for this base material
A photoresist 106 is applied on the S film 102, and a trench hole pattern is formed on the photoresist 106 by well-known lithography (FIG. 12A). Next, the TEOS film 102, the silicon nitride film 101, and the silicon oxide film are etched using the photoresist 106 as an etching mask. Thereafter, the photoresist 106 is peeled off, and this is used as an etching mask for the silicon semiconductor substrate 100 (FIG. 12B). Therefore, RIE (R
In the anisotropic etching such as eactive ion etching, a deep trench hole can be formed by using the TEOS film 102 as a mask and performing etching under an etching condition capable of obtaining a selectivity with respect to TEOS ( FIG. 13A). A silicon nitride or silicon oxide thin film is grown as a dielectric film 104 on the thus formed trench,
A capacitor is formed by depositing a polysilicon film 105 as a conductive material in the substrate 03 (FIG. 13).
(B)).

[0004]

However, when the trench hole formed in the semiconductor substrate is used as a capacitor, the capacitance is determined by the surface area of a portion corresponding to the inner wall surface of the trench. Therefore, in order to secure a large capacitance of the capacitor, it is necessary to increase the depth of the trench hole or increase the width of the trench hole. On the other hand, with the miniaturization of semiconductor elements, there has been a limit in securing a large trench width. For this reason, it has been inevitable to make the trench hole deep in order to secure the capacitance capacity. Further, when the trench hole is to be etched deeply, there is a limit in increasing the thickness of the TEOS film serving as a mask material. Therefore, the TEOS film having a limited thickness is not etched as much as possible. Must be etched deeply, and the etching of the semiconductor substrate must be performed under such etching conditions that the silicon etching rate can be set to be extremely large relative to the TEOS film etching rate. However, it is not easy to find conditions for obtaining a desired etching shape while maintaining a high selection ratio of silicon to the TEOS film, and the etching depth is necessarily limited. The present invention has been made in view of such circumstances, and provides a semiconductor device that increases the capacitance of a capacitor formed in a trench hole using a conventional etching technique, and a method of manufacturing the same.

[0005]

According to the present invention, there is provided a pillar formed of a conductive layer formed on the bottom surface of a trench hole of a semiconductor substrate and formed from the bottom surface toward an opening end, and formed on the side wall of the trench hole and the surface of the pillar. And a conductive film embedded in at least the trench hole, forming a capacitor using the semiconductor substrate and the pillar as a first electrode, the insulating film as a dielectric, and the conductive film as a second electrode. It is characterized by: Since a large side wall area in the trench hole can be secured by using the pillar, it is easy to form a large-capacity capacitor. Further, after forming an insulating film collar along the inner wall of the trench hole, polysilicon is deposited inside the collar, and then the collar is removed by selective etching to form a pillar in the trench hole. And According to this method, the pillars can be formed in a self-aligned manner. Therefore, pillars can be easily formed without performing an extra lithography step.

That is, a semiconductor device according to the present invention comprises a semiconductor substrate on which a semiconductor element and a capacitor are formed, a trench having a predetermined opening diameter formed on a main surface of the semiconductor substrate, and a trench formed on a bottom surface of the trench. A pillar made of a conductive layer formed from the bottom surface toward the opening end; an insulating film formed on the trench hole side wall and the surface of the pillar; and a conductive film embedded at least in the trench hole. The first feature of the capacitor is that the semiconductor substrate and the pillar are a first electrode, the insulating film is a dielectric, and the conductive film is a second electrode. Further, the semiconductor device of the present invention includes a semiconductor substrate on which a semiconductor element and a capacitor are formed, a first trench hole having a predetermined opening diameter formed on the main surface of the semiconductor substrate, and a first trench hole having a predetermined opening diameter. A pillar formed on the bottom surface and formed of a conductive layer formed from the bottom surface toward the opening end; a second trench hole formed from the top surface of the pillar toward the bottom surface; and the first and second trenches An insulating film formed inside the hole and on the surface of the pillar; and a conductive film buried at least in the first and second trench holes, wherein the capacitor connects the semiconductor substrate and the pillar to a first electrode. The second feature is that the insulating film is a dielectric and the conductive film is a second electrode.

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a trench hole having a predetermined opening diameter on a main surface of a semiconductor substrate, a step of forming an insulating film on a side wall of the trench hole, Filling a conductive layer in a trench hole in which an insulating film is formed on the surface and the side wall, and etching away the conductive layer on the main surface of the semiconductor substrate to leave the conductive layer only in the trench hole And etching the insulating film formed on the side wall of the trench hole to form a pillar formed on the bottom surface of the trench hole from the conductive layer formed from the bottom surface toward the opening end. The first feature is that it is provided.
Also, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a first trench hole having a predetermined opening diameter on a main surface of a semiconductor substrate, and a step of forming an insulating film on a side wall of the first trench hole. Filling a conductive layer in a first trench hole in which an insulating film is formed on the main surface of the semiconductor substrate and the side wall, and etching the conductive layer on the main surface of the semiconductor substrate to remove the conductive layer. Leaving only the inside of the first trench hole, and removing the insulating film formed on the side wall of the first trench hole by etching to form a bottom surface of the first trench hole from the bottom toward the opening end. Forming a first pillar made of the formed conductive layer; oxidizing the first pillar and a first trench hole side wall facing the first pillar; Edge the bottom of the trench hole Forming a second trench hole continuous with the first trench hole under the first trench hole, and oxidizing the first trench hole side wall under the first pillar. A second feature of forming a second pillar continuous with the first pillar by performing anisotropic etching using the formed oxide film as a mask. .

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a first trench hole having a predetermined opening diameter on the main surface of the semiconductor substrate, forming an insulating film on the side wall of the first trench hole, insulating the main surface of the semiconductor substrate and the side wall; Filling a conductive layer inside the first trench hole where the film is formed, and etching away the conductive layer on the main surface of the semiconductor substrate to leave the conductive layer only inside the first trench hole; An insulating film formed on the side wall of the first trench hole is removed by etching, and a first layer formed of the conductive layer formed on the bottom surface of the first trench hole from the bottom surface toward the opening end; Forming a pillar, and oxidizing a surface of the first pillar and a sidewall of a first trench hole facing the first pillar;
Etching the bottom surface of the first trench hole to form the first trench hole;
Forming a second trench continuous with the first trench below the trench, and forming a second pillar continuous with the first pillar below the first pillar. And performing anisotropic etching of the first and second pillars using an oxide film formed on the surface of the first pillar by oxidation as a mask.
And a step of forming a second trench hole in the second pillar.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. 1 to 3 are cross-sectional views of a semiconductor substrate illustrating a capacitor forming process. Semiconductor elements such as transistors and circuit elements such as capacitors that constitute a semiconductor device are formed on a semiconductor substrate.
In this figure, the description of the transistor portion is omitted, and the capacitor portion is shown (FIG. 1A). The semiconductor substrate 10 is made of, for example, a silicon semiconductor. On the main surface of the semiconductor substrate 10, a silicon oxide film (SiO ₂ ) as an underlayer is provided.
The first insulating film and the second insulating film are stacked via the gate insulating film 8. The first insulating film is made of a silicon nitride film (SiN) 1, and the second insulating film is made of a TEOS film 2. Further, a trench hole 3 is formed in the main surface of the semiconductor substrate 10. Polysilicon pillars 6 are formed inside the trench holes 3 from the bottom to the opening ends. A dielectric film 4 is formed on the bottom and side surfaces of the trench 3 and on the surface of the pillar 6. A conductive layer 5 such as polysilicon is formed on the TEOS film 2 and inside the trench hole. Here, the dielectric film 4 is a dielectric and the semiconductor substrate 1
A capacitor in which 0 and the pillar 6 are used as a first electrode, and the conductive layer 5 is used as a second electrode. By combining this capacitor with a MOS transistor on a semiconductor substrate, for example,
A DRAM memory element is formed.

Next, a method of forming a capacitor according to this embodiment will be described. First, a 5-nm-thick silicon oxide film (SiO ₂ ) 8 is formed on a semiconductor substrate 10 as a base material of a mask material.
Is formed, and a 200 nm-thick silicon nitride film 1 is formed thereon.
Is formed, and a 700 nm-thick TEOS film 2 is laminated thereon. Then, these laminates are used as a mask material. A photoresist (not shown) is applied to the base material on the TEOS film 2, and a trench pattern is formed on the photoresist by well-known lithography. Next, using this photoresist as an etching mask, the TEOS film 2, the silicon nitride film 1, the silicon oxide film 8
Is etched. After that, the photoresist is stripped, and this is used as an etching mask for the silicon semiconductor substrate 10. Therefore, in the subsequent anisotropic etching such as RIE performed in the etching of the semiconductor substrate, the TEOS film 2 is used as a mask and the etching is performed under the etching conditions that can obtain a selectivity with respect to TEOS. A trench hole 3 is formed (FIG. 1B). For the anisotropic etching for forming the trench holes 3, a magnetron RIE apparatus is used, and HBr, O ₂ , and NF ₃ are used as etching gases at a pressure of 100 m.
Processing is performed in Torr. The trench hole 3 has an elliptical cross section with a minor axis of 0.2 μm and a major axis of 0.34 μm. FIG. 3B is a plan view of the semiconductor substrate. Trench hole 3
Has an elliptical cross-sectional shape, and the cross-sectional shape of the pillar 6 is also elliptical accordingly. The distance between the pillar 6 and the side wall of the trench hole 3 is about 0.07 μm.

A BSG (Boron Silicate Glass) film 7 is deposited to a thickness of about 20 nm in the trench 3 thus formed (FIG. 1C). Thereafter, the BSG film 7 is removed by RIE (R
The whole surface is etched back by anisotropic etching such as eactive ion etching to expose the silicon surface of the semiconductor substrate 10 on the bottom surface of the trench hole 3 and the color of the BSG film 7 on the side wall of the trench hole 3 (hereinafter referred to as a color BSG film).
7 'is formed (FIG. 2A). Next, low pressure CVD
300n film thickness by (Chemical Vapor Deposition) method
m of polysilicon layer 5 is deposited, and trench hole 3 is formed.
Then, the polysilicon layer 5 is etched back to a position lower than the surface of the semiconductor substrate 10 to form pillars 6 (FIG. 2C). The etch-back of the polysilicon layer 5 is performed by using a down-flow type dry etching apparatus, and the surface of the polysilicon layer is controlled to be 50 nm lower than the silicon interface of the semiconductor substrate. Then, the color BSG film 7 '
Is etched with high selectivity for TEOS, silicon nitride, silicon oxide, and silicon. In the etching of the color BSG film, only the BSG can be etched while maintaining a high selectivity with respect to TEOS by using an etching method using a gas phase HF. By this etching, conductive pillars 6 are formed in trench holes 3.
Is formed (FIG. 3A).

Next, a silicon nitride film, which is a capacitor insulating film (dielectric) 4, is formed on the surface of the polysilicon pillar 6 and the side wall of the trench hole 3, and a polysilicon film 9 serving as a counter electrode of the capacitor is formed. Deposit to form a capacitor. This capacitor has a configuration in which the semiconductor substrate 10 and the pillar 6 are used as a first electrode, the polysilicon film 9 as a counter electrode is used as a second electrode, and the capacitor insulating film 4 is used as a dielectric. Further, a conventional trench structure (FIG. 13)
As compared with the case (b)), a surface area approximately 1.7 times as large as that of the case (b) can be obtained, and a capacitance of the formed capacitor can be obtained approximately 1.7 times as large as the surface area.

Next, a second embodiment will be described with reference to FIGS. 4 to 6 are cross-sectional views of the semiconductor substrate illustrating a capacitor forming process. On the semiconductor substrate,
Although a semiconductor element such as a transistor and a circuit element such as a capacitor which constitute a semiconductor device are formed, in this figure, a transistor portion is omitted and a capacitor portion is shown (FIG. 6B). The semiconductor substrate 20 is, for example,
It is composed of a silicon semiconductor. On the main surface of the semiconductor substrate 20, a first insulating film and a second insulating film are stacked via a silicon oxide film (SiO ₂ ) (not shown) as a base layer. The first insulating film is a silicon nitride film (SiN)
The second insulating film is composed of a TEOS film 22. An upper trench hole 23 and a lower trench hole 24 are formed in the main surface of the semiconductor substrate 20. Polysilicon pillars are formed inside the trench holes 23 and 24 from the bottom surface of the trench hole 24 toward the opening end of the trench hole 23. Conductive pillars 26 formed from the semiconductor substrate 20 are arranged in the trench holes 24,
A pillar 26 made of a silicon oxide film is formed in the trench 23.
, An insulating pillar 26 'is disposed. Further, a silicon oxide film 28 is formed on the side wall of the trench hole 23.

A capacitor (not shown) is formed in the trench structure. That is, after removing the insulating pillar 26 ', the bottom and side surfaces of the trench hole 24 and the pillar 2 are removed.
6 Capacitor insulation film of silicon oxide film on the surface (dielectric)
Is formed, and a conductive layer such as polysilicon is formed inside the trench holes 23 and 24 to form a capacitor. Here, the capacitor is configured such that the capacitor insulating film is a dielectric, the semiconductor substrate 20 and the pillar 26 are a first electrode, and the conductive layer is a second electrode. By combining this capacitor with a MOS transistor formed on a semiconductor substrate, for example, a DRAM memory element is formed.

Next, a method of forming a capacitor according to this embodiment will be described. First, a silicon oxide film (SiO ₂ ) having a thickness of 5 nm is formed on the semiconductor substrate 20 as a base material of a mask material.
(Not shown), a 200-nm-thick silicon nitride film 21 is formed thereon, and a 700-nm-thick T
The EOS film 22 is laminated. Then, these laminates are used as a mask material. For this base material, TE
A photoresist (not shown) is applied on the OS film 22,
A trench hole pattern is formed in the photoresist by well-known lithography. Next, using this photoresist as an etching mask, the TEOS film 22 and the silicon nitride film 2 are used.
1. Etching of the silicon oxide film is performed. Thereafter, the photoresist is stripped, and this is used as an etching mask for the silicon semiconductor substrate 20. Therefore, in the subsequent anisotropic etching such as RIE performed in the etching of the semiconductor substrate, the TEOS film 22 is used as a mask and the etching is performed under the etching conditions that can obtain a selectivity with respect to TEOS. A trench hole 23 is formed (FIG. 4A). The anisotropic etching for forming the trench holes 23 is performed using a magnetron RIE apparatus, HBr, O ₂ , and NF ₃ as etching gases at a pressure of 100 mTorr.

The trench hole has a cross section of a minor axis = 0.2 μm.
m, an elliptical shape with a major axis = 0.34 μm. A BSG film 27 is deposited to a thickness of about 20 nm in the trench hole 23 thus formed (FIG. 4B). Thereafter, the entire surface of the BSG film 27 is etched back by anisotropic etching such as RIE to expose the silicon surface of the semiconductor substrate 20 on the bottom surface of the trench hole 23 and to color the BSG film 7 (hereinafter, color BSG) on the side wall of the trench hole 23. A film 7 'is formed (FIG. 4C). Next, a polysilicon layer 25 having a thickness of about 300 nm is deposited by a low-pressure CVD method, and is buried in the trench holes 23 (FIG. 5A). Thereafter, the polysilicon layer is lowered to a position lower than the surface of the semiconductor substrate 20. 25 is etched back to form pillars 25 '(FIG. 5B). For etching back the polysilicon layer 25, a down-flow type dry etching apparatus is used.
The height of the surface of the etched-back polysilicon layer is controlled to be 50 nm lower than the silicon interface of the semiconductor substrate 20. Thereafter, the color BSG film 27 'is etched with high selectivity for TEOS, silicon nitride, silicon oxide, and silicon. In the etching of the color BSG film, only the BSG can be etched while maintaining a high selectivity with respect to TEOS by using an etching method using a gas phase HF.

By this etching, an elliptical conductive pillar 25 'having a height of 1.8 μm and a minor axis of 0.06 μm is formed in the trench hole 23 (FIG. 5C). Next, the entirety of the polysilicon pillar 25 'is oxidized by a thermal oxidation process to form an insulating pillar 26', and a silicon oxide film 28 is formed on the bottom and side walls of the trench hole 23.
Is formed (FIG. 6A). After that, first, etching is performed under the conditions for etching the silicon oxide film (equivalent to etching of SiO ₂ = 40 nm).
S, etching of the trench hole is performed under the condition that the silicon of the semiconductor substrate can be etched with high selectivity to the silicon oxide film. For the etching corresponding to SiO ₂ = 40 nm, etching is performed for 2 minutes at a pressure of 100 mTorr using HBr and NF ₃ gas using a magnetron RIE apparatus. The conditions for etching silicon with high selectivity with respect to the TEOS and silicon oxide films are as follows: a magnetron RIE apparatus is used, and HBr, O
₂ , etching was performed for 6 minutes at a pressure of 100 mTorr using NF ₃ .

As a result, a trench hole 24 having a depth of 8 μm from the silicon interface of the semiconductor substrate (the depth of the portion of the trench hole 24 is 6 μm) is formed, and a pillar 26 is formed in the trench hole 24. You. In the trench holes 23 and 24 thus formed, a film thickness of 8 nm as a capacitor insulating film (dielectric) is formed with respect to the pillar trench.
After the silicon nitride film is formed, the trench holes 23, 2
By embedding the polysilicon film in the capacitor 4, a capacitor having a surface area about 1.5 times as large as that of a conventional trench structure can be obtained.

Next, a third embodiment will be described with reference to FIGS. This embodiment is characterized in that the upper pillar of the second embodiment is entirely oxidized, whereas only the surface is oxidized. 7 and 8 are cross-sectional views of the semiconductor substrate illustrating a capacitor forming process. On the semiconductor substrate, semiconductor elements such as transistors constituting the semiconductor device and circuit elements such as capacitors are formed. In this figure, the transistor part is omitted, and the capacitor part is shown (FIG. 8B )). The semiconductor substrate 30 is made of, for example, a silicon semiconductor.
On the main surface of the semiconductor substrate 30, a first insulating film and a second insulating film are stacked via a silicon oxide film (SiO ₂ ) (not shown) as a base layer. The first insulating film is made of a silicon nitride (SiN) film 31 and the second insulating film is made of T
It is composed of an EOS film 32. In addition, the semiconductor substrate 3
On the 0 main surface, an upper trench hole 33 and a lower trench hole 34 are formed. Polysilicon pillars are formed inside the trench holes 33 and 34 from the bottom surface of the trench hole 34 toward the opening end of the trench hole 33. A conductive pillar 36 formed from the semiconductor substrate 30 is arranged in the trench hole 34, and an insulating pillar 37 made of a silicon oxide film and connected to the pillar 36 is formed in the trench hole 33.
Is arranged. Further, a silicon oxide film 38 is formed on the side wall of the trench hole 33. The pillars 36 and 37 have trench holes 39 formed therein.

A capacitor (not shown) is formed in the trench structure. That is, after the insulating pillar 37 is removed, a capacitor insulating film (dielectric) of a silicon oxide film is formed on the bottom and side surfaces of the trench holes 34 and 39 and on the surface of the pillar 36, and poly is formed inside the trench holes 33 and 34. A capacitor is formed by forming a conductive layer such as silicon.
This capacitor is configured such that the capacitor insulating film is a dielectric, the semiconductor substrate 30 and the pillar 36 are a first electrode, and the conductive layer embedded in the trench holes 33 and 34 is a second electrode. By combining this capacitor with a MOS transistor formed on a semiconductor substrate, for example, a DRAM memory element is formed.

Next, a method of forming a capacitor according to this embodiment will be described. The steps up to the step of forming the pillars 33 shown in FIG. 7A are the same as those in the second embodiment, and the description up to that point (see FIGS. 4 and 5C) is omitted. That is, in the steps up to FIG. 7A, the elliptical pillar 35 having a height of 1.8 μm and a minor axis of 0.15 μm has a depth of 2 μm.
m is formed in the trench hole 33. Trench hole 33
Has an oval cross section with a minor axis of 0.2 μm and a major axis of 0.34 μm. Next, the trench hole 3 is formed by a thermal oxidation process.
By oxidizing the side walls and the bottom surface of the third hole 3 and the surface of the pillar 35, a 20 nm-thick silicon oxide film 38 is formed on the side wall and the bottom surface of the trench hole 33 and a 20 nm-thick silicon oxide film 37 is formed on the surface of the pillar 35 ( FIG. 7 (b). Thereafter, the conditions under which the silicon oxide film is etched first (SiO ₂ =
Etching (corresponding to 25 nm etching) is performed (FIG. 8).
(A)) Subsequently, the trench hole 35 is etched under conditions that allow the silicon of the semiconductor substrate to be etched with high selectivity with respect to TEOS and the silicon oxide film. As a result, a trench hole 34 having a depth of 8 μm from the silicon interface of the semiconductor substrate 30 is formed, and a trench hole 39 is also formed inside the pillars 36 and 37 (see FIG. 8B). A 6-nm-thick silicon nitride film, which is a capacitor insulating film (dielectric), is formed on the inner surfaces of the trench holes 33 and 34 and the inner surfaces of the pillar holes 36 and 37 formed in the above manner. By embedding a polysilicon film in trench holes 23 and 24, a capacitor having a surface area approximately 2.1 times that of a conventional trench structure can be obtained.

Next, a fourth embodiment will be described with reference to FIGS. As described above, the first to third embodiments have described the trench-structured capacitors formed in the semiconductor substrate.
There is. The DRAM uses a one-transistor type cell as shown in FIG. 9 in which the number of constituent elements per memory cell is small for high bit integration.
It is characterized by being composed only of a capacitor and a MOS transistor for transferring the charge.

FIG. 9 is a circuit diagram of a DRAM memory, and FIG.
Is a sectional view of a semiconductor substrate on which a DRAM memory element is formed, and FIG. 11 is a schematic plan view of the semiconductor substrate partially showing a memory element pattern. The semiconductor substrate 40, for example, p
A transistor (Tr) and a capacitor (C) for one memory cell are formed on the silicon semiconductor substrate. A trench hole 47 is formed in the main surface of the semiconductor substrate 40. Inside the trench hole 47, a polysilicon pillar 41 is formed from the bottom surface toward the opening end. A dielectric film 42 of a silicon nitride film is formed on the bottom and side surfaces of the trench hole 47 and on the surface of the pillar 41. An n-type impurity diffusion region 44 is formed inside the semiconductor substrate near the side wall and bottom surface except for the upper part of the trench hole. A silicon oxide film (SiO ₂ ) for preventing a short circuit with the substrate except for a part of the opening end of the upper side wall of the trench hole 47
45 are formed. Then, polysilicon films 43, 43 ', 43 "are formed inside the trench holes 47. In such a trench structure, the pillar 41 and the n-type impurity diffusion region 44 serve as a first electrode, and a dielectric film is formed. 4
2 as a dielectric, polysilicon films 43, 43 ', 43 "
Is a second electrode, and a capacitor (C) is formed.

On the other hand, a MOS transistor (Tr) is formed on the main surface of the semiconductor substrate 40. That is, n-type impurity diffusion regions 46, 46 serving as source / drain regions
Are formed near the trench hole 47. Also,
A gate 49 made of a polysilicon film or the like is formed above the source / drain regions 46, 46 with a gate oxide film 48 interposed therebetween. One of the source / drain regions is electrically connected to the second electrode of the capacitor (C) (the first electrode is grounded). Such a MOS transistor and a capacitor constitute a memory cell shown in FIG. As shown in FIG. 11, one memory cell 50 is repeatedly formed vertically and horizontally on a semiconductor substrate 40 to form a cell array. N-type impurity diffusion region 4 of memory cell 50
4 denotes an n-type impurity diffusion region 44 'of an adjacent memory cell.
And is joined. The capacitor of this embodiment has a larger surface area than that of the conventional capacitor due to the formation of the pillar, and therefore has a capacity 1.7 times larger than that of the conventional capacitor. DR
AM is required to maintain a constant value of capacitance at least a certain value regardless of the miniaturization of memory cells in order to ensure the frequency of refresh operation, operation margin during sensing operation, and reduction of soft error rate by alpha rays. There is.
Since the capacitance of this embodiment is larger than that of the conventional capacitor, it is most suitable for use in a DRAM.

In the above embodiment, a magnetron RIE apparatus was used for anisotropic etching for forming a trench hole in a semiconductor substrate.
Various etching devices such as a CR-RIE device or a simple parallel plate type RIE device can be used, and the present invention is not limited to a magnetron RIE device. Although polysilicon is used as the pillar in the above-described embodiment, various kinds of conductive materials such as a semiconductor material such as amorphous silicon, various conductive materials such as silicon carbide (SiC), silicide, and carbon may be used as appropriate. it can. Further, in the above-described embodiment, the combination of BSG as the color material for the sidewall of the trench hole and the combination of TEOS as the hard mask material for the trench hole are used. However, another suitable combination of materials may be used. For example, instead of BSG, BPSG (Boron-doped Phospho-Silicate Glass) is used as a material capable of obtaining a selectivity with respect to TEOS in a gas phase HF treatment.
And PSG (Phospho-Silicate Glass), SOG (Spin On
Glass) can be used. Also, for example,
As a hard mask material, a material such as a thermal oxide film or a SiN film can be used instead of TEOS.

In the above embodiment, TEOS / SiN / SiO 2 is used as a hard mask material for forming a trench.
_{Although the two} laminates were used, various materials, film configurations, film thicknesses, and the like can be arbitrarily selected according to the purpose. For example, a TEOS single-layer film or a single-layer film of a thermal oxide film can be used. In the above embodiment, TEOS was used as a hard mask material for trench etching. However, a SiO ₂ material such as a thermal oxide film, which can obtain a selectivity with respect to BSG, can be used. It is also possible to use another material such as a SiN film. In addition, conditions such as the diameter of the pillar, the amount of oxidation when oxidizing the pillar, and the depth of the trench hole in the above embodiment can be arbitrarily selected according to the purpose. In the above-described embodiment, the vertical trench hole is formed. However, the trench hole becomes narrower at a deeper position, the trench hole has a larger diameter at a deeper position, and the trench hole changes in thickness in the middle. Any shape of can be selected. Further, in the above-described embodiment, the pillar forming step is used as a technique for forming a capacitor, but the present invention can be applied to purposes other than forming a capacitor.

[0027]

According to the present invention, since the surface area of the capacitor can be increased by using the pillar structure as a trench capacitor, the capacitance can be increased without increasing the outer diameter of the capacitor. be able to. Further, a pillar having a smaller diameter can be formed in the trench hole in a self-aligned manner, and a structure which is lower than the limit of the lithography process can be easily formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment and a manufacturing process thereof.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

3A and 3B are a cross-sectional view and a plan view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 5 is a sectional view showing the manufacturing process of the semiconductor device according to the second embodiment;

FIG. 6 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment.

FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the third embodiment.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the third embodiment.

FIG. 9 is a circuit diagram of a DRAM memory cell according to a fourth embodiment.

FIG. 10 is a sectional view of a semiconductor device according to a fourth embodiment.

FIG. 11 is a plan view of a semiconductor device according to a fourth embodiment.

FIG. 12 is a sectional view showing a manufacturing process of a conventional device.

FIG. 13 is a sectional view showing a manufacturing process of a conventional device.

[Explanation of symbols]

1, 21, 31, 101... Silicon nitride film, 2, 2
2, 32, 102... TEOS film, 3, 23, 24,
33, 34, 39, 47, 103 ... trench holes,
4, 42, 104 ... capacitor insulating film, 5, 25,
105... Polysilicon layer, 6, 25 ', 26', 3
5, 36, 41 ... pillar, 7, 27 ... BSG
Film, 7 ', 27' ... Color BSG film, 8, 2
8, 38, 45 ... silicon oxide film, 9, 43, 4
3 ′, 43 ″, 105... Polysilicon film, 10, 2
0, 30, 40, 100 ... semiconductor substrate, 37 ...
Silicon oxide films (pillars), 44, 44 '... N-type impurity diffusion regions; 46, source / drain regions (n-type impurity diffusion regions); 48, gate oxide films;
.. Gate, 50... Memory cells.

Claims (5)

[Claims] 1. A semiconductor substrate on which a semiconductor element and a capacitor are formed, a trench hole having a predetermined opening diameter formed on a main surface of the semiconductor substrate, and a bottom formed on a bottom surface of the trench hole. A pillar made of a conductive layer formed toward the substrate, an insulating film formed on the trench hole side wall and the surface of the pillar, and a conductive film embedded at least in the trench hole. A semiconductor device comprising: a substrate and the pillar as a first electrode; the insulating film as a dielectric; and the conductive film as a second electrode. 2. A semiconductor substrate on which a semiconductor element and a capacitor are formed, a first trench having a predetermined opening diameter formed on a main surface of the semiconductor substrate, and a bottom formed on the bottom of the first trench. A pillar made of a conductive layer formed from the bottom surface toward the opening end, a second trench hole formed from the top surface of the pillar toward the bottom surface, the inside of the first and second trench holes, and An insulating film formed on a pillar surface; and a conductive film buried in at least the first and second trench holes, wherein the capacitor connects the semiconductor substrate and the pillar to a first electrode,
A semiconductor device, wherein the insulating film is a dielectric, and the conductive film is a second electrode. 3. A step of forming a trench hole having a predetermined opening diameter on a main surface of the semiconductor substrate, a step of forming an insulating film on a side wall of the trench hole, and an insulating film on the main surface of the semiconductor substrate and the side wall. Filling the inside of the trench with the conductive layer, etching the conductive layer on the main surface of the semiconductor substrate to leave the conductive layer only inside the trench, and forming the conductive layer only on the sidewall of the trench. Forming a pillar composed of the conductive layer formed from the bottom surface toward the opening end on the bottom surface of the trench hole by etching and removing the formed insulating film. Device manufacturing method. 4. A step of forming a first trench hole having a predetermined opening diameter on a main surface of the semiconductor substrate, a step of forming an insulating film on a side wall of the first trench hole, and a step of forming an insulating film on the main surface of the semiconductor substrate. Filling a conductive layer inside the first trench hole in which an insulating film is formed on the side wall; and etching the conductive layer on the main surface of the semiconductor substrate to remove the conductive layer inside the first trench hole. And removing the insulating film formed on the side wall of the first trench hole by etching to form a conductive layer formed on the bottom surface of the first trench hole from the bottom surface toward the opening end. Composed first
Forming the first pillar, oxidizing the first pillar and the side wall of the first trench hole facing the first pillar, and etching the bottom surface of the first trench hole to form the first pillar. A second trench hole is formed below the trench hole, the second trench hole being continuous with the first trench hole, and an oxide film formed by oxidation on the side wall of the first trench hole is masked below the first pillar. By performing anisotropic etching, the second pillar continuous with the first pillar is formed.
Forming a pillar as described above. 5. A step of forming a first trench hole having a predetermined opening diameter on a main surface of the semiconductor substrate, a step of forming an insulating film on a side wall of the first trench hole, and Filling a conductive layer inside the first trench hole in which an insulating film is formed on the side wall; and etching the conductive layer on the main surface of the semiconductor substrate to remove the conductive layer inside the first trench hole. And removing the insulating film formed on the side wall of the first trench hole by etching to form a conductive layer formed on the bottom surface of the first trench hole from the bottom surface toward the opening end. Composed first
Forming the first pillar, oxidizing a surface of the first pillar and a sidewall of the first trench hole facing the first pillar, and etching a bottom surface of the first trench hole to form the first pillar. Forming a second trench continuous with the first trench below the trench, and forming a second pillar continuous with the first pillar below the first pillar. And anisotropically etching the first and second pillars using an oxide film formed by oxidizing the surface of the first pillar as a mask, thereby forming the first and second pillars. Forming a second trench in the semiconductor device.