JP2001015702A - Dram fixedly loaded logic lsi - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase operating speed and lower dissipation power, without spreading pattern area by determining arrangement references on a silicon chip of a DRAM core section and a logic section, dispensing with a data bus and directly connecting the core section and the logic section by using a data line. SOLUTION: In DRAM core sections 2, low decoders 6 are arranged at central sections so as to divide memory cell arrays 3 left and right in large portion, and column decoders are arranged to peripheral circuit sections 7 on the lower sides of cells. Data lines 5b are disposed on the extensions of column lines 5a parallel with bit lines 5 arranged in the row directions of the memory cell arrays, so as to penetrate from upper sections to lower sections through I/O buffers 7a, and connected directly to the input/output sections of a corresponding logic section 8 without going through the intermediary of data buses normally mounted on the interfaces of the DRAM core sections and logic sections. Here, the I/O buffers 7a and the input/output sections of the logic section 8 are disposed so as to face mutually, the constitution of the data lines 5b is simplified, and effective wiring length is shortened to a large extent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM embedded logic LSI, and more particularly to a method of connecting a DRAM core and a logic, and a method of arranging a DRAM core and a logic.

[0002]

2. Description of the Related Art Conventionally, a logic LSI and a memory LSI (D
RAM (Dynamic Random Access Memory) has been used separately, but with the advancement of semiconductor fine processing technology, it has become possible to integrate them into one chip. That is, in recent years, a semiconductor integrated circuit called a DRAM embedded logic LSI in which a DRAM core unit and a logic unit are mounted on one chip has been developed.

FIG. 6 shows an example of a chip layout of a conventional DRAM embedded logic LSI. 6 includes a silicon chip 101 and a DRAM.
A core unit 102, a memory cell array 103 in which memory cells are arranged in a matrix in a matrix, a minimum memory cell array 103a in which the memory cell array 103 is divided into blocks as shown by broken lines in FIG. A line 104, a bit line 105 in the column direction, a column line 105a to which the bit line 105 is connected in the column direction,
A row decoder 106 for selecting a word line, a column decoder 107b for selecting a column line, a sense amplifier,
A peripheral circuit unit 107 including an O-buffer and the like;
And a logic unit 108 (only the location of the logic unit 108 is indicated by an arrow) arranged above, below, or around the core unit 102.

As described above, the conventional DRAM embedded logic L
In SI, the DRA is usually located at the center of the silicon chip 101.
The M core unit 102 is arranged, and the logic unit 108 is arranged above, below, or around it. As described above, the DRAM core unit 102 includes the memory cell array 103 and a circuit unit for accessing the memory cell array 103, that is, a decoder or a sense amplifier in a row direction or a column direction, an I / O buffer, and the like.
Memory cell array 103 in DRAM core unit 102
Is generally divided into two parts vertically and horizontally, and a peripheral circuit part 107 for accessing the DRAM core part 102 is provided at a central part on the left and right sides.
Is arranged.

[0005] DRAM core unit 102 and logic unit 108
Each has a plurality of input / output buffers and an input / output unit, is connected by using a plurality of data lines and a bus line arranged in an interface between them, and is used to transfer data between the DRAM core unit and the logic unit. An exchange takes place.

Hereinafter, in this specification, a wiring portion led out from each of a plurality of I / O buffers of a DRAM core portion is called a data line, and data transmitted through the data line is collected to form a DRAM core portion and a logic portion. And a data bus that transfers data between the data buses. In addition,
The bit line is a wiring in the column direction for transferring write / read data to / from a memory cell in the area of the memory cell array 103, and is connected to the data line via the column line.

As described above, the DRAM embedded logic L
In the layout of the SI, as shown in FIG. 6, a conventional DRAM is simply cut out and pasted on a chip,
The AM core not only increases the pattern area of the I / O buffer and the like, but also complicates the wiring configuration for connecting the DRAM core and the logic unit, increases the wiring delay, and increases the speed and power consumption. It will be difficult to realize this.

When the number of DRAM cores is one, it is possible to avoid an increase in wiring delay to some extent by setting wiring routes manually. In fact, it has become extremely difficult to avoid the above problems.

[0009]

As described above, when a DRAM embedded logic LSI including one or a plurality of DRAM cores is developed by using the conventional layout method, especially when there are a plurality of DRAM cores, a wiring configuration is required. However, there is a problem that the operation speed is reduced more than expected because the pattern area increases and the pattern area increases, and it becomes difficult to improve the performance of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made to increase the speed without increasing the pattern area.
An object of the present invention is to provide a chip layout of a DRAM embedded logic LSI capable of reducing power consumption.

[0011]

According to the present invention, there is provided a DRAM-embedded logic LSI in which a positional relationship between an I / O buffer (referred to as an input / output buffer in the claims) of a DRAM core unit and an input / output unit of a logic unit is determined. Focus is placed on the arrangement standard of the DRAM core unit and the logic unit on a silicon chip (hereinafter simply referred to as a chip), and a direct connection is made using a data line without using a data bus.

In particular, when there are a plurality of DRAM cores, a pair of mirror-symmetric DRAM cores is formed so that the I / O buffers face each other, and a data bus is arranged between the DRAM cores. By connecting the lines, the logic unit connected to the data bus and the DRAM core unit are connected. At this time, a plurality of pairs of mirror-symmetrical DRAM core sections and the logic section are provided with optimal placement criteria on the silicon chip.

Specifically, the DRAM embedded logic LSI of the present invention comprises a memory cell array in which memory cells are arranged in a matrix, a plurality of word lines arranged along a row direction of the memory cell array, DRAM having a plurality of bit lines arranged along a column direction
In a DRAM embedded logic LSI in which a core portion, a DRAM core portion and a logic portion are formed on the same chip, n (n is a natural number) input / output buffers of the DRAM core portion and n logic portions of the logic portion are provided. The input / output units are arranged so as to face each other, and data lines are respectively drawn out of the n input / output buffers of the DRAM core unit in parallel with the plurality of bit lines. A buffer and n input / output units of the logic unit are directly connected to each other by the data lines without passing through a data bus.

Preferably, the DRAM embedded logic LS
I, when there are a plurality of DRAM core units,
The RAM core part is adjacent to one side of the chip along one side of the chip such that the bit lines are parallel to each other and the bit lines are perpendicular to one side of the chip. It is characterized in that it is arranged in one row, and the logic part includes constituent parts arranged on the side of the opposite side of the chip.

Further, the DRAM embedded logic LS of the present invention
I is a memory cell array in which memory cells are arranged in a matrix, a plurality of word lines arranged along a row direction of the memory cell array, and a plurality of bit lines arranged along a column direction of the memory cell array. A pair of DRAs with
A DRAM embedded logic LS in which an M core portion and the pair of the DRAM core portion and the logic portion are formed on the same chip;
I, each of the pair of DRAM core units has n (n
(A natural number) input / output buffers are arranged in mirror symmetry so as to face each other, and a data bus including a control signal line is arranged between the pair of DRAM cores along the mirror symmetry center line. From the n input / output buffers of the pair of DRAM core units, data lines are drawn out in parallel with the plurality of bit lines, respectively, and the n input / output buffers of the pair of DRAM core units are connected to the n input / output buffers, respectively. A data bus is connected by the data line, and the data bus is connected to an input / output unit of the logic unit.

Preferably, the DRAM embedded logic LS
I, when the number of pairs of the pair of DRAM core units is plural, the plural pairs of DRAM core units are arranged so as to have a common mirror-symmetric center line parallel to one side of the chip; The data buses arranged along the mirror-symmetric center line are connected to each other so as to be a common data bus of the plurality of pairs of DRAM core portions, and the plurality of pairs of DRAM core portions are adjacent to each other. The pair of DRAs
The logic unit is provided between the M core units, and the data bus includes a component connected to an input / output unit of the logic unit.

Preferably, in the DRAM-embedded logic LSI of the present invention, when the number of pairs of the pair of DRAM core units is plural, the plurality of pairs of DRAM core units include a bit of each of the plurality of pairs of DRAM core units. The lines are parallel to each other,
The bit lines are arranged in a row adjacent to one side of the chip along one side of the chip so that the bit lines are parallel to one side of the chip. It is characterized by including a constituent part in which the logic part is arranged on a side.

Preferably, the DRAM-embedded logic LSI includes at least a first-layer metal wiring and a second-layer metal wiring, and the word line is formed by the first-layer metal wiring, and the bit line And the data line is formed by the metal wiring of the second layer.

In forming the DRAM embedded logic LSI, if the automatic placement and routing is performed so as to prohibit the placement of the DRAM core portion which deviates from the above-mentioned standard, the wiring configuration for connecting the DRAM core portion and the logic portion is simplified. Since the effective wiring length is shortened, a high-speed and low-power-consumption DRAM embedded logic LSI can be obtained without increasing the pattern area.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing a chip layout of a DRAM embedded logic LSI according to a first embodiment of the present invention. The chip layout shown in FIG.
, DRAM core unit 2, memory cell array 3, word line 4, bit line 5, data line 5a, and row decoder 6
And a column decoder, a sense amplifier, and an I / O buffer 7
The logic circuit 8 includes a peripheral circuit 7 including a and the like.

The DRAM embedded logic LS shown in FIG.
When I is viewed from above the chip, the DRAM core unit 2 is arranged on the upper side, the logic unit 8 is arranged on the lower side, and the
A plurality of data lines 5 connecting the AM core unit and the logic unit
b is arranged. In FIG. 1, I / O
On the extension of the column line 5a from the buffer 7a, one data line 5b drawn toward a corresponding input / output unit (not shown) of the logic unit 8 is illustrated.

The DRAM core unit 2 includes a memory cell array 3
Row decoder (RDC; Row
Decoder 6) is arranged in the center, and a column decoder (not shown) is arranged in the peripheral circuit section 7 below the cell. The data line 5b is arranged on the extension of the column line 5a parallel to the bit line 5 arranged in the column direction of the memory cell array so as to penetrate from the top to the bottom via the I / O buffer 7a. It is directly connected to the input / output unit of the corresponding logic unit 8 without passing through a data bus provided at the interface between the unit and the logic unit. At this time,
By arranging the I / O buffer 7a of the DRAM core unit and the input / output unit of the logic unit 8 so as to face each other, the configuration of the data line 5b is simplified, and the effective wiring length can be greatly reduced.

If a plurality of DRAM cores are required,
The layout may be expanded in the horizontal direction of FIG. 1 while maintaining the mutual arrangement of the DRAM core unit and the logic unit on the chip shown in FIG.

That is, as shown in FIG. 2, the bit lines 5 of the plurality of DRAM core units 2 are parallel to each other,
The plurality of DRAM core units 2 are adjacent to each other along one side of the chip 1 so that the bit line 5 is perpendicular to one side of the chip 1.
Are arranged in one column, and the logic unit 8 is arranged on the other side of the chip 1 opposite to the chip 1, so that the I / O buffer 7a of the DRAM core unit 2 and the corresponding input / output unit of the logic unit 8 And the I / O buffer 7a and the input / output unit may be directly connected using the data line 5b without passing through the data bus.

Next, a layout of a DRAM embedded logic LSI according to a second embodiment of the present invention will be described with reference to FIG. DRAM embedded logic LSI shown in FIG.
Denotes a chip 1 and a pair of DRAs vertically arranged to be mirror-symmetrical to each other with respect to a horizontal center line of the chip 1.
The M core unit 2, the memory cell array 3, the word line 4, the bit line 5, the row decoder 6, the peripheral circuit unit 7, and the I / O included in the pair of DRAM core units 2, respectively. O buffer 7a. In FIG. 3, a data bus 5c is arranged in parallel along a mirror-symmetric center line in the horizontal direction. This data bus contains DRAM
A control signal line for controlling the operation of the embedded logic LSI is also included.

The opposite I / Os of the pair of DRAM cores
A data line 5b is extended from the O buffer 7a in parallel with the bit line 5 on an extension of the column line 5a, and connected to the data bus 5c. The data bus 5c is drawn out to the right of the chip 1 on which the logic section 8 is arranged, and is connected to a corresponding input / output section of the logic section 8.

In this way, especially when there are a plurality of DRAM core sections, the configuration of the data bus conventionally routed to the interface between the DRAM core section and the peripheral logic section surrounding the DRAM core section is simplified and reduced in effect. The wiring length can be reduced.

When a plurality of pairs of the DRAM core units are required, the layout may be expanded in the horizontal direction while maintaining the mutual arrangement of the DRAM core unit and the logic unit on the chip shown in FIG. .

That is, as shown in FIG. 4, the plurality of pairs of DRAM core units 2 are arranged so as to have a common mirror-symmetric center line parallel to one side of the chip 1, and The plurality of pairs of data buses 5c are connected to each other such that the plurality of data buses 5c are shared by the plurality of pairs of DRAM core units.
The RAM core unit 2 is a pair of adjacent DRAM core units 2
And the data bus 5c may be connected to the input / output unit of the logic unit 8.

In FIG. 4, the four DRAM cores 2 have a mirror-symmetric center line in the horizontal direction of the chip 1 along the data bus 5c, and at the same time, the vertical direction of the chip 1 perpendicular to the data bus 5c. Although the logic unit 8 is arranged so as to have a mirror-symmetric center line, the logic unit 8 does not necessarily need to be arranged so as to have the vertical and horizontal mirror-symmetric center line.

As in the case of the four DRAM core parts, when the logic part 8 has the vertical and horizontal mirror-symmetric center lines, the wiring configuration is simplified most, but the symmetry of the logic part 8 is reduced. However, there is no significant effect on the increase in the effective wiring length.

FIG. 4 shows a case in which the logic unit 8 is arranged between two pairs of mirror-symmetrical DRAM cores composed of two DRAM cores. Are arranged in a row in the horizontal direction, and each adjacent 1
It goes without saying that a logic section may be arranged between the pair of DRAM core sections.

As another example of the arrangement in which a plurality of pairs of DRAM core units are required, a layout is vertically arranged while maintaining the mutual arrangement of the DRAM core unit and the logic unit on the chip shown in FIG. FIG. 5 shows an example of an extended arrangement.

That is, as shown in FIG. 5, the plurality of pairs of DRAM core units 2 have their bit lines 5 parallel to each other, and the bit lines 5 are parallel to one side of the chip 1. As described above, one side of the chip 1 is arranged along one side of the chip 1 and adjacent to each other in a row,
The logic unit 8 is arranged on the side of the chip opposite to the chip, and in the plurality of pairs of DRAM core units 2, the data lines 5 b drawn from the opposing I / O buffers 7 a are connected to the pair of DRAM core units 2. And a data bus 5c disposed between the logic unit 8 and the data bus 5c.
May be connected to the corresponding input / output unit.

The D of the first and second embodiments described above
The RAM embedded logic LSI includes at least a first layer metal wiring and a second layer metal wiring, and the word lines 4 of the memory cell array 3 in the DRAM core unit 2 are formed by the first layer metal wiring. The bit line 5 and the data line 5b connected to the column line 5a via the I / O buffer 7a are formed using a second layer metal wiring.

The present invention is not limited to the above embodiment. In the first and second embodiments, the case where the DRAM core unit and the logic unit are mixedly mounted on one chip has been described, but the target of the mixed mounting is not necessarily limited to the DRAM core unit. For example, when an SRAM or ROM is used instead of the DRAM,
The layout of the present invention can be applied. In addition, various modifications can be made without departing from the spirit of the present invention.

[0038]

As described above, according to the DRAM embedded logic LSI of the present invention in which the DRAM core portion is arranged,
Since the wiring configuration for connecting the RAM core part and the logic part is simplified, not only the increase in the pattern area in the interface between the two is suppressed, but also the speeding up of the device and the reduction in power consumption are achieved. Can be. Further, when there are a plurality of DRAM cores, if the I / O buffers of the pair of DRAM cores are arranged face-to-face with mirror symmetry, and a data bus is provided along this line of symmetry, the data bus can be used. Thus, even when the DRAM core unit and the logic unit are connected, it is possible to achieve high-speed and low power consumption of the device.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a DRAM embedded logic LSI according to a first embodiment.

FIG. 2 is a layout diagram of a DRAM embedded logic LSI according to the first embodiment having a plurality of DRAM core units.

FIG. 3 is a layout diagram of a DRAM embedded logic LSI according to a second embodiment;

FIG. 4 is a layout diagram of a DRAM embedded logic LSI according to a second embodiment having a plurality of pairs of DRAM core units;

FIG. 5 is a diagram illustrating another layout of a DRAM embedded logic LSI according to a second embodiment having a plurality of pairs of DRAM core units;

FIG. 6 is a layout diagram of a conventional DRAM embedded logic LSI.

[Explanation of symbols]

 1, 101 silicon chip 2, 102 DRAM core part 3, 103 memory cell array 103a minimum memory cell array 4, 104 word line 5, 105 bit line 5a, 105a column line 5b, 105b data line 5c Data bus 6, 106: Row decoder 7, 107: Peripheral circuit unit 7a: I / O buffer 107b: Column decoder 8, 108: Logic unit

Claims (6)

[Claims] A memory cell array in which memory cells are arranged in a matrix; a plurality of word lines arranged in a row direction of the memory cell array; and a plurality of bits arranged in a column direction of the memory cell array. A DRAM core unit having a DRAM core unit and a logic unit formed on the same chip, wherein the DRAM core unit includes n (n is a natural number) input / output buffers; The n input / output units of the logic unit are arranged so as to face each other, and data lines are respectively drawn out of the n input / output buffers of the DRAM core unit in parallel with the plurality of bit lines. N input / output buffers and n input / output units of the logic unit are respectively connected by the data lines without passing through a data bus. A logic LSI integrated with DRAM, which is directly connected. 2. When the number of said DRAM core units is plural,
The plurality of DRAM cores are arranged along one side of the chip so that the bit lines are parallel to each other and the bit lines are perpendicular to one side of the chip.
2. The DRAM-embedded logic LSI according to claim 1, wherein the logic unit is arranged in a row adjacent to one side, and the logic unit includes a component arranged on the other side of the chip facing the other side. . 3. A memory cell array in which memory cells are arranged in a matrix, a plurality of word lines arranged in a row direction of the memory cell array, and a plurality of bits arranged in a column direction of the memory cell array. A pair of DRAM core units each having a line, and a pair of DRAM core units and a logic unit, wherein the pair of DRAM core units and the logic unit are formed on the same chip. (N is a natural number) input / output buffers are arranged mirror-symmetrically to face each other, and a data bus including a control signal line is arranged between the pair of DRAM cores along the mirror-symmetric center line. A data line extending in parallel with the plurality of bit lines from each of the n input / output buffers of the pair of DRAM core units; Wherein each of n input and output buffers and the data bus are connected by the data line, and, DRAM-embedded logic LS, wherein the data bus is connected to the input and output portions of the logic unit
I. 4. When the number of pairs of the pair of DRAM core units is plural, the plural pairs of DRAM core units are arranged so as to have a common mirror-symmetric center line parallel to one side of a chip. The data buses arranged along the mirror-symmetric center line are connected to each other so as to be a common data bus of the plurality of pairs of DRAM core units, and the plurality of pairs of DRAM core units are 4. The logic device according to claim 3, further comprising the logic unit disposed between the pair of adjacent DRAM core units, wherein the data bus includes a component connected to an input / output unit of the logic unit. DRAM embedded logic LSI. 5. When the number of pairs of the pair of DRAM core units is a plurality of pairs, the plurality of pairs of DRAM core units are configured such that bit lines of the plurality of pairs of DRAM core units are parallel to each other, And one side of the chip along one side of the chip such that the bit line is parallel to one side of the chip.
4. The DRAM-embedded logic LSI according to claim 3, further comprising a component part arranged in a row adjacent to one side and having the logic part disposed on the other side opposite to the chip. 6. The DRAM-embedded logic LSI includes at least a first-layer metal wiring and a second-layer metal wiring, wherein the word line is formed by the first-layer metal wiring, and wherein the bit line and the bit line are formed. 5. The data line according to claim 1, wherein the data line is formed of the second layer metal wiring.
The logic LSI with embedded DRAM according to any one of the above.