JP2001014287A - Serial communication device and serial communication method, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make normally performable the subsequent serial communications even when an option unit is removed from an electronic device without turning off the power supply of the electronic device main body. SOLUTION: The array order of slave station having the states '1' of bit 2 among the data on lower 4 bits stored in a memory is scanned and retrieved via the loops of steps S1-S4. When the first normal communication processing is not decided after the initialization communication processing, the retrieved array order of slave stations is compared with the array order of slave stations stored in the memory (S3→S5→S7). If the difference is recognized between both array orders, it is required to perform again the initialization communication processing (S8).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a serial communication device, a serial communication method, and a storage medium for serially communicating information between a central processing unit and a plurality of electric units provided in an electronic device.

[0002]

2. Description of the Related Art A serial communication device for serially communicating information between a central processing unit and a plurality of electric units provided in an electronic device has been known.

[0003] Such a serial communication device includes a main device for serial communication called a master station of a central processing unit in the electronic device, and a slave station of a plurality of electric units scattered in the electronic device. The main device and the sub-device exchange information between the main device and the sub-device. Many electronic devices are used for the purpose of suppressing the ease of assembling electronic devices and manufacturing costs. Used in equipment.

Information exchange by a serial communication device has been basically performed by serial communication executed in response to an information exchange request generated by a main station attached to a CPU serving as a central processing unit. Therefore, when the slave station wants to exchange information, it transmits a communication request signal to the master station, and when the master station receives this signal, the master station executes serial communication in response to the signal, thereby receiving a signal from the slave station. Information was updated and both parties exchanged information. This exchange of information
Since the master station and the slave station are implemented on a one-to-one basis, the transfer information generated from the master station is transferred to a specific slave station, and the transfer information returned from the slave station is the master station. Both the master and slave stations had to be aware that they came from the slave station identified by

For this reason, many conventional serial communication devices have attached transfer information with identifier information designating a slave station. Therefore, in this transfer method, it is necessary to distinguish all the slave stations connectable to the transmission line by the identifier information, so that the method is established after limiting the maximum number of slave stations. In other words, the data length (number of bits) of the data (transfer information + identifier information) transferred to the slave station is determined according to the maximum number of slave stations that can exist on the transmission path. This means that communication protocols and data processing devices cannot be designed.

As described above, in the conventional serial communication device, it is necessary to determine the number of connectable slave stations in advance.
The number of slave stations must be set larger than actually required, and the communication protocol and the data processing device must be designed. This has increased the cost for manufacturing a serial communication device.

Further, when the configuration of the number of slave stations in the electronic equipment is changed and the design is changed accordingly, the data length of the basic transfer data is changed. I needed to.

In recent years, therefore, the data length (the number of transfer information bits + the number of identifier information bits) of the data (the transfer information + identifier information) transferred to one slave station has been fixed.
2. Description of the Related Art A serial communication device including a communication protocol that enables connection of a semi-infinite number of slave stations and a data processing device that performs data processing based on the communication protocol has been developed. As a result, the same serial communication device can be used with an optimum number of slave stations regardless of the number of slave stations provided in the electronic device, so that it is possible to easily cope with a design change in the middle, and The manufacturing cost can be reduced as compared with the conventional serial communication device.

Hereinafter, a serial communication device which can connect a semi-infinite number of slave stations while keeping the number of transfer information bits and the number of identifier information bits fixed will be described in detail with reference to FIGS. Before that, an outline of this serial communication device will be described.

In this serial communication apparatus, the master station creates transfer information of a predetermined data length, and the shift register circuit of each slave station (the number of constituent bits is, for example, 4 bits for convenience of explanation. The number of bits is not limited to this.) The slave station parallel output information from the master station is shift-transferred together with the transfer clock, and should be returned to the shift register circuit in advance to the shift register circuit before the shift transfer by the master station. By loading the parallel input information of the slave stations, information is exchanged between the master station and each slave station in the shift transfer performed by the master station.

Each slave station has a phase control counter circuit, and is configured to execute an operation specified by the count value of the phase control counter circuit. By controlling the count value of the phase control counter, the master station can control the operation of the slave station with respect to, for example, a shift register circuit. In order to control the phase control counter circuit of each slave station, the master station also includes a phase control counter, and by performing operation control in the same manner as the phase control counter circuit of the slave station,
The operation status of each slave station can be grasped by its count value, and the operation control of each slave station in the transmission path is executed to perform serial communication.

On the other hand, the master station recognizes a semi-infinite number of slave stations that can be connected to the transmission line with a fixed number of identifier information bits, and implements one-to-one information exchange in order to perform two-to-one information exchange. It is configured to perform communication independently.

One is communication for the purpose of recognizing a slave station existing on a transmission line, and is called "initialization communication" in the present serial communication device. In this initialization communication, identifier information of each slave station is received, and the sequence of slave stations in the transmission path is recognized based on the identifier information.

The other is communication for creating and transferring shift transfer data in accordance with the sequence of slave stations recognized in the initialization communication, and is called "normal communication" in the present serial communication device. In this normal communication, information exchange with each slave station is performed on a one-to-one basis. In other words, the sequence of the slave stations connected to the current transmission path is invariable once recognized by the initialization communication, so if the master station shifts and transfers data created according to the slave station order to each slave station, Similarly, from each slave station, return information data created in accordance with the order of arrangement of the slave stations is shifted and returned, so that information exchange is easily performed.

Here, a basic idea for recognizing the number of slave stations equal to or greater than the number of slave stations that can be represented by a fixed number of bits of identifier information will be described. Note that the fixed number of identifier information bits will be described as, for example, 4 bits, but this is for convenience of description and is not particularly limited.

First, as a premise, a slave station is classified into two types based on the configuration of electronic equipment to which the present serial communication device is applied.

One is that a slave station used as an indispensable unit for the operation of the electronic device main body is called a “main unit”, and identifier information is assigned by a fixed value code.

The other is a slave station which is not essential to the operation of the electronic device itself and is used as an option as a so-called extension unit, which is called an "option unit".
In each case, identifier information is allocated with the remaining codes after the fixed value code is allocated. That is, the identifier information of the option unit is all zero (0000B), all ones
(1111B), a fixed value for the main unit (for example,
Code value other than 1 (set to 1101B)
1B). Here, “B” is a symbol indicating that the preceding numerical value is a binary number (binary).

When the arrangement order of the transmission lines is considered only by the configuration of the main unit, the arrangement order is invariable since the main unit is an essential unit. That is, the set slave station arrangement for the main unit is
Since there is no change when arranged only in the main unit, a memory map may be formed according to the order of arrangement in the transmission path.

Next, an optional unit slave station that can be connected based on the main unit slave station order will be described.

When the slave station is an optional unit, it is not known whether the slave station is connected to the transmission line. Therefore, the identifier information is allocated in order, but the arrangement order is determined by the main unit unit arrangement. Using the units, a plurality of option units existing between the main units are grouped as one group, and in the same group, 1, 2, 3,... These groups are formed between different main units. That is, the identifier information to which the option unit is allocated may be duplicated as long as the group is different.

According to this method, even if the number of slave stations is half-infinite, it can be distinguished by 4-bit identifier information. More specifically, a maximum of 13 optional units can be allocated between the first and second main units (to exclude all 0s, all 1s, and fixed value codes of the main units) with non-overlapping code values. If there are five units, for example, 4 × 13 = 52 optional units can be identified on a one-to-one basis. Conversely, if a main unit including a dummy corresponding to the required number of optional units is prepared, a semi-infinite number of slave stations can be recognized within the allowable range of the electric transmission capacity of the transmission line.

The overall operation in the case where the present serial communication device capable of connecting a semi-infinite number of slave stations described above actually executes communication is as follows.

First, in the electronic equipment to which the present serial communication device is applied, the master station presets the number of all slave stations connectable to the serial communication transmission line and the arrangement order thereof, and stores the slave station parallel input / output information contents. Mapping to a memory provided on the master station side.

Next, the master station executes the initialization communication to receive the identifier information in accordance with the arrangement order of the slave stations connected to the actual transmission line, and to determine whether or not there is a slave station registered in the memory. Is set, the mapped slave station arrangement order is reset to the slave station arrangement order existing in the current transmission path. Thus, the master station can grasp the slave station arrangement order existing on the transmission path, and thereafter, constructs and outputs shift transfer data in accordance with the slave station arrangement order indicated by the reset memory map, and outputs the input shift transfer data. The serial communication is executed by storing the data in the memory according to the slave station arrangement order indicated by the reset memory map. The serial communication at this time is “normal communication”, and the normal communication occupies most of the serial communication.

As described above, the data of the number of information bits corresponding to the predetermined number of slave stations is prepared, the return data is loaded to each slave station, and then the shift operation is executed. Since each slave station can transfer information to the master station, the time required for communication is minimized.
Since the signal processing is further simplified and the circuit configuration of the slave station is simplified, the manufacturing cost is reduced.

Further, in the normal communication, after one cycle of the shift transfer for exchanging information, a second round of the shift transfer is performed again with the same information, and a single serial communication operation is performed. By performing the information exchange operation and comparing the information content of the first cycle with the information content of the second cycle, the accuracy of the information content can be improved with a simple configuration, and erroneous transmission of information can be prevented.

Next, a detailed configuration of the serial communication device will be described.

FIG. 6 is a block diagram showing a schematic configuration of an electronic apparatus to which the present serial communication device is applied. The present electronic apparatus has one master station m and a plurality of (twelve in the illustrated example) slave stations s.
1 to s12. FIG. 6 shows all connectable slave stations, and an electronic device can be configured by a slave station arbitrarily selected from these slave stations.

FIG. 7 is a block diagram showing a detailed configuration of any one of the slave stations s1 to s12 in FIG. 6, and each of the slave stations s1 to s12 has the same configuration.

In FIG. 7, the input selector circuit 1 includes:
The parallel input information and the identifier input information are input, and the input selector circuit 1 selects either the parallel input information or the identifier input information as information to be returned from the slave station to the master station, and selects the input latch circuit 2 and the exclusive input information. The logical OR circuit A (hereinafter, referred to as “EXOR circuit A”) 3. The input latch circuit 2 latches and holds the selected information for the execution period of one serial communication, and holds the EXOR circuit A
3 and the shift register circuit 4.

The EXOR circuit A3 includes input information to the input latch circuit 2 (output information from the input selector circuit 1),
The output information from the input latch circuit 2 is compared for each bit, and the result is collectively output as one signal by a multi-input gate. This signal is turned on when any one bit changes. "1"), and at other times, it is turned off ("0") and output to the decode circuit B12.

The shift register circuit 4 is for the slave station to execute shift transfer. The shift register circuit 4 reads a shift-in signal in synchronization with a transfer clock and outputs information already stored as a shift-out signal. Further, the shift register circuit 4 reads the stored information twice and outputs the information to the latch circuit 5 and the EXOR circuit B6.

The double read latch circuit 5 latches and holds the information of the first cycle of the shift transfer, and outputs the information to the EXOR circuit B 6 and the output latch circuit 7.

The EXOR circuit B6 compares the information content in the second shift transfer with the information content latched and held by the twice-read latch circuit 5 on a bit-by-bit basis, and compares the result with one multi-input gate. This signal is turned on ("1") when any one bit does not match, turned off ("0") otherwise, and output to the decoding circuit B12. Is done.

The output latch circuit 7 performs a latch holding operation in response to the latch signal output from the decode circuit B12 with respect to the signal output from the EXOR circuit B6, and outputs the result to the outside as a parallel output of the slave station.

The gate circuit 8 is for instructing the input selector circuit 1 on the type of information to be selected. The gate circuit 8 uses the transfer clock and the soft reset signal as its input sources, and based on this, the selection instruction signal. Is output. Here, the soft reset signal is one of three types of signals (soft reset signal, forced reset signal, and count instruction signal) classified by the decoding circuit A9 based on a 2-bit slave station coded signal output by the master station. 1 signal.

The transfer clock is input to the shift register circuit 4, clock number counter circuit 10, and phase control counter circuit 11. Clock counter circuit 10
Counts this transfer clock and outputs a timing pulse for each predetermined value, and the phase control counter circuit 11
In response to the count instruction signal classified by the decode circuit A9, a count operation, a count stop holding operation, and the like are performed.

The master station also has a master station phase control counter circuit that operates in the same manner as the phase control counter circuit 11, and controls shift transfer.

The decoding circuit B12 uses the Q output, which is the count result of the phase control counter circuit 11, as an input source,
An operation instruction is issued to each circuit based on the control phase timing, and an input signal from each circuit is output to the master station as a return phase signal based on the control phase timing.

The operation of the shift register circuit 4 is basically controlled according to the count value of the phase control counter circuit 11 operated by the slave station coded signal output from the master station. In this way, the slave station is controlled by the master station. Specifically, the count value of the phase control counter circuit 11 (hereinafter simply referred to as “control count value”) is transferred by the phase control counter circuit 11 in accordance with a slave station instruction coded signal output by the master station. The count is performed by performing a count operation (operation such as count-up, stop, control count value reset, etc.) using the clock as a clock source. Then, the control count value is input to the next-stage decode circuit B12, and the decode circuit B12 directly outputs a timing instruction signal to a circuit that executes each slave station operation.

Hereinafter, the operation processing of the slave station will be described focusing on shift transfer.

When a soft reset is instructed by the slave station coded signal, the control counter value becomes 00H (“H”).
Means that the value before that is hexadecimal
l)).
During the soft reset, the input information of the input selector circuit 1 is selected by utilizing the fact that the control count value does not change even when the transfer clock is received. The gate circuit 8 is configured to switch the selection instruction signal of the input selector circuit 1 depending on whether or not the transfer clock is received during the soft reset. Thus, the input selector circuit 1 selects either the parallel input or the identifier input and transmits the information to the input latch circuit 2. Thereafter, when the soft reset is released and a new transfer clock is received, the input latch circuit 2 latches and holds the input information,
The information is accessed to the shift-in parallel input of the shift register circuit 4.

On the other hand, a latch signal is supplied from the decode circuit B12 to the input latch circuit 2, and the EXOR circuit A3
Compares the latch input and output of the input latch circuit 2 bit by bit and collectively supplies one signal to the decode circuit B12 by the gate circuit. This signal is a source of a communication request signal generated by the slave station, and is transmitted from the return phase signal to the master station at a predetermined control count value (valid at the timing of 0EH in this serial communication device). Is done.

Next, when the master station continuously instructs the control count value to be 01H, the output information of the input latch circuit 2 is shift-loaded into the shift register circuit 4, and the shift transfer operation is performed as the transfer clock is received. Be started. From this time, the master station generates transfer data and a transfer clock of the number of bits corresponding to the number of slave stations in the transmission path grasped in the initialization communication processing described later, and at a desired timing by a slave station instruction coded signal. While manipulating the control count value, instruction control is performed so that the control count value becomes 06H at the shift end timing for making a round of shift transfer.

The slave station has a control count value of 06H.
Then, it is determined that the first round of the shift operation has been completed, and the decode circuit B12 outputs a latch pulse for latching and holding the shift data of the shift register circuit 4 to the twice-read latch circuit 5. On the other hand, the shift register circuit 4
When the control count value becomes 00H, the information of the input latch circuit 2 latched and held can be accessed. Since the information content latched and held by the input latch circuit 2 is not updated except when the control count value becomes 00H, the same information content as the immediately preceding information content is retained when the control count value is 06H. ing.

Then, the master station sets the control count value to 07H.
Then, the second round of the shift transfer is started. The shift register circuit 4 loads the shift data again at 07H and starts the shift operation. On the other hand, the master station also loads the same information content as that in the first shift transfer, and generates transfer data and a transfer clock having the number of bits corresponding to the number of slave stations on the transmission path. Then, the same operation as in the first cycle is executed, and the instruction control is performed so that the control count value becomes 0CH in accordance with the shift transfer end timing.

When the control count value reaches 0CH, the slave station determines that the second-cycle shift transfer has been completed, and the EXOR circuit B6 compares the output of the double-read latch circuit 5 holding the first-cycle data with the output of the second-time latch circuit 5. The output of the shift register circuit 4 in which the data of the cycle is stored is compared bit by bit. As a result, the EXOR circuit B6 outputs an OFF signal when all the contents match for each bit, and outputs an ON signal when any one bit does not match.

When the control count value becomes 0DH, the decode circuit B12 outputs a latch holding pulse to the output latch circuit 7 if the read results match each other, and outputs the read result twice. When there is a mismatch, the return phase signal is turned on without outputting the latch holding pulse to the output latch circuit 7. When the return phase signal is turned on at 0DH, the master station determines that the shift transfer has failed due to a communication error, and recognizes a communication error. In this case, as will be described later in the description of the master station, the control count value is returned to 00H by a soft reset signal, and the above serial communication is executed again as a serial communication retry. If an error occurs even after the retry communication is performed a predetermined number of times, the operation of the entire device is stopped as a serial communication failure, and the processing is terminated while maintaining a predetermined state such as a serviceman call.

On the other hand, if the shift transfer is successful at 0DH,
The transfer information to the slave station is output as a slave station parallel output, and the shift transfer operation ends. Accordingly, the master station reads and compares the input shift transfer data from the slave station twice in the same manner, and updates the information content in a predetermined memory when all the data match, while reading and comparing the data twice and finds that there is no mismatch. If there is only one bit, the retry communication is similarly performed after the soft reset.

When the master station also determines that the shift transfer has succeeded, it operates the control count value to 0EH.
This time, the state of the return phase signal is detected in order to determine the presence / absence of a slave communication request signal from each slave station. This state of 0EH is maintained until at least one slave station or master station issues a communication request. If there is a communication request, the control counter value is immediately set to 00H, and the serial communication is again executed. That is, the master station determines that the control counter value is 0DH.
The return phase signal at the time is used as a transfer error judgment,
The return phase signal at the time of 0EH is determined as a slave station communication request.

As described above, the return phase signal output is read by the master station while distinguishing its meaning according to the control count value. Therefore, the master station is configured as necessary so that it can be determined with various contents according to the control count value, and by devising the operation timing of the control count value, it is possible to classify the return signal having various meanings. .

On the other hand, when the control count value becomes 0EH, the slave station outputs the output state of the EXOR circuit A3 as a return phase signal by the decoding circuit B12. While this control count value is 0EH, the presence or absence of a slave communication request is transmitted.
As described above, with respect to the latch contents of the input latch circuit 2 for latching and holding the shift-transferred slave parallel input information,
As soon as even one bit of the current slave station parallel information content accessed to the input terminal of the input latch circuit 2 is updated, it is output as a slave station communication request for requesting the master station to perform information exchange. By this signal, the same operation as the bidirectional serial communication configuration can be originally obtained even in the unidirectional serial communication configuration from the master station.

Next, the control processing executed by the master station will be described in more detail with reference to FIGS.

FIG. 8 is a block diagram showing an example of an electronic apparatus in which some of the optional stations installed from the electronic apparatus of FIG. 6 are omitted. The electric unit (slave station) referred to as an option here is not limited to an option installed by a user.
It also includes electrical units installed during factory assembly.

In FIG. 6, the master station executes control based on the slave station arrangement order allocated in the order shown in FIG. In addition, the slave station arrangement order of the basic transmission line is determined according to the configuration of the electronic device to be used. However, if the slave station arrangement order is changed due to a specification change or the like, the slave station arrangement order becomes the basic. Change the slave station order.

In FIGS. 6 and 8, a ring-shaped transmission line including the slave stations s1 to s12 is provided starting from the master station m.

FIGS. 9 and 10 are diagrams showing an example of a memory map used when the present serial communication device performs information exchange, and shows a memory map of a storage memory (not shown) provided only in the main station. It shows the transition of. That is,
The slave parallel output information (a) and the slave parallel input information (b) in FIG. 9 are obtained by mapping the slave array order in the basic transmission line in FIG. 6, and the slave parallel output information (a) in FIG. ) And the slave station parallel input information (b) are obtained by mapping the current order of slave stations in the transmission path of FIG. 8 by initialization communication described later, and show a state in which the memory map is reset. is there.

Then, based on the arrangement order of the slave stations in the reset memory map of FIG. 10, information exchange with each slave station is performed by normal communication, and the data content is updated. On the other hand, an electronic device to which the present serial communication device is applied executes device control by reading and writing the present memory map.

In FIG. 10, the bits represented by "X" and "Z" indicate information contents updated with the execution of normal communication.

FIG. 11 is a flowchart showing a procedure of a serial communication process executed by the present serial communication device.
FIG. 12 is a flowchart showing a detailed procedure of the initialization communication process in FIG. 13 and FIG.
12 is a flowchart showing a detailed procedure of a normal communication process in FIG.

In the case of normal communication, a so-called double feed and double reading mode is executed in which the shift transfer for executing the serial communication operation is performed twice and the information contents of the first and second rounds are compared. However, in the case of the initialization communication, the communication operation is controlled to be forcibly terminated by performing a soft reset at the stage where the shift transfer for executing the serial communication operation has been completed. This is because the reset of the memory map is finished as soon as possible, and the system can be shifted to the normal communication. With this process,
The entire electronic device can be started up as quickly as possible. Therefore, in the case of initialization communication, resetting of the memory map by shift transfer is rounded up by one round of shift transfer, and the process proceeds to the next normal communication as one serial communication.

Hereinafter, the control processing executed by the present serial communication device centering on the main station will be described in detail with reference to FIGS.

When the power is turned on and the CPU (not shown) is reset, the initialization setting processing of the memory (not shown) of the CPU is executed, and the memory portion of the main station is connected to the basic transmission line. When the arrangement order of all possible slave stations is mapped, the control program of the electronic device by the CPU operation is started, and at the same time, the serial communication processing (FIG. 11) which is the control processing of the master station is started. Before performing information exchange with each slave station, the master station performs communication to determine the sequence of slave stations existing in the current transmission path, that is, initialization communication, before performing communication called normal communication. . At this time, the memory state of the master station is a memory map shown in FIG.

When the serial communication process is started, first,
In step S101, the retry counter value is checked to determine whether the value is equal to or less than a predetermined value. At first, since the retry counter value is zero, the process proceeds to step S102.

In step S102, it is determined whether or not the memory map reset flag is set ("1"). If the flag is not set, the flow advances to step S103 to reset the memory map in the initialization communication process. Execute.

In the initialization communication process shown in FIG.
In step S121, the idle transfer of one transfer clock, which is the operation of making the input selector circuit 1 of the slave station of FIG. 7 access the identifier information of the slave station, is executed. (If the idle transfer of the transfer clock is not performed, the input selector circuit 1 of the slave station accesses the information content of the slave station.) Next, in step S122, the memory map is used for resetting. The communication abnormality flag for registering the abnormality of the memory pointer and the communication result is initialized, and the execution of the initialization communication after step S123 is started.

In step S123, the memory pointer is incremented to 01H, and in step S124, the value obtained by adding the top address of the memory map of the slave array output information in which the slave array order is registered in advance: MTO and the memory pointer value It is determined whether or not the memory address indicated by matches the final value address: MTE in the memory map of the slave parallel output information in which the slave array order is registered in advance.

If they match in step S124, it means that the scanning of the memory map has been completed. Now, it is determined that they do not match, and the flow advances to step S125 to prepare for output of transfer data to be shifted and transferred.

In this initialization communication processing, the contents of all zeros are shift-transferred. However, the present invention is not limited to this, and shifts other than all zeros may be shift-transferred depending on the use of the serial communication device.

Next, in steps S126 to S128, 4-bit shift transfer is executed in accordance with the circuit configuration of the slave station. That is, 1-bit shift-out signal and 1-bit
The output transfer clock is output, and the clock counter is incremented (step S126), and a 1-bit shift-in signal is input (step S127).
It is determined whether or not the bit-wise shift transfer has been completed (step S128), and if not, the processes of steps S126 and S127 are repeated until the transfer is completed.

When the shift transfer of 4 bits is completed, the process shifts to step S129 to process the identifier information from the first slave station returned to the master station by the shift transfer. That is, the contents of the memory address indicated by the sum of the start value address: MTO and the memory pointer value of the memory map, which is the slave parallel output information of the base memory map, are accessed, and the upper 4 bits are accessed. . Then, the contents of the upper 4 bits are compared with the identifier information of the bit configuration of the 4-bit configuration when it is determined in step S128 that the input is completed (step S1).
30) If they match, it is determined that there is a slave whose identifier information is registered in the slave parallel output information of the basic memory map, and the process returns to step S123. Is determined. On the other hand, if they do not match, it is determined that there is no slave station of the identifier information registered in the slave station parallel output information of the basic memory map, and in step S131, the identifier information indicated by the upper four bits of the slave station is determined. The content is cleared to all zeros (00H) meaning "no slave station" and re-registered, and in the following step S132, the memory pointer is incremented and the registration located next to the slave parallel output information in the basic memory map is performed. The slave station of the identified identifier information is designated, and the process returns to the step S129 to determine the existence of the corresponding slave station. In other words, the memory area of the non-existing slave station is set to 00H to cancel the registration, and the existing memory area of the slave station retains the already registered identifier information, so that the current slave station arrangement order is reset. You.

By repeating the above processing and resetting the slave station arrangement order of the basic memory map, step S1
At 24, since the scan address reaches the address value MTE at which it is determined that the scan of the registered slave station should be terminated, the process moves to step S133, and the master station counts the total number of transfer clocks actually shifted and output during execution of the initialization communication. Divides the count value of the clock number counter provided by 4 bits, which is the number of bits constituting one slave station, to calculate the total number of slave stations present on the current transmission line, and determines the slave station determined to be present on the reset memory map. By comparing with the total number, self-diagnosis is performed to determine whether or not the slave station arrangement order reset by the initialization communication has been normally performed.

If it is determined in step S133 that they match,
It is determined that the reset has been normally performed, and the process proceeds to step S134. After the reset flag is set, the initialization communication process ends.

On the other hand, if there is a mismatch in step S133, it is determined that the reset is not normal, and the reset flag is reset, the process proceeds to step S135, the retry counter is incremented and the reset is performed once. The initialization communication processing ends.

Returning to FIG. 11, when the initialization communication processing is completed, the serial communication processing is temporarily terminated.

When the serial communication process is started again, the retry counter value is checked in step S101, and it is determined in step S102 whether the memory map has been reset. If so, the process proceeds to step S105, and the process proceeds to a normal communication execution operation described below. If the reset has failed, the process returns to step S103 to retry the initialization communication process.

If the initialization communication process succeeds even once, the process proceeds to normal communication after step S105. If the initialization communication process continues to fail, the retry counter value is incremented in step S135 in FIG. The count value exceeds a predetermined value, and step S in FIG.
At 101, it is determined that the communication cannot be performed, and step S104
Then, the communication failure processing is executed. In this communication failure process, the operation of the entire electronic device is stopped as a device failure, and a serviceman's response is required.

The master station control of the initialization communication has been described above. Here, a specific initialization communication operation will be briefly described with reference to FIGS.

The resetting of the memory map by the initialization serial communication is performed based on the basic memory map of the slave station arrangement order shown in FIG. The master station first determines the lower 4 levels of the slave station parallel output information in the memory map in the order of the base station arrangement order.
The information content of the bit string is shifted and transferred to each slave station to initialize the slave station parallel output state.

In this serial communication apparatus, all zeros are set to initialize the slave station parallel state.
The present invention is not particularly limited to this, and the contents of the initialization information may be set in advance when a basic memory map in the slave station arrangement order is created.

Then, as described above, the master station outputs a soft reset signal to each slave station, and operates the transfer clock to shift the slave station identifier input contents to the shift register circuit 4.
To load. Thereafter, the slave parallel output information for initializing the slave parallel output state is shifted and transferred. As a result, the slave station parallel output information contents to be initialized are output to the parallel output terminals to the slave stations, and the identifier information contents are sequentially returned to the master station in the slave station arrangement order of the transmission path. The master station divides this identifier information content every 4 bits, and resets the current slave station sequence order of the transmission line while comparing it with the order of the identifier information content registered in the basic slave station sequence memory map.

Next, the rules for the identifier information will be briefly described.

In the identifier information, an electric unit required for the configuration of the electronic device is referred to as a main unit, a fixed value is allocated, and an electric unit capable of performing an operation without the configuration of the electronic device is referred to as an optional unit. And assign values in order. However, in the case of this optional unit, it is not simply allocated in order from 1. That is,
Since the main unit always exists in the apparatus, it is sufficient that the main unit can be confirmed to be at a position in the transmission line order set in advance. Therefore, the identifier information can be set with a fixed value. Since the optional units always exist between the main units whose position order has already been determined, the optional units are numbered sequentially based on one main unit. Therefore, the identifier information of the option unit has no duplicate identifier information content between one main unit, but it is allowed to be duplicated between different sets of main units, and the identification judgment can be made. . In FIG.
An example of the assignment of the identifier information is shown in the upper 4 bits of the slave station parallel output information.

The resetting process of the memory map will be described by taking the transmission line shown in FIG. 8 as an example based on the definition of the identifier information according to such a rule. Note that this memory setting is performed in the same manner as a general CPU memory operation, and will be described below as an example, but is not particularly limited to this.

As means for operating the memory, there are a head position address of the memory (indicated by MTO in FIG. 9) and a memory pointer counter, and the contents of the memory indicated by the head position address of the memory are used as a reference counter. If the identifier information of the shifted unit is the main unit,
The reference counter value of the memory content indicated by the head position address of the memory is incremented. In the case of the optional unit, the memory pointer counter value is incremented.

First, checker identifier information (main unit) is shift-transferred to the master station. In this case, since the main unit is used, the reference counter value is incremented to 01H. On the other hand, the memory pointer counter value is not incremented and remains at 00H. Then, scanning is performed from the start position address of the base memory map, and an address position in which the identifier information content of the main unit located in the order indicated by the reference counter value is registered is determined from the base memory map ( In this case, since it is 01H, the checker which is the main body unit located first is calculated), and the reference counter address is set at that address position.

Next, the upper four bits of the memory at the address indicated by the result of adding the reference counter value and the memory pointer counter value
The bits are compared with the shift-transferred identifier information contents. In this case, the first main unit 0
The contents of the memory (the checker in Fig. 9)
Matches with the transferred identifier information content of the checker. If they match, it is determined that there is a corresponding slave station, and the upper 4 bits set in the basic memory map are left as they are, and a state is set where there is a slave station.

Next, the sorter identifier information (option unit) is shifted and transferred. In this case, since this is an optional unit, the reference counter value is not incremented and remains at 01H, and the memory pointer counter value is incremented to 01H. As a result, the first memory (the sorter in FIG. 9) after the main unit, which is located first, matches the identifier information of the transferred sorter for comparison. Therefore, it is similarly processed that there is a slave station.

The identifier information to be shifted next is shown in FIG.
Higher pressure red (optional unit). In this case, since it is not the main unit, the memory pointer counter value is incremented to 02H. On the other hand, the reference counter value remains at 01H. Therefore, the memory located second after the main unit located first (switched back in FIG. 9) is compared with the transferred identifier information of the sorter. as a result,
If there is no match, first, the upper 4 bits of the switchback memory, which is the memory located second after the main unit located first, are reset to all zeros, and there is no corresponding slave station.

Next, the value of the memory pointer counter is incremented again, and 03H is compared with the content located in the next memory map. That is, it is compared with the memory located third after the main unit located first. Similarly, in this case, it is determined that they do not match,
The non-matching memory is set as no slave station and the comparison is continued.

In this case, when the memory pointer counter value is 04H, that is, when the memory pointer counter value is compared with the fourth memory located after the first main unit, it is determined that the slave station of this memory is present. Set.

Next, as shown in FIG. 8, the identifier information (main unit) of the high voltage 1 is shifted and transferred. When the identifier information content of the main unit is received, first, starting from the memory indicated by the reference counter value and the memory pointer counter value, the optional counter of the optional unit registered between the main units indicated by the incremented value of the reference counter value is started. Set all memory contents to no slave station. In this case, high-pressure yellow (optional unit) corresponds to this. Next, based on the incremented reference counter value, the reset of the basic memory map is continued as described above. When the reference counter is incremented, the memory pointer counter value is cleared and returned to 00H.

By executing the above operation for all the basic memory maps, the resetting of the memory is performed as shown in FIG.
This is performed as shown in FIG. In other words, this memory operation is basically performed in the form of the optional unit located at the position after the main unit located at the position, and the memory contents are set.

Hereinafter, steps S105 to S11 in FIG.
The normal communication indicated by No. 2 will be described.

In the figure, when the above-described initialization communication processing is executed in step S103, a memory map reset flag is set. As a result, the memory map is shown in FIG.
As shown in the upper four bits of the slave station parallel output information in FIG. 7A, the slave station arrangement order in the basic memory map is reset to the slave station arrangement order of the slave stations existing on the current transmission path. Normal communication is executed based on the state of the slave station arrangement order.

When the process proceeds from step S102 to step S105, the retry flag is checked to determine whether or not there is retry communication. In the retry communication, similarly to the processing described in the initialization communication, when one serial communication fails, the retry counter is incremented, and when the count value is within a predetermined value, the retry communication is performed. And usually also exists in communication control.

Note that the configuration of the retry communication means uses the same means configuration since the initialization communication and the normal communication, which are the two types of communication means of the present serial communication device, do not proceed simultaneously. That is, when an error occurs in the retry communication exceeding a predetermined value, both the initialization communication and the normal communication shift from step S101 to step S104, and are processed in the communication failure processing routine. On the other hand, when the retry communication is executed, in the case of the initialization communication, as described above, the retry counter is incremented in step S135 in FIG. 12, and the process proceeds to step S102 in FIG. 11 while the reset flag is reset. Then, the retry communication is executed because the reset flag is not set. In the case of normal communication, the retry flag is reset in step S112 after the normal communication is executed.
05, it is determined that retry communication is to be executed. That is, the retry communication control for the initialization communication and the normal communication is controlled separately, but the flags and counters necessary for the error processing routine and processing are shared.

When the resetting of the memory map is completed, it is determined in step S105 that there is no retry communication.
At 106 and S107, a request for execution of normal communication is awaited by either the request flag at the master station or the communication request signal at the slave station. When the initialization communication has been completed, since both the phase control counter 11 of the slave station and the control count value of the master station phase control counting means are set to 00H by the communication software reset, the slave station communication request signal in step S107 is set. Is invalid. Therefore, although not particularly shown, the master station sets the master station communication request flag immediately after finishing the initialization communication, and instructs execution of the normal communication in step S106. On the other hand, if the normal communication has been performed even once, the control count value is 0EH, and as described above, the system waits for the execution instruction of the normal communication. That is, the process proceeds from step S107 to step S112, resets the processing signals for retries and failures, temporarily ends the serial communication processing, and again executes steps S105 to S107.
And waits for the execution of the normal communication to detect the execution instruction. Then, when an instruction to execute normal communication is received, step S
The routine proceeds to 108, where normal communication processing is executed.

In the normal communication processing shown in FIG. 13, first, in step S141, communication software reset is executed to synchronize the execution of communication.

Next, in step S142, a flag for executing communication and each counter value are reset.

In step S143, the memory pointer for memory operation is incremented. In steps S144 and S145, the control counter value is loaded and checked from the phase control counter of the main station, and is a predetermined value registered in advance. It is determined whether or not. In this case,
Two points are determined: 00H when the slave station input information to be shifted from the slave station is selected and 06H when the shift transfer is performed once. Further, the value of the double reading comparison result after performing the shift transfer twice is set to 0DH, and the determination is made in steps S160 and S161 in FIG. On the other hand, the validity period of the slave station communication request signal is set to 0EH. Here, although the timing determination is not particularly performed, the communication operation in the normal communication is terminated, and the next communication executable state is set to 0EH. It is controlled to be.

If it is determined in step S145 that the control counter value is the predetermined value (00H, 06H), the process proceeds to step S14.
6, while the return phase signal is checked on, while the control counter value is not the predetermined value in step S145, the process proceeds to step S147 in FIG. 14, where the return phase signal is checked off.

Then, it is turned on when the return phase signal is checked on in step S146, or in step S14.
If it is off when the return phase signal is off-checked in step 7, it is determined that the phase timing is normally synchronized, and the routine goes to step S150. On the other hand, step S146
If it is off when the return phase signal is on-checked in step S147, or if it is on when the return phase signal is off-checked in step S147, it is determined that the phase timing is out of synchronization, and a communication error is detected in step S148 in FIG. The phase error bit of the flag is set, and communication software reset is executed in step S149 to cancel the currently executed normal communication. In this case, step S109 in FIG.
In step S110, a communication error flag analysis is performed. In step S111, a retry flag is set to instruct retry communication.
Further, the retry counter is incremented.

The execution of the communication error flag analysis routine is made up of a plurality of flags corresponding to various types of abnormal conditions, not shown. Then, when a flag indicating that the content of the abnormal state is light is set (the content of the abnormal state referred to here is one that has been identified and set in advance as a minor category and a severe category),
The retry counter value is incremented (+1) in the next step S111 to instruct execution of retry communication. On the other hand, when the flag indicating that the content of the abnormal state is heavy is set, the retry counter value is classified in advance so as to be directly set to a predetermined value causing an error on the spot. In this case, the retry communication is not executed according to the determination in step S101 after the serial communication processing is completed, and the process immediately proceeds from step S101 to step S104 to perform the communication operation in the communication failure processing routine. And the operation of the electronic device is stopped.

If it is determined in step S146 in FIG. 13 and step S147 in FIG. 14 that the state of the return phase signal is normal, the flow shifts to step S150 to start execution of normal communication.

First, it is determined whether or not the sum of the memory pointer value and the head address: MTO of the reset memory map indicated by the slave station parallel output information is the final address of the memory map: MTE. If they are equal, it means that one round of data to be shifted and transferred has been scanned, so the flow shifts to step S160 to enter post-processing after execution of normal communication. On the other hand, if they are not equal, that is, if the shift transfer is not completed, step S15
1 and S152, the upper 4 bits of the memory content indicated by the address of the sum of the memory pointer value and the start value address of the memory map: MTO are checked.

In step S152, the upper 4 bits are set to 00.
If it is H, it is determined that there is no registered slave station by resetting,
Returning to step S143 again, the memory pointer value is incremented, and the process shifts to execution of shift transfer in the next slave station in the memory map. Then, when it reaches step S152 again, it similarly checks the upper 4 bits of the memory contents. At this time, if the upper 4 bits are 00H, the same operation is repeated. If the upper 4 bits are not 00H, the lower 4 bits of the memory contents are accessed in step S153, and 1-bit shift for shift transfer is executed in step S154. . Further, in step S155, it is determined whether or not the clock number counter means of the master station has a predetermined value, and control of the control count values of the phase control counters of the master station and the slave stations is executed.

Then, in step S157, a 1-bit return signal by shift transfer is input, and in step S158, it is determined whether or not the shift transfer for 4 bits corresponding to one slave station has been completed. If it is not determined in step S158, the process returns to step S154 to repeat the same operation.
In step 159, the 4-bit data is stored in the slave station parallel input information of the memory map shown in FIG. More specifically, the start value address of the memory map of the memory pointer value and the slave station parallel input information: MTI
Is stored in the lower 4 bits of the memory content indicated by the added value address to update the information content.

Then, in order to repeat the above operation to execute the shift transfer of the next slave station, step S14 is performed again.
Return to 3.

As described above, when it is determined in step S150 that the data scan of the slave station to be shifted and transferred has completed one cycle, the process proceeds to step S160 in FIG. 14, and the control count value of the phase control counter of the master station is set to 0DH.
Then, the result of reading twice from each slave station is determined. If the return phase signal is on in step S161, it means that there is an error in the double reading comparison in any of the slave stations, and the process proceeds to step S163, where the double reading comparison error bit of the communication abnormality flag is set. Is set in step S1
At 64, a communication software reset for executing retry communication is executed. Thereafter, step S109 in FIG.
Then, as described above, the process proceeds from step S109 to step S110, where the execution request processing of the retry communication is performed.

On the other hand, if the return signal is not turned on in step S161, it means that there is no error in the double reading comparison in all the slave stations, so that step S1 is executed.
In step 62, the control count value of the phase control counter of the master station is set to 0EH, the communication request signal from each slave station is set to be valid, and it is assumed that normal communication has been safely completed, and the process returns to step S109 in FIG. And the normal abnormality flag is 0
At 0H, the retry flag and the retry counter are reset in step S112 to complete one normal communication.
Thus, in the next communication execution, in steps S106 and S107, the communication standby state is continued until there is a communication request from the master station or the slave station, and communication is basically not performed unless there is a request.

The above is the master station control of the normal communication. This normal communication is performed after the arrangement order of the slave stations existing on the current transmission path can be reset by executing the initialization communication. When the arrangement order of the slave stations existing on the set transmission line changes, it is necessary to immediately execute the initialization communication to execute the resetting of the memory.

Although a part for generating a master station communication request is not particularly shown, the CPU controlling the electronic device main body sets a master station communication request flag for determining that each slave station needs to update information in each control task. Set to. Therefore, the master station checks the master station communication request flag in the part for controlling the normal communication of the serial communication processing (step S106 in FIG. 11) and determines whether or not the normal communication is to be executed.

As described above, the execution of the normal communication sequentially shifts and transfers the lower 4 bit information contents validated by the slave parallel output information of the reset memory map, and sequentially shifts the returned information contents to the slave station. Only the lower 4 bits of the parallel input information need be stored. That is, once the memory is reset, the master station can exchange information with each slave station by simple control such as simply transferring the contents of the memory. Furthermore, the time required to execute the normal communication can be processed in a minimum time because only the number of data bits for information exchange needs to be shifted and transferred.

[0116]

However, the conventional serial communication device has the following problems.

That is, in this serial communication device, the plurality of slave stations existing on the transmission path are constituted by a slave station for a main unit that cannot be detached from the electronic device main body and a slave station for an optional unit that can be detached from the electronic device main body. Some optional units are removable at the user level and others are not.

Optional units that can be attached and detached at the user level are described in the instruction manual of the electronic equipment so that the power is always turned off when the attachment / detachment is executed, and the user is thoroughly instructed. In some cases, when stopping the use of a user-level detachable option unit that has been used in the past, the user can simply remove the option unit without turning off the power of the electronic device itself, and continue to use the electronic device. The use of is very rare.

Also, in particular, a paper jam phenomenon (generally referred to as “jam”, hereinafter simply referred to as “jam”) that occurs during paper conveyance as in an electrophotographic apparatus, etc. Occurs, depending on the device, it is necessary to remove the optional unit detachable at the user level from the device for the jam processing and execute the jam processing. As a result, in some rare cases, the user disconnects the option unit without turning off the power of the apparatus main body, forgets to connect the option unit after the jam has been cleared, and continues to use the device as it is.

As described above, this serial communication device resets the arrangement order of the slave stations existing on the transmission line in the memory by the initialization communication, and shift-transfers only the information contents corresponding to the registered slave stations. Because information is shifted and transferred by normal communication, and the master station exchanges information with multiple slave stations, remove the option unit without turning off the power of the electronic device itself and continue using the electronic device If there is, the arrangement order of the slave stations existing on the transmission path recognized by the initialization communication will be out of order. In other words, during the normal communication after the initialization communication for resetting the arrangement order of the slave stations present on the transmission line to the memory, the communication execution is performed with the shift transfer information configured based on the determined arrangement order of the slave stations. Therefore, when one slave station connection is actually lost, a deviation occurs between the slave station array actually connected to the transmission path and the slave station array registered in the memory of the master station.

Therefore, when the power of the electronic device is turned off and the optional unit is removed, the arrangement order of the slave stations is updated again by the initialization communication executed after the power is turned on, regardless of whether the optional unit is connected or not. So there is no problem, but if one slave station is removed and the electronic device is used continuously without turning off the power of the electronic device body,
The arrangement order of the slaves connected to the actual transmission path and the arrangement order of the slaves held in the memory of the master determined in the previous initialization communication may be out of order, and the information contents originally intended to be transmitted to a certain slave may be different. Since the information exchange by the normal communication is continued and executed without noticing the erroneous transmission such as erroneous transmission to the slave station, the serial communication itself cannot be established.

The present invention has been made in view of this point, and even if the optional unit installed in the electronic device is removed without turning off the power of the electronic device main body, the serial communication after that is performed. It is an object of the present invention to provide a serial communication device, a serial communication method, and a storage medium that can perform the normal operation.

[0123]

To achieve the above object, a serial communication apparatus according to the present invention comprises a transmission line connecting one master station and a plurality of slave stations in a loop, and a transmission line connecting the plurality of slave stations. Storage means for storing the arrangement order of the slave stations, based on the identifier information that each of the slave stations serially returns via the transmission path in response to the request of the master station, the arrangement of the slave stations currently arranged on the transmission path. Initialization communication means for resetting the order in the storage means, and, based on the arrangement order of the slave stations reset by the initialization communication means, information is serially transmitted from the master station to the slave stations via the transmission path. A normal communication unit for transferring and serially transferring information from each of the slave stations to the master station, and storing the information serially transferred to the master station in a position corresponding to the slave station in the storage unit; Among a plurality of slave stations existing on the transmission line classified into a station and a second slave station, at least one or more of a plurality of preset slave stations, among information transferred to the master station, are set for the first slave station. Is set to a first fixed value, and for the second slave station, the bit is set to the first fixed value.
Setting means for setting a second fixed value having a state different from the fixed value of the fixed value, a state of the fixed value set for the bit in the information transferred to the master station stored in the storage means, and an array thereof. A determination unit that determines whether or not there is a shift between the two by comparing the order, and as a result of the determination, when there is a shift, the processing by the initialization communication unit is executed again. And control means for controlling.

[0124] Preferably, the number of the first slave stations is selected to be extremely small as compared with the number of the second slave stations.

Preferably, the judging means compares the information, in which the first fixed value is set, in the information transferred to the master station stored in the storage means with the arrangement order thereof. It is characterized by the following.

Further, preferably, the determination means performs the shift determination after the processing by the normal communication means has been completed for all of the plurality of slave stations.

[0127] More preferably, the determination means performs the deviation determination each time the processing by the normal communication means ends for each of the plurality of slave stations.

In order to achieve the above object, a serial communication method of the present invention stores a transmission path connecting one master station and a plurality of slave stations in a loop, and an arrangement order of the plurality of slave stations on the transmission path. A serial communication method in an electronic device comprising a storage unit, wherein each of the slave stations responds to a request from the master station based on identifier information serially returned via the transmission path. The initialization communication step of resetting the arrangement order of the slave stations that have been set in the storage means, and based on the arrangement order of the slave stations reset by the initialization communication step, via the transmission path, from the master station. While serially transferring information to each slave station, serially transferring information from each slave station to the master station,
A normal communication step of storing information serially transferred to the master station at a position corresponding to the slave station in the storage means; and a plurality of slave stations existing on the transmission line classified into a first slave station and a second slave station. Of the information transferred to the master station, at least one or more bits set in advance are set to a first fixed value for the first slave station. Setting the bit to a second fixed value having a state different from the first fixed value; and setting the bit in the information stored in the storage means and transferred to the master station. A determination step of determining whether or not there is a difference between the two by comparing the state of the fixed value and the arrangement order thereof, and as a result of the determination, when there is a difference, the initialization communication A system that controls the process to be executed again Characterized by a step.

Preferably, the number of the first slave stations is selected to be extremely small as compared with the number of the second slave stations.

Preferably, in the determining step, the information transferred to the master station stored in the storage means includes:
The information in which the first fixed value is set is compared with the arrangement order thereof.

More preferably, in the determining step,
The shift determination is performed after the processing in the normal communication step is completed for all of the plurality of slave stations.

[0132] More preferably, in the determination step, a shift determination is performed each time the processing in the normal communication step ends for each of the plurality of slave stations.

In order to achieve the above object, a storage medium of the present invention is a storage medium for storing a transmission line for connecting one master station and a plurality of slave stations in a loop, and an arrangement order of the plurality of slave stations on the transmission line. And a storage medium storing a program that can be implemented by a computer, including a serial communication module in an electronic device provided with the means. An initialization communication module for resetting the arrangement order of the slave stations currently arranged on the transmission path in the storage unit based on the identifier information serially returned via the communication station; and a slave station reset by the initialization communication module. Based on the arrangement order, via the transmission path, while serially transferring information from the master station to each of the slave stations, from each of the slave stations The information to the serial master station and serial transfer,
A normal communication module for storing information serially transferred to the master station at a position corresponding to the slave station in the storage means;
Of the plurality of slave stations existing on the transmission path classified into the first slave station and the second slave station, for the first slave station,
In the information transferred to the master station, at least one bit set in advance is set to a first fixed value;
A setting module for setting the bit to a second fixed value having a state different from the first fixed value, and the information stored in the storage means and transferred to the master station. A determination module that determines whether or not there is a shift between the two by comparing the state of the fixed value set in the bit with the arrangement order thereof, and a result of the determination,
And a control module for controlling the initialization communication module to execute the processing again when a deviation occurs.

Preferably, the number of the first slave stations is selected to be extremely small as compared with the number of the second slave stations.

Preferably, in the determination module, the information in which the first fixed value is set in the information transferred to the master station stored in the storage means is compared with the arrangement order thereof. It is characterized by the following.

[0136] More preferably, in the determination module, the shift determination is performed after the processing by the normal communication module is completed for all of the plurality of slave stations.

[0137] More preferably, in the determination module, each time the processing by the normal communication module is completed for each of the plurality of slave stations, a shift determination is performed.

[0138]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an electronic apparatus to which the serial communication device according to the first embodiment of the present invention is applied, and corresponds to FIG.

In FIG. 8, a plurality of parallel input terminals of all slave stations connected to the transmission line are configured so that all bits are used as return information to the master station. However, in this embodiment, As shown in FIG. 1, among a plurality of parallel input terminals of all slave stations connected to the transmission line, bit 2
Are fixed to information contents of predetermined bits set in advance. The predetermined bits are not particularly limited, as long as one bit of one slave station is allocated. In this embodiment, only the slave station s2 is set to the first fixed value state (high level), and the other predetermined stations are set to the second fixed value state (low level). And are mixed in the transmission line.

The slave station configuration on this transmission path is merely the simplest one in order to explain the gist of the present invention as easily as possible. A multi-bit configuration may be used, and the first fixed value state and the second fixed value state may be of any type as long as they can be distinguished, and may be coded, for example. Further, only one slave station need not be in the first fixed value state, and the first fixed value state and the second fixed value state may be mixed in an appropriate number in the transmission path. It goes without saying that it is good.

In the present embodiment, as shown in FIG. 1, only slave station s2 is set to the high level, which is the first fixed value state. Therefore, when normal communication processing is executed, information returned to the master station is obtained. 9 (b) and 10 for storing contents
In the slave-side parallel input information of the memory shown in (b), bit 2 of the lower 4 bits becomes a predetermined bit. 4 bit bit 2 "
1 ”is input and the other lower 4 bits, bit 2
Becomes “0”. Then, when the arrangement order of the slave stations reset by the initialization communication processing becomes out of order, bit 2 of the lower 4 bits of this manual feed unit becomes “0”, and the slave station that should become “0” changes “1”. Will show. Therefore, by executing the control shown in FIG. 2, it is possible to realize the arrangement order deviation correction self-diagnosis processing which is a feature of the present invention.

Hereinafter, control processing executed by the serial communication device according to the present embodiment will be described with reference to FIG. 2 and FIG.

Although the present invention is such that the self-diagnosis of the arrangement order deviation correction can be executed based on the above-mentioned conventional serial communication device, any serial communication device capable of executing the control processing intended by the present invention is applicable. The serial communication device is not particularly limited as long as it is used. In the description of the present embodiment, description and drawings which are the same as those in the above-described conventional example will be omitted to facilitate the description.

FIGS. 2 and 3 are flow charts showing the procedure of the normal communication process which is a part of the control process executed by the CPU of the serial communication device of the present embodiment, in particular, the master station m. This corresponds to FIG.

Before describing the normal communication processing, the configuration of a program executed by the CPU of the main station will be briefly described.

This program is configured by task type parallel processing. In other words, each independent control program configures a plurality of tasks, and executes initialization settings of memory and ports by resetting the CPU after turning on the power,
A program called a monitor program for controlling the start operation of each task is executed.

Each task is processed in parallel and executed in real time. The normal communication task (processing) in the serial communication task shown in FIG. 2 and FIG. 3 is also started by the monitor program, and returns to the monitor program once after executing a predetermined processing operation. Is made. Similarly, another task executes a predetermined processing operation and temporarily stops, but is started again to execute a subsequent control operation. As a result, the respective tasks perform parallel processing by sequentially executing predetermined processing operations, and the operation of the entire apparatus is controlled.

The cooperation between the tasks is performed by a memory accessed by each task.

Hereinafter, the present embodiment will be described.
The programs described below are tasks that are similarly processed in parallel, but are described as one connected program process for ease of description.

When the serial communication task (processing) described with reference to FIG. 11 is started by the monitor program, as described in the conventional example, in step S103, the serial communication task (processing) is connected to the current communication transmission line by the initialization communication processing. The memory reset of the slave station arrangement order is executed.

When the resetting of the memory is completed, the first normal communication after the initialization communication processing is performed in step S10.
6 or S107 is shifted to normal communication processing in step S108.

When the processing shifts to the normal communication processing, as described in the conventional example, the shift transfer control is sequentially performed, and the parallel input information from all the slave stations existing on the transmission path is stored in the memory. If it is determined in step S150 that the shift transfer operation has been completed, the process proceeds to step S1 in FIG. 3, and a predetermined bit (bit 2 in the present embodiment) that is set in advance
Performs a control for recognizing the arrangement order of the slave stations set in the first fixed value state, storing the arrangement order, and recognizing the basic arrangement order of the slave stations. Thus, in the first normal communication after the initialization communication, the arrangement order of the basic slave stations is recognized, and the arrangement order of the recognized basic slave stations is monitored for each subsequent normal communication. The self-diagnosis of the sequence order deviation correction, which is the feature of the above, is performed.

When the parallel input information from all slave stations is stored in the memory in the first normal communication after the initialization communication, the state of bit 2, which is a predetermined bit stored in the memory, is changed by the loop of steps S1 to S4. , "1" (ON state), the order of arrangement of slave stations is scanned and searched. In this embodiment, since only one slave station is "1" (on state), if a slave station whose bit 2 can be determined to be on is found, the scan search can be terminated. If there are a plurality of slave stations that can be determined, a scan search of bit 2 of all slave stations existing in the memory is executed.

If bit 2 is determined to be on in step S3, the order flag is checked in step S5.
If reset, it means that the communication is the first normal communication after the initialization communication, and the process proceeds to step S6, where the arrangement order of the slave stations is stored and held in the counter B (not shown), and the basic arrangement of the slave stations is performed. Since the order is recognized, the order flag is set, and post-processing of the normal communication after step S160 is executed as described in the conventional example.

As described above, the process of scanning and searching the information content stored in the memory and storing and holding the sequence number of the corresponding slave station in the counter B is the predetermined state search and storage process.

While the order flag is set, the arrangement order of the slave stations stored in the counter B is maintained, and as will be described below, the arrangement order of the slave stations detected each time normal communication is executed. Is compared to

Next, when the execution of the first normal communication after the initialization communication is completed, and the subsequent normal communication is executed, the information content stored in the memory is updated, and the process similarly proceeds to step S1. Come. Using the scan search routine (steps S2 to S4) of the predetermined state search and storage processing, a signal state determination processing for determining the arrangement order of the slave stations whose predetermined bits are turned on in the updated information content is executed. I do.

In this embodiment, the scan search routine of the predetermined state search and storage processing is used, but the signal state determination processing may be independently provided as in a second embodiment described later.

As a result of the execution of the signal state determination processing, the order flag is determined in step S5, and the process proceeds to step S7. In step S7, a slave station order determination process for comparing the array order of the slave stations stored in the counter B with the array order of the slave stations whose predetermined bits obtained in the current shift transfer are turned on is executed. Is the same as in the conventional example, step S1
Post-processing of normal communication after 60 is executed. That is, it is determined that there is no deviation in the arrangement order of the slave stations existing on the transmission path.

On the other hand, if it is determined that they do not match in step S7, the reset flag in the memory map is reset in order to execute the initialization communication again in step S8. The flag is also reset. Then, the process proceeds from step S8 to step S164, where the communication software reset is executed as described in the conventional example, and processing is performed so that the arrangement order of the slave stations connected to the transmission path is set again by executing the serial communication processing. .

As described above, according to the present embodiment, the arrangement order of the base stations is recognized and stored in the predetermined state search and storage processing, and the signal state determination processing is performed for each subsequent communication. Check the arrangement order of the slave stations, and in the corresponding slave station order determination process, confirm the deviation of the arrangement order of the base slave stations,
As soon as it is determined that there is a deviation, the information exchanged by the executed communication is soft-reset, and the arrangement order deviation correction self-diagnosis processing for executing the initialization communication for re-recognizing the arrangement order of the slave stations is performed. The conventional control operation can be performed without detecting the out-of-order sequence of the slave stations existing on the transmission line while performing information exchange and without increasing the cost of the self-diagnosis function to correct the out-of-order sequence. And can be easily realized.

Next, a serial communication device according to a second embodiment of the present invention will be described.

In the serial communication device of the present embodiment, similar to the serial communication device of the first embodiment, a shift in the arrangement order of the basic slave stations is confirmed in the transmission line of the slave station configuration shown in FIG. As soon as it is determined to be off,
The information exchange performed by the executed communication is software-reset, and the arrangement order deviation correction self-diagnosis processing for executing the initialization communication for re-recognizing the arrangement order of the slave stations is performed.
In the first embodiment, after the sequence of the base stations is recognized and stored in the predetermined state search and storage process, the information content updated in the memory in the signal state determination process is scanned and searched, and the predetermined bit is turned on. In the present embodiment, the sequence of the base stations is determined in a predetermined order search and storage process. In the normal communication executed after storing and storing, the information contents from the slave stations sequentially returned are determined for each slave station by determining the state of a predetermined bit. Is determined to be on, and in any case, if the determinations are different, it is determined that there is a shift in the arrangement order of the base slaves.

For ease of explanation in the present embodiment, too, the configuration of the slave station connected to the transmission path is based on the block diagram of the slave station of the transmission path in FIG.
The same parts as those in the conventional example and the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

FIGS. 4 and 5 are flowcharts showing the procedure of the normal communication process which is a part of the control process executed by the CPU of the serial communication device of the present embodiment, particularly, the main station m.

When the serial communication task shown in FIG. 11 is started by the monitor program, as described above, in step S103, the memory reset of the sequence of the slave stations connected to the current communication transmission line by the initialization communication is executed. Is done.
When the resetting of the memory is completed, the first normal communication after the initialization communication is performed in step S108. In the normal communication at this time, as in the first embodiment, the order flag remains reset, so that steps S142 to S159 and steps S21 to S159 are performed.
As described in the conventional example, the information content returned from the slave station is stored in the memory 143, and when the end of the shift transfer is determined in step S150, the process proceeds to step S11 in FIG. This predetermined state search and storage process is performed in steps S11 to S11, as in the first embodiment.
In the loop of S14, the arrangement order of the slave stations in which the state of bit 2 which is a predetermined bit stored in the memory is "1" (on state) is scanned and searched. If it is determined in step S13 that bit 2 is on, then step S13 is executed.
In step S16, the arrangement order of the slave stations is stored and held in the counter B, and since the arrangement order of the basic slave stations is recognized, the order flag is set.
By executing the post-processing of the normal communication after 0 as described in the conventional example, the first normal normal means after the initialization communication is completed.

Next, in the predetermined state retrieval / storage processing, the counter B
The processing in the normal communication after the order flag is set based on the basic arrangement order of the slave stations stored in the base station will be described. The contents of the counter B are updated in the predetermined state search and storage process executed in the first normal communication after the initialization communication, but are not updated and stored in other cases.

In the present embodiment, for each information content returned from the slave station, the arrangement order of the slave station and the state of a predetermined bit are checked as needed, and if there is an abnormality, the subsequent communication operation is immediately canceled, and Recovery of the arrangement order of the slave stations by the arrangement order deviation correction self-diagnosis processing is executed. In the normal communication process, as described in the conventional example, return information is processed for all slave stations while return information is stored in a predetermined memory for each slave station. That is, step S1 in FIG.
One slave station is processed by one execution from 43 to step S159, and steps S143 to S1 are performed until it is determined in step S150 that the processing of all slave stations is completed.
59 is repeatedly executed. Therefore, in the present embodiment, the state of a predetermined bit is determined for each slave station.

Therefore, after step S159 is completed, the process proceeds to step S21, where it is determined that the communication is not the first normal communication after the initialization communication by judging the order flag, and then the process proceeds to step S22. Then, step S22
Then, in the pertinent station order judging process for comparing the memory pointer value of the subordinate station stored in step S159 with the memory pointer value stored in the counter B, it is determined whether or not it is the pertinent substation. Since the slave stations other than the slave stations registered in the counter B are not the corresponding slave stations, the process proceeds to step S24, and the signal state determination processing determines that the predetermined bit is off. If the slave station is registered in the counter B, the process proceeds to step S23 because it is the slave station, and it is determined in the signal state determination processing that the predetermined bit is on.

In steps S23 and S24, it is determined that the slave station whose predetermined bit is to be off is off and the slave station whose predetermined bit is to be on is on.
If there is no problem, the process returns to step S143, where the return information is similarly stored in the memory and the predetermined bit check is executed for the next slave station, and the process is repeated until all slave stations are completed.

On the other hand, steps S23 and S24
In the case where the slave whose predetermined bit is to be off is on, or when it is determined that the slave whose predetermined bit is to be on is off, it is determined that the arrangement order of the slaves in the transmission path has been out of order, Immediately, the order flag is reset in step S25, the execution of the initialization communication is instructed, and the communication software reset is executed in step S164 in FIG. 5 to temporarily end the task. In other words, if it is determined that there is an abnormality in the arrangement order of the slave stations even during normal communication, the communication is interrupted, the initialization communication is executed as soon as possible, and the arrangement order of the slave stations is set again. Can be executed.

As described above, in the present embodiment, the arrangement order of the basic slave stations whose predetermined bits are turned on in the predetermined state search and storage processing is searched from the memory and stored, and after execution of the next normal communication, The return information input in the slave station order determination process is determined for each slave station at any time to determine whether or not the slave station is the corresponding slave station, and the signal state of a predetermined bit corresponding to the result is determined by the signal state determination process. By confirming the deviation of the arrangement order, if it is determined that there is a deviation in the arrangement order of the slave stations, by immediately interrupting the communication operation and switching to the execution of the initialization communication,
Since the setting of the arrangement order of the slave stations is executed again, without increasing the cost of the self-diagnosis function for correcting the arrangement order deviation,
It can be easily configured using conventional control operations,
The reliability of information exchange in a communication mode such as the present serial communication device can be further improved.

The storage medium storing the program codes of the software for realizing the functions of the above-described embodiments is supplied to a system or an apparatus, and the computer (or CPU or MPU) of the system or the apparatus stores the program in the storage medium. It goes without saying that the object of the present invention is also achieved by reading and executing the program code.

In this case, the program code itself read from the storage medium realizes the novel function of the present invention, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM,
CD-R, magnetic tape, nonvolatile memory card, RO
M6 or the like can be used. Further, the program code may be supplied from a server computer via a communication network.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also an OS or the like running on the computer operates based on the instruction of the program code. It goes without saying that a part or all of the actual processing is performed, and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written into the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

[0179]

As described above, according to the first, sixth or eleventh aspect, of the plurality of slave stations existing on the transmission path classified into the first slave station and the second slave station, For the first slave station, at least one or more bits set in advance in the information transferred to the master station are set to a first fixed value, and for the second slave station, The bit is set to a second fixed value having a state different from the first fixed value, and the state of the fixed value set to the bit in the information transferred to the master station stored in the storage means, By comparing the arrangement order, it is determined whether or not a shift has occurred between the two. As a result of the determination, when a shift has occurred, the process by the initialization communication is executed again,
For example, even if the user disconnects one slave from the main unit without turning off the power of the electronic device for some reason and continues operation of the device itself, the serial number is not recognized even if the arrangement order of the slaves is out of order. It does not cause a malfunction by executing communication, and can immediately reset the arrangement order of the slave stations immediately and perform serial communication that does not hinder the subsequent operation of the device main body. The reliability of information exchange in the electronic device of the embodiment can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an electronic apparatus to which a serial communication device according to a first embodiment of the present invention has been applied.

FIG. 2 is a flowchart illustrating a procedure of a normal communication process which is a part of a control process executed by a CPU of a serial communication device of FIG. 1, in particular, a master station.

FIG. 3 is a flowchart showing a continuation of the normal communication process of FIG. 2;

FIG. 4 is a flowchart illustrating a procedure of a normal communication process which is a part of a control process executed by a CPU of a serial communication device, particularly, a master station according to a second embodiment of the present invention.

FIG. 5 is a flowchart showing a continuation of the normal communication process of FIG. 4;

FIG. 6 is a block diagram illustrating a schematic configuration of an electronic apparatus to which a conventional serial communication device is applied.

FIG. 7 is a block diagram showing a detailed configuration of one of the slave stations in FIG. 6;

FIG. 8 is a block diagram illustrating an example of an electronic device configured by omitting some slave stations installed as options from the electronic device of FIG. 6;

9 is a diagram illustrating an example of a memory map used when the serial communication device in FIG. 6 performs information exchange.

10 is a diagram showing a memory map after resetting the memory map of FIG. 9 by initialization communication.

FIG. 11 is a flowchart illustrating a procedure of a serial communication process executed by the serial communication device of FIG. 6;

FIG. 12 is a flowchart illustrating a detailed procedure of an initialization communication process in FIG. 11;

FIG. 13 is a flowchart showing a detailed procedure of a normal communication process in FIG. 11;

FIG. 14 is a flowchart showing a continuation of the normal communication process of FIG. 13;

[Explanation of symbols]

 Reference Signs List 1 input selector circuit 2 input latch circuit 3 EXOR circuit A 4 shift register circuit 5 double read latch circuit 6 EXOR circuit B 7 output latch circuit 8 gate circuit 9 decode circuit A 10 clock number counter circuit 11 phase control counter circuit 12 decode circuit B m master station s1 to s12 slave station

Continuation of the front page F term (reference) 5B021 AA01 BB10 CC06 5B045 BB31 BB42 HH06 JJ45 5B077 NN02 5K031 AA10 BA01 CB06 CB09 DA02 DA16 EA07 EC01 5K034 AA05 CC06 DD02 DD04 EE05 HH01 HH02HHH HMM HHH HMM HHH TT01 TT02

Claims (15)

[Claims] A transmission line for connecting one master station and a plurality of slave stations in a loop; a storage unit for storing an arrangement order of the plurality of slave stations on the transmission line; Initialization communication means for resetting the arrangement order of the slave stations currently arranged on the transmission path in the storage means based on the identifier information which each slave station serially returns via the transmission path; and Based on the arrangement order of the slave stations reset by the means, the information is serially transferred from the master station to each slave station via the transmission line, and the information is serially transferred from each slave station to the master station. Normal communication means for storing information serially transferred to the master station at a position corresponding to the slave station in the storage means; and a plurality of slave stations existing on the transmission line classified into a first slave station and a second slave station. U , For the first slave station,
In the information transferred to the master station, at least one bit set in advance is set to a first fixed value;
Setting means for setting the bit to a second fixed value having a state different from the first fixed value; and in the information transferred to the master station stored in the storage means, Determining means for comparing the state of the fixed value set in the bit with the arrangement order thereof to determine whether or not there is a deviation between the two; Control means for controlling the processing by the initialization communication means to be executed again. 2. The serial communication device according to claim 1, wherein the number of said first slave stations is selected to be extremely smaller than the number of said second slave stations. 3. The information processing apparatus according to claim 2, wherein the determination unit compares the information, in which the first fixed value is set, in the information transferred to the master station stored in the storage unit with an arrangement order thereof. The serial communication device according to claim 2, wherein 4. The apparatus according to claim 1, wherein said determination means performs a shift determination after the processing by said normal communication means has been completed once for all of said plurality of slave stations.
The serial communication device according to any one of the above. 5. The apparatus according to claim 1, wherein the determination unit performs a shift determination each time the processing by the normal communication unit ends for each of the plurality of slave stations. Serial communication device. 6. A serial communication method in an electronic device, comprising: a transmission line connecting one master station and a plurality of slave stations in a loop; and storage means for storing an arrangement order of the plurality of slave stations on the transmission line. In response to the request from the master station, the arrangement order of the slave stations currently arranged on the transmission path is re-stored in the storage means based on the identifier information that each of the slave stations serially returns via the transmission path. An initialization communication step to set, and, based on the arrangement order of the slave stations reset by the initialization communication step, serially transfer information from the master station to the slave stations via the transmission path, and A normal communication step of serially transferring information from the first station to the master station, and storing the information serially transferred to the master station at a position corresponding to the slave station in the storage means; and a first slave station and a second slave station. Of the plurality of slave stations present on the classified transmission path, for the first slave station,
In the information transferred to the master station, at least one bit set in advance is set to a first fixed value;
A setting step of setting the bit to a second fixed value having a state different from the first fixed value; and setting the bit in the information stored in the storage means and transferred to the master station. A determination step of comparing the state of the fixed value set in the bit with the arrangement order thereof to determine whether or not there is a shift between the two; and, as a result of the determination, when there is a shift, A control step of controlling the initialization communication step to execute the processing again. 7. The serial communication method according to claim 6, wherein the number of said first slave stations is selected to be extremely smaller than the number of said second slave stations. 8. The information processing apparatus according to claim 1, wherein, in the information transferred to the master station stored in the storage unit, the information in which the first fixed value is set is compared with the arrangement order thereof. The serial communication method according to claim 7, wherein 9. The method according to claim 6, wherein, in the determining step, a shift determination is performed after the processing in the normal communication step has been completed for all of the plurality of slave stations.
The serial communication method according to any one of the above. 10. The method according to claim 6, wherein in the determining step, each time the processing in the normal communication step is completed for each of the plurality of slave stations, a shift determination is performed.
The serial communication method according to any one of the above. 11. A serial communication module in an electronic device, comprising: a transmission line for connecting one master station and a plurality of slave stations in a loop; and storage means for storing an arrangement order of the plurality of slave stations on the transmission line. A storage medium storing a program that can be realized by a computer, wherein the serial communication module is based on identifier information that each of the slave stations serially returns via the transmission path in response to a request from the master station. An initialization communication module for resetting the arrangement order of the slave stations currently arranged on the transmission path in the storage unit; and, based on the arrangement order of the slave stations reset by the initialization communication module, via the transmission path. Serially transferring information from the master station to the slave stations, serially transferring information from the slave stations to the master station, A normal communication module for storing serially transferred information at a position corresponding to the slave station in the storage means; and a plurality of slave stations existing on the transmission path classified into a first slave station and a second slave station. For the first slave,
In the information transferred to the master station, at least one bit set in advance is set to a first fixed value;
A setting module for setting the bit to a second fixed value having a state different from the first fixed value, and the information transferred to the master station stored in the storage means. A determination module that determines whether or not there is a difference between the two by comparing the state of the fixed value set in the bit and the arrangement order thereof, and when the result of the determination indicates that there is a difference, A control module for controlling the initialization communication module to execute the processing again. 12. The storage medium according to claim 11, wherein the number of said first slave stations is selected to be extremely smaller than the number of said second slave stations. 13. The information processing apparatus according to claim 1, wherein the information transferred to the master station stored in the storage means is the first one.
8. The storage medium according to claim 7, wherein the information in which the fixed value is set is compared with the arrangement order. 14. The apparatus according to claim 11, wherein the determination module performs a shift determination after the normal communication module completes one process for all of the plurality of slave stations. Storage media. 15. The apparatus according to claim 11, wherein the determination module performs a shift determination each time the processing by the normal communication module ends for each of the plurality of slave stations. Storage media.