JP2001013670A - Proximity correction method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for enhancing the efficiency of the proximity correction of a pattern forming process in terms of given chip layout design, and constitution therefor. SOLUTION: This method includes a step G01 for describing the pattern forming process in accordance with at least one layout parameter, a step G03 for making the distribution of at least one parameter discrete, a step G05 for providing an error correction table linking the correction of layout with at least one parameter and a step G06 for correcting the layout by applying correction in the table to the layout at least once.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates primarily to the fabrication of very large scale integrated (VLSI) circuit devices, and more particularly to a rule-based automatic proximity correction method and apparatus.

[0002]

2. Description of the Related Art Semiconductor device fabrication relies on the accurate copying of computer aided design (CAD) generated patterns onto the surface of a device substrate. The copying process is typically performed using, for example, photolithography followed by various subtractive (eg, etching) and additive (eg, deposition) methods. However,
Other patterning methods such as next generation lithography (NGL) and other operations following lithography, such as a damascene process, may also be used.

[0003] Taking photolithography as an example, photolithographic patterning involves a magnified image of a computer generated pattern etched into an opaque film.
It involves illuminating a master stencil called a photomask. This pattern is illuminated and (typically reduced in size) is projected onto a photosensitive film on the device substrate.

[0004] Light interference and processing effects that occur during pattern transfer cause the image formed on the device substrate to deviate from the ideal dimensions and shape represented by the computer image, and thus the image on the mask. This shift is
It depends on the characteristics of the pattern and various process conditions. This shift is usually referred to by the term (optical) "proximity effect", the magnitude of which depends on the resolution of the optical lithography system, defined as k ₁ λ / NA. Where λ is the illumination wavelength and NA is the numerical aperture of the imaging system.

[0005] Optical lithography with a k ₁ factor of less than 0.5 greatly complicates the proximity curve, which means that the deviation of the printed pattern from the original mask pattern is further increased. . For example, if the process is optimized for an array of DRAM chips (e.g., for some mask levels, equal lines and spaces), the more spaced lines outside the array will have line width and (configuration of geometry). May be printed smaller or larger depending on the environment. These effects may even cause lines and spaces to disappear.

[0006] This deviation can have a significant effect on the performance of the semiconductor device and must be minimized.

[0007] An alternative to costly developing processes with greater effective resolution is to compensate for pattern distortions that occur during wafer processing by selectively biasing the mask pattern. The term "optical proximity correction" (OPC), which tends to include pattern distortions unrelated to optical image transfer, is commonly used to describe this selective mask biasing process.

[0008] Many approaches have been pursued that focus on CAD compensation schemes in order to achieve an ideal image as a result. The methodology of these approaches is to characterize the patterning process experimentally based on first principle calculations, or a combination thereof, and to generate the expected patterning results based on these characterizations as desired. Based on inferring patterning inaccuracies by comparing with patterning results and applying geometric compensation to the patterning process input shape to eliminate the effects of patterning inaccuracies ing. These schemes can be based on interactive convolution of the input shape with a mathematical model of the patterning process, or the applicable compensation can be described in a rule table. Direct convolution methods provide more accurate results, but suffer from throughput limitations due to multiple computationally intensive operations. Rule-based corrections are fairly efficient as long as the number of rules required to accurately describe the corrections is relatively small. All conventional O
A limitation shared by PC approaches is that they are fundamentally aimed at improving accurate pattern duplication, rather than the robustness of pattern formation, ie, the ability to form patterns safely and without defects. That is. In high resolution patterning operations, it may not be possible to achieve CAD compensation that meets the requirements that these OPC tools aim to achieve, or the applied compensation will actually compromise the robustness of patterning there is a possibility.

Therefore, the purpose of the proximity correction system is to
Transfer masks from design data to transfer all features onto the wafer and to transfer patterns onto the wafer to meet all performance requirements of the resulting chip, i.e., within pattern-specific tolerances. Is to generate. However, conventional methods cannot do so in an efficient, computationally inexpensive manner.

[0010]

In view of the above and other problems of the prior art systems and methods, it is an object of the present invention to provide for less computation and simpler algorithms for higher order corrections, e.g. An arrangement and method for improving the printability of a pattern that uses a correction table based on only two parameters and is repeated regardless of the design pattern as the target pattern and with or without convergence requirements. To provide.

Another object of the present invention is that, unlike copying patterns to exact specifications, certain design levels need only be copied to "reasonable" accuracy of pattern copying. By recognizing is to improve the robustness of the pattern reproduction.

[0012]

SUMMARY OF THE INVENTION In a first aspect, a method is provided for efficiently performing proximity correction in a patterning process for a given chip layout design. The method provides for describing a patterning process in response to at least one layout parameter, discretizing a distribution of the at least one parameter, and providing an error correction table for linking layout modification to the at least one parameter. And correcting the layout by applying the corrections in the table to the layout at least once. Other aspects, including an apparatus and a signal generating medium, are also provided.

The unique, non-trivial feature of the present invention allows the layout to be redesigned to improve the robustness of the patterning process, rather than just copying the pattern exactly. Such a redesign is performed, for example, by mapping a limited parameter space (ie, line width and spacing for the nearest neighbor) to a “good” (safe) or “bad” (failure) region. can do.

Further, the present invention recognizes that in some cases (eg, not necessarily all), robust pattern duplication may be more important than accurate pattern duplication. Thus, by recognizing that some design levels must be patterned to exacting specifications and others that require that patterns only be copied within a reasonable range of the original design, And intermediate regions (eg, between a "safe" region and a "failure" region).

Thus, in the present invention, the patterning process is more efficient in moving the layout shape from its original location in parameter space to the closest safe point in parameter space at the expense of patterning accuracy. Desirable, specific design levels can be addressed.

Furthermore, the method of the present invention provides a simpler algorithm for higher order corrections, wherein the correction table is used based on a minimum number of parameters (eg, preferably only two). Finally, the iteration is performed irrespective of the design pattern as the target pattern and with or without convergence requirements. Thus, improved pattern printability with less computation is achieved.

Furthermore, by making the transition between different proximity environments gradual, a larger common process window can be obtained. Further, by using a "multi-pass" correction technique, higher order interactive corrections can be made without having to construct a variable function table.

Note that the invention is not limited to optical lithography. Other patterning methods can also be used, such as next generation lithography (NGL), other operations following lithography such as etching and deposition processes.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
The present invention is described herein below with reference to FIGS.

In general, the correction method of the present invention is based on rule-based automatic proximity correction using a table as input.

The efficient proximity correction method according to the present invention will be discussed in detail with reference to FIGS.

FIG. 1 shows that for any patterning process, the parameter space (eg, feature size or line width and feature spacing) provides good pattern transfer (eg, line width and space security). It is shown that the area 11 can be divided into an area 11 and an area 12 in which the pattern forming process fails or has a defect. Further, there is a third region 13 which is not desirable compared to the region 11 but is not a catastrophic region as in the region 12.

Thus, this area represents a space which is not necessarily the most favorable ("safe"), but which does not "fail". Note that the ideal "safe" position is assumed to be diagonal 14.

In the exemplary illustration of FIG. 1, when using the patterning process, areas along diagonals of equal line width / space are considered to be ideal for pattern formation. As shown in FIG. 1, thin lines in large spaces fail as well as thick lines in small spaces. Note that additional parameters such as pattern density and pattern direction can be added, but increase the complexity of the chart / table, thereby increasing the computational burden of the correction process described below. It should also be noted that other parameters can be considered in addition to space (or direction) and line width. Therefore, the present invention
It is not limited to the exemplary parameters described herein.

As shown by FIG. 1, unlike conventional OPC, which merely aims at accurate pattern duplication, the present invention redesigns the layout and improves the robustness of the patterning process. I have. Such a redesign reduces the limited parameter space (ie, line width and spacing to the nearest neighbor), as shown in FIG. 1, in the “good” (safe) region and the “bad” (failure). ) Can be implemented by mapping to a region.

The present invention also presupposes that in some cases (eg, not necessarily all), robust pattern duplication may be more important than accurate pattern duplication. For example, design levels, such as the transmission gate of a field effect transistor, must be patterned to exact specifications given by the designer. However, other design levels, such as wiring levels, only require that the pattern be copied within a "reasonable" range of the original design. In such a case, not only values that fall within the “safe” area are acceptable, but also “intermediate” in FIG.
Values that fall within region 13 are also acceptable.

Therefore, in the present invention, the pattern forming process can be defined by a finite number of parameters, and the parameter space (ie, the combination of the finite number of parameters) can be divided into “safe” and “failure”.
However, at some design levels, it is more desirable to move the layout shape from its original location in parameter space to the nearest safe (or "middle") point in parameter space at the expense of patterning accuracy. .

For example, the first method is to limit the layout according to a design rule and to include all patterns in a chip design in a “safe pattern forming area”. In such a case, the design rules given by way of example in FIG. 1 are such that thin lines require a small space and correspondingly small spaces require a thin line. Such a process is optimized until the patterning process is changed so that the area depicted in FIG. 1 looks completely different, so that a complete redesign of the chip (eg, is very time consuming) , Costly redesign).

The second technique is to mathematically model the pattern forming process. Such a model is
It can be derived from first principles or experimentally adapted to experimental data. Iterative optimization can then be performed by repeatedly convolving the drawn shape with the patterning model, measuring image quality, and manipulating the drawn shape to improve image quality. . However, such techniques are very slow, computationally intensive, and the originally drawn shape is not directly related to the desired optimized shape (eg, considering that accuracy is not as important as robustness). . Therefore, it is difficult to formulate a quality function that the iteration can optimize.

The third method is a rule-based correction method. However, one feature is changed from “failure” to “safe”
Correction changes to describe the environment for neighboring features that were originally "safe", which in turn could cause the neighboring features to fall within the "failure" region, Such an approach is difficult to envision. The rules for moving all features from "failure" to "safe" in a single operation can be quite complex and can be very resource intensive.

With the above description and the parameter distribution partitions of FIG. 1 in mind, the present invention provides several methods for implementing the above and other objects of the present invention.

A feature of the invention is that it creates a simple rule table that eventually moves all shapes from the "failure" area to the "safe" area (eg, as shown in FIG. 1). (Note that in a single move, it is very likely that all features and their neighbors will not be in the "safe" area) and apply the layout to this simple table one or more times The end result is that the entire layout is in the "safe" area. Moving the shape from its original point in parameter space to its ideal position (eg, diagonal 14 in FIG. 1) is not straightforward because it involves all parameters (eg, In such a case, the space becomes smaller as the line width increases, so that when the line width changes, it necessarily affects the space for the adjacent line.)

However, when the present invention is used, no matter how the shape moves in this parameter space, if the shape is sufficiently passed through a simple correction table, an ideal position (for example, FIG. 1 (eg, a very large space area of the section of FIG. 1) or across (eg, a large space) until it comes into a stable (“safe”) area. Line width area)
Be moved.

Thus, the present invention provides a "safe" parameter space and a series of simple rule-based corrections to achieve complex redesigns, and all features must be copied to exacting specifications. Recognizing that this is not the case, it improves the robustness of the pattern reproduction.

FIGS. 2-5 illustrate how an exemplary rule table is generated based on a particular parameter space, and will be discussed in more detail below.

First, FIG. 2 shows that the layout is made on a finite design grid (ie, the corners or "vertices" of the shape are
It must be drawn at an integer multiple of the design grid n), thus illustrating that line width and space continuity are not necessarily present or required by the present invention.

In the illustrated example, the design grid has a side of 25 nm.
Having a square. Of course, other values for the grid size can be selected depending on the constraints and requirements of the designer.

In FIG. 3, the design grid is changed to a smaller number (to increase the resolution) to achieve a finer correction grid. The size of the correction grid is ultimately limited by the mask writing tool. That is, a smaller grating in the design requires a smaller mask writing grating that increases the mask writing time very quickly,
Thus, there is a tool-dependent minimum grid that can be performed accurately. Thus, the correction grid is defined by manufacturing constraints (and is limited in a practical sense). FIG.
, The design grid is reduced in half to provide a correction grid. Therefore, in FIG. 3, finer granularity is obtained compared to the original lattice of FIG.

Here, before the design, all the shapes must be arranged on the intersections of the design grid. The shape can be moved to any intersection of the correction grid (e.g., by repeatedly passing through a rule table). However, for simplicity, in the parameter space selected in this example, the shape is moved only from the lower right to the upper left (ie, perpendicular to the ideal 45 degree line).

In this case, as the line width increases, the space decreases, and vice versa. Since the line width and the space are directly linked, movement on the design grid can be expressed in terms of a change in only the line width. This is more logical than choosing the opposite, because it is the shape, not the space, that is actually manipulated. Of course, the present invention can also manipulate spaces in alternative embodiments. Thus, as illustrated in FIG. 3, such subdivisions of the design grid are for correcting / manipulating the shape.

FIG. 4 shows that the starting position is LW (line width) = 300.
The movement for a shape with nm, space = 175 nm is illustrated. Such a shape has a diagonal of 237.5 nm,
It is moved towards the intersection of space 237.5. With different parameters, the movement will be different. Further, FIG.
Clearly shows that adjusting the line width affects spacing in the design.

FIG. 5 simply represents the movement of FIG. 4 in the form of a rule table. Although not shown in FIG.
For shapes having a spacing of
There may be at least one additional feature in nm.

For example, if this second feature is 175 /
If it is 175, it is safe. However, moving its neighboring features as shown in FIG. 4 (eg,
The space is increased from 175 to 237.5 nm), this second feature is also moved to the 237.5 nm space and the second feature is placed in the failure area.

Next, a second pass through the same correction table of the present invention moves the "second feature" to the safe area.

In this application example, the term “design to table”
"Apply" or "pass through" means that the layout is passed through a CAD tool (or application) that applies corrections based on the instructions contained in the table. The concept of “passing through” a CAD tool is to load the layout into the tool, manipulate the layout geometrically,
It will then be quite generally understood by those skilled in the art to output it again.

Furthermore, describing a shape with two edges, each edge having a spacing, complicates the movement of the shape, and in fact, each shape has two entries in the parameter space table (eg, (Left edge spacing and right edge spacing). Both edges move independently in parameter space based on the movement of neighboring features.

Thus, the present invention achieves a “safe” parameter space and a series of simple rule-based corrections
Provided to achieve complex redesign.

Turning to FIG. 6, the above-described invention is further clarified by reference to the flowchart of FIG. 6, which illustrates the method of the present invention.

First, in step 601, the process of interest is characterized. In this step, the robustness of the process is linked to the design parameters.

In step 602, a parameter space is defined (eg, line width and space for the nearest neighbor) to determine preferred and undesirable layout states. For example, something close to an equal line space can be considered “good” (eg, see region 11 in FIG. 1), and those that deviate significantly from that ideal are:
There is a sub-optimal but acceptable risk area (eg, area 13 in FIG. 1) that is considered “bad” (eg, see area 12 in FIG. 1). Once again, the present invention is concerned with whether a design level must be duplicated with absolute accuracy, or whether a design level must be duplicated simply to avoid being in a "bad" area of the grid. Is determined in advance, thereby reducing the computation and increasing the robustness of the copying process.

In step 603, as shown in FIG. 2, the parameter space is discretized based on allowable design conditions (eg, mask manufacturing constraints and design rule limitations).

In step 604, as shown in FIG. 3, the allowable correction conditions are defined based on the "valid" (acceptable) reduction of the design grid. For example, in the present case, the design grid can be halved to obtain one intermediate legitimate line width / space. Alternatively, the design grid can be reduced to a quarter or the like.

In step 605, as shown in FIGS. 3-4, by assessing the distance between each acceptable layout state (eg, the intersection of a real grid line) and the secure space, the parameter space is reduced. It is converted into a correction table.
For example, the ideal state may be in the middle of a secure space, but conservative weakening applies only a fraction of the total distance in one correction step. 300nm line is 1
Illustrated with a 75 nm space. Complete correction is
This is equivalent to 2.5 squares of the original design grid. The correction is based on edges, so conservative tables use less than half of the full correction value (eg grid 1.25 in line width)
Use less than squares). One edge is moved by at most half of the distance to the ideal line width / space. This is because it is not known if the other edge of the feature will be so. In some cases, moving each edge half that distance can result in non-convergence (ie, repeatedly jumping from right to left of the ideal line and vice versa). Therefore, one-fourth of the full correction per edge is the safest.

FIG. 5 shows a correction table.

After step 605, a correction is applied at step 606 by passing through a rule-based table.

In step 607, the output is checked.

At step 608, it is determined whether the output is acceptable (eg, based on a defined parameter space). Thus, if the shape has been moved to satisfy the "safe" or "intermediate" regions of the design grid of FIG. 1, the output is considered acceptable and the process ends.

If the output is not acceptable (eg,
Values within the "failure" region) can be subjected to further iterations until the output is acceptable.

[0059] Optionally, the process may continue to step 609 to determine if the maximum number of iterations has been reached. If that number has not been reached, the correction is applied again. If it is determined that the maximum iteration has been reached, the process simply ends. Thus, the designer can limit the design to a predetermined number of iterations when determining whether the design is feasible. Such steps allow designers to save wasted computationally intensive resources.

Optionally, the checking procedure found in steps 607-608 can be bypassed (eg, not performed) and the decision can be made directly from step 606 to step 609. That is, the number of iterations is fixed in advance, and the process ends when it is determined that the number of iterations has been reached.

In certain implementations of the invention, special rules (eg, Niagara® (IBM), PROTEUS
(Precim Company) to process large design data and shift each edge of the shape using software that can shift the edges (or
The motion of the shape edges (each segment) was made to be a function of the width of the shape and the distance to the nearest neighbor (eg on the same level). Therefore, only two parameters (eg, line width and distance to the nearest neighbor) were used to determine the correction for each edge (or each segment of an edge).

For example, in the correction table shown in FIG. 7, the shaded entry of the table must have a line width of 250 nanometers and a spacing of 300 nanometers to the nearest adjacent line without correcting grid point +0.5. Indicates that it must not. In other words, the correction must be made by shifting the edge of the line by +0.5 (25 nm) = 12.5 nanometers toward the nearest neighbor. Some conventional systems have a table with 5 parameters as input (in addition to the line width and the space to the nearest neighbor line, other parameters include the line width of the nearest neighbor line, the line under consideration Hidden space on the other side of the, there is a line width next to the hidden space). This is very complex and computationally intensive. For example, with two parameters, in Fig. 7 exemplary table to be applied to the two tables, without extremely increasing the bucket (e.g., (6 ^{2) 2} 2 × 6 ² compared to), more and more Parameter effects are possible. In this example, the line width and the hidden space of the nearest adjacent line in the second pass.
Each pass through the table adds two input parameters.

By applying (eg, processing) the design to the table (eg, shown in FIG. 7) more than once,
The transition between different proximity environments takes place more gradually (for example, see FIGS. 8 and 9).

Accordingly, the robustness of the printed shape in various proximity environments can be increased or in some cases achieved.

More specifically, FIG.
84 are shown together with the designed shape. FIG. 9 illustrates a corrected shape (eg, a black rectangle) after a pass through the second table. The first pass enlarges the outer line. The second pass also enlarges the outer space as well as the outer line.

Although the general methodology of the present invention has been described above, it will be appreciated by those skilled in the art that the present invention can be implemented in many different types of systems and can be implemented in many different ways. .

For example, as illustrated in FIG. 10, a typical hardware configuration of an information processing / computer system according to the present invention preferably has at least one processor or central processing unit (CPU) 11. The CPU 11 connects a random access memory (RAM) 14, a read-only memory (ROM) 16, and peripheral devices such as the disk unit 21 and the tape device 40 to the bus 12 via the system bus 12. Input / output (I / O) adapter 18, keyboard 24, mouse 26, speaker 28, microphone 3
2, and / or a user interface adapter 22 (for connecting other user interface devices to the bus 12), a communication adapter 34 (for connecting an information processing system to a data processing network), Interconnected to a display adapter 36 (for connection to a display device 38).

Although the invention has been described primarily with reference to a software configuration or a software / hardware configuration, furthermore, the same or similar functions may be implemented in a dedicated hardware configuration.

In addition to the hardware / software environment described above, different aspects of the present invention
And a computer implemented method for identifying critical paths requiring high voltage bus configuration. By way of example, the method may be implemented in the particular environment described above.

Such a method can be implemented, for example, by operating a computer to execute a sequence of machine-readable instructions, as implemented by a digital data processing device. These instructions are
It can reside on various types of signal producing media.

Accordingly, this aspect of the invention provides a program, including a signal-generating medium, that substantially implements a program of machine-readable instructions executable by a digital data processor to perform a method of designing a circuit. Targets expression products.

The signal generating medium is, for example, a random access memory such as a high-speed access storage area included in a computer.
An access memory (RAM) may be included. Alternatively, the instructions may be contained on another signal-producing medium that is directly or indirectly accessible by a computer, such as the magnetic data storage diskette 500 exemplarily shown in FIG.

The instructions, whether contained on a diskette, on a computer, or on another device, are stored on a DASD storage device (eg, a conventional "hard drive" or RAID array). , Magnetic tape, electronic read only memory (for example, ROM, EPRO
M, or EEPROM), an optical storage device (eg,
CD-ROM, WORM, DVD, digital optical tape, etc.), paper "punch" card, or digital link,
It can be stored on various machine-readable data storage media, such as analog links, communication links, other suitable signal-producing media, including transmission media such as wireless. In an exemplary embodiment of the invention, the machine readable instructions may comprise software object code compiled from a suitable language.

Thus, according to the present invention, improved stiffness of the printed shape can be obtained by progressively transitioning between different proximity environments. In addition, the robustness of pattern duplication is different from duplicating patterns to exacting specifications, and some design levels have a "reasonable" accuracy (e.g., key shapes are placed in "good" locations on the design grid). It is provided by recognizing that it is only necessary to copy the pattern copy (which moves the non-essential shapes to the "good" or "middle" position on the design grid).

Using the “multi-pass” correction technique, a>
Higher order interactions can be described without having to construct two variable function tables. Therefore, the present invention
Use only two parameters (eg, line width and spacing to the nearest neighbor to determine how far the edge of the line must be moved to make the correction) Use a simple table. It should be noted that the invention is not limited to these two parameters, as will be clear from the above description.

In addition, the present invention that implements multi-pass correction keeps the computational requirements of each pass relatively simple, rather than attempting to correct in a single computationally intensive pass.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.

For example, although the example of photolithography pattern formation has been described above, the present invention is not limited to such a pattern formation method. Next generation lithography (NGL),
Other patterning methods can also be used, such as other operations following lithography, such as etching and deposition processes.

Further, the exemplary implementation described above is based on 2
Although based on one parameter (eg, line width and space), more or less parameters, or different parameters could be used.

In summary, the following items are disclosed regarding the configuration of the present invention.

(1) A method for proximity correction of a pattern formation process for a given chip layout design, comprising the steps of describing a pattern formation process according to at least one layout parameter, and a distribution of the at least one parameter. And providing an error correction table that links a layout correction to the at least one parameter; and correcting the layout by applying the correction in the table at least once to the layout. A method that includes (2) The method according to (1), wherein the at least one parameter includes any of a feature size or line width and a feature spacing. (3) The step of discretizing the distribution includes a first “safe” area where an optimal pattern transfer is performed, a second “failure” area where a pattern forming process fails, the first area and the first area. The method of claim 1, including dividing the parameter space into a third "intermediate" region that is intermediate to the second region and is a minimally acceptable region. (4) Redesigning the layout to improve the robustness of the patterning process so that all pattern transfers of the shape selectively fall within the first or third regions. ). (5) The step of describing the pattern formation process includes the step of defining a finite number of parameters, and the parameter space comprising the finite number of parameter combinations comprises a first “safe” area and a second “safe” area. The method according to (1), wherein the method is divided into a "failure" region and a third acceptable "intermediate" region. (6) The correction table finally determines all shapes,
To move from the second "failure" area in the direction of the first "safe" area of the parameter space, and that the entire layout is at least one of the first "safe" area and the third "intermediate" area The method according to (3), wherein the method is for applying the chip design layout at least once by a table as included in the above. (7) Further, which features must be included in a first "safe" region of the parameter space and which features can be included in a minimally acceptable third "intermediate" region The method according to (1), further comprising the step of recognizing (8) The method of (1) above further comprising the step of characterizing the process such that the robustness of the process is linked to the design parameters in the parameter space. (9) Further, a first “optimal” area and a second “failure”
The method of claim 1, further comprising the step of determining preferred and unfavorable layout states of the parameter space including the region and a third "intermediate" region that is not optimal but minimally acceptable. (10) Does the characterization step have to duplicate the design level to the optimal region with absolute accuracy, or simply avoid the design level being within the "failure" region of the design grid in parameter space? (8). The method according to the above (8), which includes a step of determining in advance whether to make a copy. (11) The method according to (10), wherein the parameter space includes a line width and a space to a nearest neighbor line. (12) The method according to (1), wherein the step of discretizing the distribution includes the step of discretizing a parameter space based on allowable design conditions. (13) The method according to (1), further comprising the step of defining an allowable correction condition based on an allowable reduction of the design grid in the parameter space. (14) The method of (1) above further comprising the step of converting the parameter space into a correction table by assessing the distance between each acceptable layout state and the safe space. (15) checking the output of the table, and determining whether the output is acceptable based on the described pattern formation process, wherein the design is a first of the design grids; Filling the first "safe" area or at least the third "intermediate" area, which is acceptable but not optimal, and said layout satisfies the first "safe" area or the third "intermediate" area If not, iterating through the table again. (16) The method of (1) above, further comprising the step of repeating a predetermined number of times through the table without checking the output of the correction table between iterations. (17) The method according to (1), further comprising applying a design a predetermined number of times using the correction table, and checking the output of the correction table after the predetermined number of times is completed. (18) The method according to (1), wherein the correction table includes a line width and a distance to a nearest adjacent line. (19) The method according to (1), wherein the correction includes continuously applying the layout design two or more times through a correction routine in which the design output of the previous pass becomes the design input of the subsequent pass. . (20) A proximity correction method for increasing the robustness of a patterning process for a given chip layout design, the method comprising: describing a quality of the patterning process in response to at least one layout parameter; Discretizing the distribution of the parameters, providing a table linking the improved patterning quality to the modification of the at least one parameter, and applying the modification in the table to the layout; Improving the patterning robustness of the layout. (21) further comprising capturing the higher order interaction of the at least one parameter with the patterning robustness by applying the modification to the layout at least once. The method described in. (22) Optical proximity correction (O) to increase the robustness of the patterning process for a given chip layout design
PC) method, comprising: providing an error correction table having at least one parameter; and applying a design at least once with the correction table, whereby all shapes in the design are: Included within at least one of a first "safe" optimal region and a third "intermediate" minimally acceptable region;
A method for ensuring that no shapes are included in the second "failure" area. (23) A method for improving the transferability of a design pattern from a patterned mask to a substrate by optical lithography, wherein the design pattern has an edge of a shape, and according to a value of at least one parameter, Providing an error correction table indicating an error correction increment for the at least one parameter; determining, for at least one of the edges, a value of the at least one parameter; corresponding to the determined parameter value Adjusting the at least one parameter with respect to the at least one edge by an error correction increment from the table. (24) Optical proximity correction (O) to increase the robustness of the patterning process for a given chip layout design
PC) The method wherein the design comprises a shaped edge;
Providing an error correction table indicating an error correction increment for at least the first parameter in response to the value of the first parameter; and for at least one of the edges of the design, changing the value of the at least one parameter. Determining a value of the at least one parameter with respect to the at least one edge by an error correction increment from the table corresponding to the determined parameter value. (25) A run-time effective optical proximity correction (OPC) method for capturing proximity effects that are more parameter dependent on the design, wherein defining a parameter space for a patterning process; A method comprising: discretizing; providing an error correction table having at least one parameter; and applying the shape of the design at least twice with the table. (26) The proximity effect having higher parameter dependence is as follows:
The method according to (25), wherein the table is captured by applying the shape of the design by the table in one or more subsequent correction runs. (27) The method according to (25), wherein the correction includes two or more continuous paths through a correction routine in which a design output of a previous path becomes a design input of a subsequent path. (28) An apparatus for improving the transferability of a design pattern from a patterned mask to a substrate by optical lithography, the means for describing a pattern formation process according to one or more layout parameters. Means for discretizing the distribution of the parameters, an error correction table for linking the layout correction to one or more of the parameters, and applying the correction in the table at least once to the layout. And means for correcting the layout. (29) A signal-generating medium that substantially implements a program of machine-readable instructions executed by an apparatus to implement a method of increasing the robustness of a patterning process for a given chip layout design, The method includes the steps of describing a patterning process in response to one or more layout parameters, discretizing a distribution of the parameters, and an error linking layout modification to the one or more parameters. A signal generating medium comprising: providing a correction table; and correcting the layout by applying the corrections in the table at least once to the layout.

[Brief description of the drawings]

FIG. 1 shows the operation of the method according to the invention.

FIG. 2 shows the operation of the method according to the invention.

FIG. 3 shows the operation of the method according to the invention.

FIG. 4 shows the operation of the method according to the invention.

FIG. 5 illustrates the operation of the method according to the invention.

FIG. 6 is a flow chart of a method according to the present invention.

FIG. 7 is a diagram showing a correction table in which correction is based on design grid points.

FIG. 8 shows a desired shape.

9 is a corrected after a second pass through the table of FIG. 7, wherein the first pass enlarges the outer line and the second pass enlarges the outer space as well as the outer line. It is a figure showing a shape (for example, a black rectangle).

FIG. 10 illustrates an exemplary information processing / computer system for use with the present invention.

FIG. 11 shows a medium for storing a program for implementing the method according to the invention.

[Explanation of symbols]

 Reference Signs List 11 random access memory (RAM) 12 system bus 14 random access memory (RAM) 16 read-only memory (ROM) 18 input / output (I / O) adapter 21 disk unit 22 user interface adapter 24 keyboard 26 Mouse 28 Speaker 32 Microphone 34 Communication Adapter 36 Display Adapter 38 Display Device 40 Tape Device 500 Magnetic Data Storage Diskette

Continued on the front page (71) Applicant 399035836 Infineon Technologies North America Corporation Infineon Technologies North America Co. USA San Jose North First Street 1730 1730 North First Street, San Jose, CA, San Jose, CA, United States San Jose North First Street U.S.A. 12590 Wappingers Halls, NY Penlock Circle 19F (72) Inventor Kamiz Farahapur United States 12540 La Grangeville Cross Road 116, NY 116 (72) Inventor Henning Huffner United States 12524 Drive 15 Apartment Dee (72) Inventor Mark Lee Rabin United States 10536 Katton-Anne Chambers Lane, New York 20 (72) Inventor Lars W. Liebman United States 12570 Polkwag Cornwell Street, New York 5 (72) Inventor Donald J. Samuels United States 80498 Colorado Cyberthorne Emerald Road 1228

Claims (29)

[Claims] 1. A method for correcting proximity of a patterning process for a given chip layout design, comprising: describing a patterning process in response to at least one layout parameter; Discretizing; providing an error correction table linking a layout correction to the at least one parameter; and correcting the layout by applying the correction in the table to the layout at least once. Including methods. 2. The method of claim 1, wherein the at least one parameter comprises one of a feature size or line width and a feature spacing. 3. The step of discretizing the distribution includes a first “safe” area where an optimal pattern transfer is performed, a second “failure” area where a pattern forming process fails, and the first area. 2. The method of claim 1, comprising dividing the parameter space into a third "intermediate" region that is intermediate to the second region and is a minimally acceptable region. 4. The layout is redesigned to improve the robustness of the patterning process so that all pattern transfers of a shape selectively fall within the first region or the third region. Item 4. The method according to Item 3. 5. The method of claim 1, wherein the step of describing the patterning process includes the step of defining a finite number of parameters, wherein the parameter space comprising the finite number of parameter combinations comprises a first "safe" area, a second 2. The method of claim 1, wherein the "failure" region is divided into a third "intermediate" region that is at least acceptable. 6. The correction table for moving all shapes eventually from a second "failure" area to a first "safety" area of the parameter space, and that the entire layout is 4. The method according to claim 3, wherein the method is for applying the chip design layout at least once by a table to be included in at least one of a first "safe" area and a third "intermediate" area. 7. Further, which features must be included in a first "safe" area of said parameter space and which features are included in a minimally acceptable third "intermediate" area. 2. The method of claim 1 including recognizing whether it is possible. 8. The method of claim 1, further comprising the step of characterizing the process such that the robustness of the process is linked to design parameters in a parameter space. 9. A preferred layout state of the parameter space including a first "optimal" region, a second "failure" region, and a third sub-region that is not optimal but at least acceptable. The method of claim 1, comprising determining an undesired layout state. 10. The step of characterizing whether the design level must be copied to the optimal region with absolute accuracy, or simply lies within the "failure" region of the design grid in parameter space. 9. The method of claim 8 including the step of determining in advance whether to duplicate so as to avoid. 11. The method of claim 10, wherein said parameter space includes a line width and a space to a nearest neighbor line. 12. The method of claim 1, wherein the step of discretizing the distribution includes the step of discretizing a parameter space based on acceptable design conditions. 13. The method of claim 1, further comprising the step of defining allowable correction conditions based on an allowable reduction of the design grid in the parameter space. 14. The method of claim 1, further comprising the step of converting the parameter space into a correction table by assessing the distance between each acceptable layout state and the safety space. 15. The method further comprising: checking the output of the table; determining whether the output is acceptable based on the described patterning process;
Allowing the design to fill a first "safe" area of the design grid, or a minimally acceptable but non-optimal third "intermediate"area; and Iterating through the table again if the third "intermediate" region is not satisfied. 16. The method of claim 1, further comprising the step of repeating a predetermined number of times through said table without checking the output of said correction table between iterations. 17. The method of claim 1, further comprising: applying a design a predetermined number of times with the correction table; and checking the output of the correction table after the predetermined number of times has been completed. 18. The method according to claim 1, wherein the correction table includes a line width and a distance to a nearest neighbor line. 19. The method according to claim 1, wherein the correction includes continuously applying the layout design two or more times through a correction routine in which the design output of the previous pass becomes the design input of the subsequent pass.
The method described in. 20. A proximity correction method for increasing the robustness of a patterning process for a given chip layout design, the method comprising: describing a quality of the patterning process in response to at least one layout parameter; Discretizing the distribution of one parameter; providing a table linking the improved patterning quality to the modification of the at least one parameter; applying the modification in the table to the layout. Improving the patterning robustness of the layout. 21. Capturing a higher order interaction of said at least one parameter in conjunction with said patterning robustness by applying said modification to said layout at least once. 20. The method according to 20. 22. An optical proximity correction (OPC) method for increasing the robustness of a patterning process for a given chip layout design, comprising: providing an error correction table having at least one parameter; Applying the design at least once with a correction table so that all features in the design have a first "safe" optimal region and a third "intermediate" minimally acceptable region. A method wherein no shape is included within at least one region and within a second "failure" region. 23. A method for improving the transferability of a design pattern from a patterned mask to a substrate by optical lithography, the design pattern comprising an edge of a shape, wherein the design pattern comprises an edge of a shape, and wherein the design pattern has an edge of the shape. Providing an error correction table indicating an error correction increment for the at least one parameter; determining a value of the at least one parameter for at least one of the edges; Adjusting said at least one parameter with respect to said at least one edge by an error correction increment from a corresponding said table. 24. An optical proximity correction (OPC) method for increasing the robustness of a patterning process for a given chip layout design, said design comprising an edge of a shape, and a value of said first parameter. Providing an error correction table indicating an error correction increment for at least a first parameter in response to determining the value of the at least one parameter for at least one of the edges of the design; Adjusting the at least one parameter with respect to the at least one edge by an error correction increment from the table corresponding to the determined parameter value. 25. A run-time effective optical proximity correction (OP) to capture proximity effects that are more parameter dependent on the design.
C) A method comprising: defining a parameter space for a patterning process; discretizing the parameter space; providing an error correction table having at least one parameter; Applying the shape of at least twice. 26. The method of claim 25, wherein the more parameter dependent proximity effect is captured by applying the shape of the design with the table in one or more subsequent correction runs. 27. The method of claim 25, wherein the correction includes two or more consecutive passes through a correction routine in which a design output of a previous path becomes a design input of a subsequent path. 28. An apparatus for improving the transferability of a design pattern from a patterned mask to a substrate by optical lithography, the apparatus describing a patterning process in response to one or more layout parameters. Means for discretizing the distribution of the parameters; an error correction table for linking the layout correction to one or more of the parameters; and applying the correction in the table at least once to the layout. And means for correcting the layout. 29. A signal producing medium that substantially implements a program of machine readable instructions executed by an apparatus to implement a method that increases the robustness of a patterning process for a given chip layout design. The method comprising: describing a patterning process in response to one or more layout parameters; discretizing a distribution of the parameters; and linking a layout modification to one or more of the parameters. A signal generation medium, comprising: providing an error correction table to cause the correction; and applying the correction in the table to the layout at least once to correct the layout.