JP2001013187A - Matrix array device and substrate for matrix array device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate for a matrix array device and the matrix array device allowing effective and accurate inspection of variation of a transistor characteristic. SOLUTION: This substrate 100 for a matrix array device has inspection circuit parts 104 each disposed near an area formed with at least one of a gate line drive circuit part 102 and a signal line drive circuit part 103 over a nearly same length as one side of the drive circuit 102 or 103 or above. By measuring an oscillation frequency of the inspection circuit part 14, variety of a transistor characteristic different in each the area can be easily and accurately detected on the substrate 100 for the matrix array device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix array device and a substrate on which the matrix array device is formed, and more particularly to a substrate having a built-in inspection circuit for performing a reliability test.

[0002]

2. Description of the Related Art A schematic configuration of a matrix array device will be described with reference to FIG. This device includes a plurality of gate lines 203 and signal lines 2 on the same insulating substrate 201 such as glass.
02, and a thin film transistor (hereinafter, referred to as a TFT) formed of polycrystalline silicon used as a pixel electrode 209 and a switching element near the intersection.
(Referred to as a reference numeral 210) are integrally formed with a matrix array portion in which a matrix is arranged and a driving circuit which is constituted by TFTs and drives gate lines and signal lines.

A matrix array device can be used as an image pickup device by providing a photoelectric conversion film or the like (not shown) on an upper portion of the device. In addition, a counter substrate (not shown) and a matrix array device may be arranged to face each other with a gap therebetween, and a liquid crystal composition may be sealed therebetween to be used as a liquid crystal display device.

When this device is used as an imaging device,
Electromagnetic waves such as X-rays are applied to the photoelectric conversion film or the like to generate charges, accumulate on the pixel electrodes 209, scan by the gate lines 203, and read signal charges from the signal lines 202 via the TFTs 210.

When this device is used as a liquid crystal display device, a signal voltage scanned by the gate line 203 and supplied from the signal line 202 is applied to the pixel electrode 209 to form an image.

When the signal line 202 is used as an imaging device, signal charges read from the signal line 202 are transferred to a bus line 212 via an analog switch 206 and a buffer 207 formed on the same insulating substrate 201. You.

When used as a liquid crystal display device, a video signal is supplied to a signal line 202 via an analog switch 206 and a buffer 207.

The analog switch 206 samples a video signal supplied from the video bus line 212 based on a signal given from the X-side shift register 211. Here, the X-side shift register 211 receives a start pulse and a clock signal, sequentially shifts the start pulse based on the clock signal, and generates a signal for sampling.

The gate line 203 is supplied with a scanning signal generated by the Y-side shift register 205 formed on the insulating substrate 201 via the buffer 204 and supplies the scanning signal to the gate of the TFT 210.

In such a matrix array device,
For example, a region in which the pixel electrodes 209 and the TFTs 210 are arranged in a matrix is defined as a matrix array unit, and the X shift register 211, the analog switch 207, the buffer 2
The circuit including 06 is referred to as a signal line driving circuit, and the circuit including the Y shift register 205 and the buffer 204 is referred to as a gate line driving circuit.

As shown in FIG. 17, the matrix array device includes a matrix array section 221, a signal line drive circuit section 223, and a gate line drive circuit section 222. One or a plurality is formed, and unnecessary portions are separated and used.

Also, the matrix array device substrate 220
On the outer periphery of the region where the matrix array device is formed, one or a plurality of test circuits 224 each composed of a single transistor or a circuit using a transistor are formed. Used for inspection.

However, the above-mentioned conventional substrate for a matrix array device has the following problems.

The inspection circuit 224 is located locally on the matrix array device substrate 220. Therefore, if there is a variation in characteristics depending on the position on the substrate 220 due to a variation in the manufacturing process, the above-described inspection circuit 2
24, it was difficult to detect it reliably.

In particular, in a device in which a drive circuit section including a signal line drive circuit section 223 and a gate line drive circuit section 222 is built on the same substrate 220 together with a matrix array section 221, a drive circuit using, for example, an amorphous silicon TFT is used. It is more important to ascertain the variation in the characteristics of the transistors constituting the drive circuit section than in a device without a built-in device.

Further, in the conventional substrate for a matrix array device, the inspection has to be performed by bringing the inspection probe into contact with each inspection circuit 224. Therefore, in order to detect the variation on the substrate 220 with high accuracy, the inspection circuit 22
When the number of 4 is increased, the inspection time is increased and the inspection efficiency is deteriorated.

The configuration of the conventional matrix array device substrate and its problems have been described above. Next, the matrix array device separated from the substrate will be described.

The matrix array device is required to be more inexpensive whether it is used as an image pickup device or a liquid crystal display device.

In order to cope with such a demand, as described above, a method for reducing the number of members and reducing the cost by forming and integrating the drive circuit section together with the matrix array section on the same insulating substrate. Used.

In a matrix array device having a built-in drive circuit unit, it is necessary to guarantee an operation life equal to or longer than that of a device in which the drive circuit unit is externally mounted on a substrate. Here, the drive circuit section is generally composed of P-type and N-type TFTs.

However, conventionally, in order to confirm the operating life of the drive circuit section in the matrix array device, individual TFs are required.
The reliability test was performed using the matrix array device itself instead of T.

FIG. 18 shows an example of the results of a reliability test performed with a conventional matrix array device. As shown in FIG. 18, the operation time is generally at least 100.
A long-term reliability test of 00 hours is required.

However, when a reliability test is performed using the matrix array device itself, it is difficult to prepare a large number of samples because it takes a long time to prepare the sample and the number of parts is large and the cost is high.

In addition, if the reliability test is not performed for a long time,
There was also a problem that sufficient reliability could not be confirmed. For example, in the case where the characteristics of the TFTs constituting the drive circuit unit are slightly inferior, the drive circuit unit stops operating just before the test time passes 10,000 hours as shown in FIG. , May prove to be unreliable. For this reason, there has been a problem that the reliability test requires a long time and the test cost cannot be reduced.

[0025]

As described above, it is difficult to detect the variation in the characteristics of the transistors constituting the drive circuit unit built in the substrate in the conventional matrix array device substrate, as described above. However, there is a problem that the inspection time is long and the efficiency is low.

Further, in a conventional matrix array device,
There is a problem that the inspection time is long and it is difficult to reduce the cost.

The present invention has been made in view of the above circumstances, and provides a matrix array device substrate capable of efficiently and highly accurately inspecting variations in characteristics existing on the matrix array device substrate. It is an object of the present invention to provide a matrix array device capable of shortening the time.

[0028]

A substrate for a matrix array device according to the present invention is arranged on an insulating substrate so that a plurality of gate lines and signal lines intersect with each other, and near an intersection of the gate line and the signal line. A matrix array portion in which pixel electrodes and switching elements are arranged in a matrix; a gate line driving circuit portion provided on the insulating substrate to drive the gate lines; and a signal line provided on the insulating substrate. And a signal line drive circuit portion for driving the one of the gate line drive circuit portion and at least one of the signal line drive circuit portions provided on the insulating substrate; And a test circuit section used for testing characteristics of the matrix array section or the drive circuit section.

The inspection circuit may be used for inspection based on the oscillation frequency of the inspection circuit.

Here, a plurality of matrix array devices having the matrix array portion, the gate line drive circuit portion, and the signal line drive circuit portion are provided on the same insulating substrate, and the inspection circuit portion is provided in the matrix array device. It may be provided for each.

The inspection circuit section may be arranged adjacent to one side of the drive circuit section so as to extend in the same direction.

The inspection circuit section may be arranged so as to surround the outer periphery of each of the matrix array devices.

Alternatively, the test circuit section may include test circuits arranged in at least two columns in parallel so as to surround the outer periphery of each of the matrix array devices.

Further, the inspection circuit section may be arranged in a peripheral region of the insulating substrate so as to surround all the matrix array devices.

Further, the test circuit section may include a test circuit arranged over each of the drive circuit sections in at least two of the matrix array devices.

In the matrix array device according to the present invention, a plurality of gate lines and signal lines are wired on an insulating substrate so as to intersect, and pixel electrodes and switching elements are arranged in a matrix near an intersection between the gate lines and the signal lines. A matrix array portion on which elements are arranged; a gate line drive circuit portion provided on the insulating substrate to drive the gate lines; and a signal line drive circuit portion provided on the insulating substrate and driving the signal lines And provided on the insulating substrate and arranged on one side of at least one of the gate line drive circuit section and the signal line drive circuit section over a length substantially equal to or longer than the side. And a test circuit unit used for testing characteristics of the matrix array unit or the drive circuit unit.

The inspection circuit section may be used for inspection based on the oscillation frequency of the inspection circuit section.

It is desirable that the inspection circuit section includes a CMOS circuit.

Further, the inspection circuit section may include an inverter chain in which a plurality of inverters are connected in cascade. 10. The matrix array device according to claim 9, wherein:

[0040] The matrix array device is used for a liquid crystal display device which is disposed opposite to a counter substrate and holds a liquid crystal composition, and the inspection circuit section is disposed in a region on the insulating substrate which is not opposed to the counter substrate. It may be.

The matrix array device further includes an external circuit provided on a substrate different from the insulating substrate and connected to the drive circuit unit, and the inspection circuit unit is connected to a pad provided on the substrate. You may.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a substrate for a matrix array device according to a first embodiment of the present invention. For example, on a glass substrate 100 having a size of 400 mm * 500 mm,
A plurality of signal lines and gate lines are wired so as to intersect, and pixel electrodes and TFTs as switching elements are arranged in a matrix near the intersection. A gate of the TFT is connected to a corresponding gate line, a source or a drain is connected to a signal line, and a drain or a source is connected to a pixel electrode.

A matrix array section 101 in which pixel electrodes and TFTs are arranged in a matrix, a gate line driving circuit section 102 for supplying a scanning signal to a gate line, and a signal line driving circuit for supplying a video signal to a signal line The portion 103 is formed to constitute a matrix array device, and four such devices are arranged.

The dimensions of each matrix array device are, for example, 180 mm * 220 mm. Further, the side where the gate line driving circuit portion 102 is arranged and the signal line driving circuit portion 103
A plurality of inverters formed of CMOS circuits formed in the same process as the drive circuit units 102 and 103 are cascade-connected along the side where is disposed and over substantially the same length as each side. An inspection circuit unit 104 including an inverter chain is provided.

FIG. 2 shows a specific configuration of the inspection circuit unit 104 arranged along the sides of the drive circuit units 102 and 103. Inverters IN are arranged at substantially equal intervals (for example, at intervals of about 25.8 mm), and the inverters are connected to each other by aluminum wiring having a width of 100 μm and a thickness of 500 nm formed in the same process as the signal line formation. Each inverter I
N is a CM composed of a P-channel transistor PT and an N-channel transistor NT, as shown in FIG.
OS configuration. Each of the P-channel transistor PT and the N-channel transistor NT has, for example, a gate width of 10 μm.
m, and the gate length is 5 μm. Then, the inspection circuit unit 104
Must be set so that the oscillation frequency when a predetermined voltage is applied takes a desired value. For example, the oscillation frequency when a driving voltage Vcc of 10 V is applied is 10 MHz.
Design so that

Then, a predetermined drive voltage Vcc is applied to the test circuit section 104 provided in each matrix array device, and the oscillation frequency is measured using the test terminal 105 to determine the characteristic of each of the drive circuit sections 102 and 103. To inspect.

Thereafter, the substrate 10 for the matrix array device
When 0 is used as an imaging device, a photoelectric conversion film or the like is formed on the surface, and X-rays or the like are applied to inspect the sensitivity or the like. When the substrate 100 is used as a liquid crystal display device, an alignment film is formed on each of the substrate 100 and the counter substrate on which the common electrode is formed, and an alignment process is performed on each of the alignment films.
The two substrate surfaces are opposed to each other, and a gap material, a peripheral sealing material, and a liquid crystal material are sandwiched and adhered to each other. Unnecessary peripheral portions of each substrate are separated to form a liquid crystal display cell, and a lighting image quality inspection is performed. .

The matrix array device substrate 10
When the correlation between the result of measuring the oscillation frequency of the inspection circuit unit 104 at the stage of 0 and the result of the lighting image quality inspection performed after the liquid crystal display cell is created, the oscillation frequency of the inspection circuit unit 104 is, for example, 5 to 20 MHz. At one point, it was found that good display was obtained.

From the above results, it is found that the test circuit section is arranged around the drive circuit section of the matrix array device, and the oscillation frequency of the test circuit section is measured. It has been found that the quality of the object can be grasped easily and with high accuracy.

Here, the inspection circuit section 104 is formed along a side in a region near the gate line drive circuit section 102 and the signal line drive circuit section 103. However, FIG.
As shown in (1), the inspection circuit section 111 may be formed only in the vicinity of one of the gate line drive circuit section 102 and the signal line drive circuit section 103. Further, as shown in FIG. 5, the inspection circuit 112 is provided not only in the gate line driving circuit section 102 and the signal line driving circuit section 103 but also in the vicinity of the matrix array section 101 where the driving circuit sections 102 and 103 are not formed. It may be arranged.

Alternatively, as shown in FIG. 6, the inspection circuit section 12 surrounds the outer periphery of each matrix array device.
1 can also be arranged. As a result of preparing such a matrix array device substrate, measuring the oscillation frequency of the test circuit section 121, and further preparing a liquid crystal display cell using this substrate and performing an image quality test, FIG. The same correlation as the matrix array device substrate shown in FIG. In particular, when the test circuit unit 121 is arranged so as to surround the outer periphery of the matrix array device as in the test circuit unit 121 shown in FIG. 6, the transistor characteristics of not only the drive circuit units 102 and 103 but also the entire device are collectively grasped. It is possible to

In the matrix array device substrate shown in FIG. 7, the inspection circuit section 122 formed so as to surround the outer periphery of the matrix array device has a double inverter chain. In each inverter chain, a plurality of inverters are arranged at equal intervals. Further, each inverter included in one inverter chain is disposed substantially at the center of the interval between the inverters included in the other inverter chain.

A substrate for a matrix array device on which such a test circuit section 122 was formed was prepared, the oscillation frequency of the test circuit section was measured, and a liquid crystal display cell was prepared using this substrate to evaluate the image quality. However, there is still a correlation between the oscillation frequency of the inspection circuit and the lighting image quality inspection result,
It has been found that good display can be obtained when the oscillation frequency of the inspection circuit unit 122 is 10 MHz to 40 MHz.

When the difference between the oscillating frequencies of the double inverter chains exceeds 8%, display defects occur in the liquid crystal display cell due to local variations in transistor characteristics. From this, it is possible to detect the variation in the characteristics with higher accuracy by performing the characteristic inspection using the plurality of inspection circuit units 122 provided with the plurality of inverter chains arranged in parallel as shown in FIG. It turned out to be possible.

FIG. 8 shows a configuration of a substrate for a matrix array device prepared for comparing the present embodiment with the conventional technology. On this substrate, two types of inspection circuit units 12 are provided.
1, 131 are provided. The test circuit section 121 is provided so as to surround the outer periphery of the matrix array section, similarly to the test circuit section shown in FIG. Inspection circuit section 131
Is equivalent to that provided on a conventional substrate for a matrix array device, is composed of 31 inverter chains constituted by CMOS circuits, and is locally disposed at six locations around the matrix array device.

Inspection circuit section 1 according to the first embodiment
When the oscillation frequency of No. 21 was measured, it was 3 MHz, and it was determined that the screen quality was poor when a liquid crystal display cell was formed. On the other hand, when the oscillation frequency of the inspection circuit unit 131 according to the conventional technique was measured, it was found that the frequency was almost 10 MHz in all six places, and that the judgment result that the screen quality was not a problem was obtained. Thereafter, when a liquid crystal display cell was prepared using this substrate and the screen quality was actually evaluated, display unevenness was observed.

The reason why the problem of screen quality could not be detected when the conventional inspection circuit unit 131 was used is that the transistor characteristics varied due to manufacturing process fluctuations in regions other than the six regions where the inspection circuit unit 131 was arranged. I was there. On the other hand, when the test circuit unit 121 according to the first embodiment is used, the transistor in the region where the test circuit unit 131 is not provided is provided by an inverter chain arranged so as to surround the outer periphery of the matrix array device. It can be detected including the variation in characteristics. Therefore, according to the first embodiment, it is possible to detect variations in characteristics existing in the peripheral region where the matrix array device is formed in a wide range and with high accuracy. Furthermore, since the number of times of measuring the oscillation frequency of the inspection circuit unit 121 may be one, the inspection can be performed efficiently.

By the way, in the above-described first embodiment, each of the plurality of matrix array devices formed on the substrate is provided with a separate inspection circuit unit.
On the other hand, in a second embodiment of the present invention described below, an inspection circuit unit is provided so as to be shared by a plurality of matrix array devices.

FIG. 9 shows the configuration of the substrate for a matrix array device according to the present embodiment. As in the first embodiment, for example, a matrix array unit 10 is provided on a matrix array device substrate 100 having a size of 400 mm * 500 mm.
1, gate line drive circuit section 102, signal line drive circuit section 10
3 are formed to constitute a matrix array device, and four such devices are arranged. The dimensions of each matrix array device are, for example, 180 mm * 220 mm.

A CMOS is provided around the outer periphery of the substrate 100 so as to surround the matrix array device arranged on four sides.
An inspection circuit unit 131 is provided which is composed of an inverter chain in which a plurality of inverters formed of circuits are cascaded.

FIG. 10 shows a specific circuit configuration of the inspection circuit section 104. A plurality of inverters are arranged at substantially equal intervals, and the respective inverters are connected by an aluminum wiring having a width of 100 μm and a thickness of 500 nm. Each inverter has a CMOS configuration, and each of the P-channel transistor PT and the N-channel transistor NT has, for example, a gate width of 10 μm and a gate length of 5 μm. Inspection circuit section 131
Is designed so that the oscillation frequency when a driving voltage Vcc of, for example, 10 V is applied is 10 MHz, as in the first embodiment.

Then, similarly to the first embodiment,
At the stage of the matrix array device substrate 100, a predetermined drive voltage Vcc is applied to the inspection circuit section 131, and the oscillation frequency is measured. Thereafter, when the matrix array device substrate is used as an imaging device, a photoelectric conversion film is formed on the surface, and X
Inspection of sensitivity etc. is performed by irradiating a line or the like. When a substrate for a matrix array device is used as a liquid crystal display device, an alignment film is formed on this substrate and on a counter substrate on which a common electrode is formed, and an alignment process is performed on each alignment film. Are opposed to each other, and a gap material, a peripheral sealing material, and a liquid crystal material are adhered so as to be sandwiched therebetween. An unnecessary peripheral portion of each substrate is separated to form a liquid crystal display cell, and a lighting image quality inspection is performed. The correlation between the result of the inspection of the oscillation frequency of the inspection circuit unit 131 and the result of the lighting image quality inspection performed after the liquid crystal display cell is created is obtained, as in the first embodiment. Frequency is for example 5-20M
It was found that when the frequency was in Hz, good display quality was obtained.

From the results, according to the present embodiment, the oscillation frequency of the inspection circuit portion arranged so as to surround the matrix array device is inspected in the outer peripheral region of the substrate for the matrix array device device, whereby each device is inspected. It has been found that the quality of the image quality caused by the variation in the characteristics of the constituent transistors can be grasped efficiently and with high accuracy by one measurement.

Here, the inspection circuit section 131 is formed so as to surround the entire four-sided matrix array device. However, such an arrangement may be difficult due to a space problem of providing an inspection circuit unit on the substrate. In such a case, for example, as shown in FIG.
2, 141-3 may be divided and arranged. The inspection circuit unit 141-1 includes the matrix array devices 101-1 and 1
01-2 is arranged along the side in the vicinity of each of the gate line drive circuit units 102-1 and 102-2, and the inspection circuit unit 141-2 is arranged in each of the matrix array devices 101-3 and 101-4. Are arranged along the gate line drive circuit units 102-3 and 102-4 of
Further, the inspection circuit section 141-3 is a matrix array device 1
Gate line drive circuit section 1 in 01-3 and 101-4
It is arranged along the side opposite to 02-3 and 102-4.

Such a substrate for a matrix array device is prepared, and the inspection circuit units 141-1, 141-2, 141-
As a result of measuring the oscillation frequency of each of No. 3 and evaluating the image quality after forming the liquid crystal display cell using this substrate, the same correlation as that of the matrix array device substrate shown in FIG. 9 was obtained.

Therefore, even in the matrix array device substrate having the inspection circuit sections 141-1, 141-2, 141-3 as shown in FIG.
By measuring each of the oscillation frequencies of (1) to (3), it is possible to grasp variations in transistor characteristics existing on the matrix array device substrate.

Next, a matrix array device according to a third embodiment of the present invention will be described. In the present embodiment, in a matrix array device, a reliability test based on a change in static characteristics of a transistor, which conventionally required a long time, is performed, and a circuit speed is measured based on dynamic characteristics to predict the reliability of the device. Thus, for example, it is possible to guarantee an operation time of at least 10,000 hours or more.

FIG. 12 shows the configuration and appearance of the matrix array device according to the present embodiment, and FIG. 13 shows the block configuration of the device.

The matrix array section 3, the gate line drive circuit section 5a, and the signal line drive circuit section 5b are arranged on an insulating substrate 1 such as glass, and do not face the opposing substrate 2 on the same insulating substrate 1. The inspection circuit unit 4 is arranged in the area. The test circuit section 4 has an inverter chain similarly to the test circuit section in the first embodiment, and FIG. 14A shows an equivalent circuit thereof. A plurality of inverters of a CMOS configuration including a P-channel transistor PT and an N-channel transistor NT are cascaded in a plurality of stages, and a pulse-like voltage of, for example, 5 to 20 V as shown in FIG. Is done. Then, the output voltage Vout of the test circuit section 4 can be taken out from any test pad described later.

An outer terminal bonding pad (hereinafter referred to as OLB) is provided on the matrix array substrate 1.
6). The OLB pad 6 is a pad for connecting the drive circuit units 5a and 5b on the matrix array substrate 1 and the external circuit 9 via a printed wiring board 8 using a flexible substrate or the like.
The external circuit 9 is for controlling the drive circuit units 5a and 5b. Then, in the region where the OLB pad 6 is formed, the test pad 11 connected to the test circuit unit 4 is provided.
Is arranged.

Inspection pad 1 on matrix array substrate 1
1 is connected to a test pad 7 provided on a printed wiring board 8, and the test pad 7 is connected to a test pad 12 provided on an external circuit 9. With such a connection configuration, the inspection circuit section 4 can be formed using either the inspection pad 11 on the matrix array substrate 1, the inspection pad 7 on the printed wiring board 8, or the inspection pad 12 on the external circuit 9. Can be measured.

When a reliability test is performed, a power supply voltage Vcc of, for example, 5 to 20 V is applied to the inspection circuit unit 4. The change with time during the reliability test is measured by monitoring the output voltage Vout of the inspection circuit unit 4 with a synchroscope or the like and reading the oscillation frequency during the test.

As described above, three test pads for monitoring the output voltage Vout are provided on the insulating substrate 1, the printed wiring board 8, and the external circuit 9, respectively. In the array process for forming the matrix array device substrate 1 and the cell process for arranging the opposing substrate 2 to face each other, the inspection pads 11 on the insulating substrate 1 are used. In the module process of mounting each component of the liquid crystal display device including the external circuit 9 after the cell process, either the test pad 7 on the printed wiring board 8 or the test pad 12 on the external circuit 9 is used.

FIG. 15 shows the life time dependence of the oscillation frequency (Δf) before and after the reliability test. In advance, TFT
The relationship between the threshold shift (ΔVth) and the oscillation frequency difference (Δf) is clarified, and as shown in FIG. 15, Δf which is a criterion of pass / fail is set as a standard. If the measured value is within this standard, the operation can be guaranteed for 10,000 hours.

Here, as a condition of the reliability test, unlike the conventional case where the test is performed using the liquid crystal display device main body, the drive voltage applied to the inspection circuit section 4 in the present embodiment is used in the liquid crystal display device. It is desirable to perform an acceleration test set higher than the drive voltage. By using such a drive voltage, the deterioration mode is accelerated as compared with the case where the same voltage as the drive voltage used in the device is used, so that the reliability can be easily predicted in a short time. Also, in the present embodiment, there is almost no increase in the number of parts required for the inspection.
An increase in cost can be prevented.

The above-described embodiments are merely examples, and do not limit the present invention. For example, the arrangement of the inspection circuit portion formed on the matrix array device substrate is as follows.
The present invention is not limited to the one shown in the first embodiment, but may be formed at least over a substantially same length or longer along one side of one of the drive circuit units included in the matrix array device. I just need. Further, the driving circuit portion formed on the substrate for the matrix array device, and the circuit configuration of the driving circuit portion formed in the matrix array device,
The present invention is not limited to the inverter chains in the first and second embodiments, but may be any as long as the characteristics can be evaluated by measuring the oscillation frequency and the like. Further, the first
In this embodiment, four matrix array devices are formed on the matrix array device substrate. However, the number of matrix array devices is not limited to four, and may be one or two or more.

[0078]

As described above, according to the substrate for a matrix array device of the present invention, the inspection circuit portion provided over substantially the same length or longer along at least one side of the drive circuit portion. By using this, it is possible to easily and highly accurately inspect variations in characteristics on the substrate. Further, according to the matrix array device of the present invention, the reliability can be easily evaluated in a short time by using the inspection circuit portion provided on the insulating substrate on which the device is formed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a substrate for a matrix array device according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing a matrix array unit, a driving circuit unit, and an inspection circuit unit formed on the substrate.

FIG. 3 is a circuit diagram showing a configuration of an equivalent circuit of the inspection circuit unit.

FIG. 4 is a plan view showing another example of the arrangement area of the inspection circuit section on the matrix array device substrate.

FIG. 5 is a plan view showing still another example of the arrangement area of the inspection circuit section on the matrix array device substrate.

FIG. 6 is a plan view showing still another example of the arrangement area of the inspection circuit section on the matrix array device substrate.

FIG. 7 is a plan view showing an example of a circuit configuration in which the inverter chains in the inspection circuit section shown in FIG.

FIG. 8 is a plan view showing a matrix array device substrate for evaluation on which the test circuit section according to the above-described embodiment and a conventionally used test circuit section are formed.

FIG. 9 is a plan view showing another example of the arrangement area of the inspection circuit unit according to the embodiment.

FIG. 10 is a circuit diagram showing a configuration of an equivalent circuit of the inspection circuit unit.

FIG. 11 is a plan view showing still another example of the arrangement area of the inspection circuit unit according to the embodiment.

FIG. 12 is a plan view showing the appearance and schematic configuration of a matrix array device according to a second embodiment of the present invention.

FIG. 13 is a block diagram showing a block configuration of the matrix array device.

FIG. 14 is a circuit diagram showing an equivalent circuit of a test circuit unit in the matrix array device.

FIG. 15 is a graph showing a deviation Δf of the oscillation frequency of the inspection circuit unit used when performing a reliability test on the matrix array device with the elapse of life time.

FIG. 16 is a plan view showing a configuration and an arrangement of a matrix array unit, a gate line driving circuit unit, and a signal line driving circuit unit which can be applied to the matrix array device substrate and the matrix array device according to the present invention.

FIG. 17 is a plan view showing the appearance of a matrix array device substrate on which a conventional inspection circuit is formed.

FIG. 18 is a graph showing a relationship between a cumulative failure rate and a test time when a reliability test is performed in a conventional matrix array device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Counter substrate 3 Matrix array part 4, 104, 111, 112, 121, 122, Inspection circuit part 5a, 102 Gate line drive circuit part 5b, 103 Scan line drive circuit part 6 OLB pad area 7, 11, 12 Test pad 100 Matrix array device substrate 101 Matrix array unit 105 Test terminal IN Inverter PT P-channel transistor NT N-channel transistor

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/30 338 G02F 1/136 500 5G435 9A001 (72) Inventor Ryoichi Watanabe Hatara-cho, Fukaya-shi, Saitama 1-9-2 Toshiba Fukaya Factory Co., Ltd. (72) Inventor: Manabu Watanabe 1-9-2 Hara-cho, Fukaya City, Saitama Prefecture F-term Fukaya Factory Co., Ltd. 2G032 AB02 AC05 AK11 2G036 AA06 AA19 CA07 2H088 FA11 HA06 HA08 MA20 2H092 JA24 JB77 MA56 NA29 NA30 PA06 5C094 AA31 AA42 AA43 AA46 AA48 BA03 BA43 CA19 DA09 EA03 FA01 GB10 5G435 AA14 AA17 BB12 CC09 GG21 KK05 9A001 BB04 KK15 KK31 KK37 LL05

Claims (14)

[Claims] 1. A matrix in which a plurality of gate lines and signal lines are wired on an insulating substrate so as to intersect, and pixel electrodes and switching elements are arranged in a matrix near an intersection of the gate lines and the signal lines. An array unit, a gate line drive circuit unit provided on the insulating substrate and driving the gate line, a signal line drive circuit unit provided on the insulating substrate and driving the signal line, and on the insulating substrate The gate line drive circuit portion and the signal line drive circuit portion, at least one side of the drive circuit portion, is disposed over substantially the same or longer length of the side, the matrix array portion or A substrate for a matrix array device, comprising: a test circuit unit used for testing characteristics of the drive circuit unit. 2. The test circuit according to claim 1, wherein the test circuit is used based on an oscillation frequency of the test circuit.
The substrate for a matrix array device according to the above. 3. A plurality of matrix array devices each having the matrix array unit, the gate line driving circuit unit, and the signal line driving circuit unit are provided on the same insulating substrate, and the inspection circuit unit is provided for each of the matrix array devices. The substrate for a matrix array device according to claim 1, wherein the substrate is provided on a substrate. 4. The matrix array device according to claim 1, wherein said inspection circuit section is arranged adjacent to one side of said drive circuit section and along the same direction. Substrate. 5. The substrate for a matrix array device according to claim 3, wherein said inspection circuit portion is arranged so as to surround an outer periphery of each of said matrix array devices. 6. The matrix array device according to claim 3, wherein said test circuit section includes test circuits arranged in at least two columns in parallel so as to surround an outer periphery of each of said matrix array devices. substrate. 7. The substrate for a matrix array device according to claim 3, wherein the inspection circuit section is arranged in a peripheral region of the insulating substrate so as to surround all the matrix array devices. 8. The matrix array device according to claim 3, wherein the test circuit portion includes a test circuit arranged over each of the drive circuit portions in at least two of the matrix array devices. substrate. 9. A matrix in which a plurality of gate lines and signal lines are wired so as to intersect on an insulating substrate, and pixel electrodes and switching elements are arranged in a matrix near an intersection between the gate lines and the signal lines. An array unit, a gate line drive circuit unit provided on the insulating substrate and driving the gate line, a signal line drive circuit unit provided on the insulating substrate and driving the signal line, and on the insulating substrate The gate line drive circuit portion and the signal line drive circuit portion, at least one side of the drive circuit portion, is disposed over substantially the same or longer length of the side, the matrix array portion or A test circuit unit used for testing characteristics of the drive circuit unit. 10. The matrix array device according to claim 9, wherein said inspection circuit section is used for inspection based on an oscillation frequency of said inspection circuit section. 11. The matrix array device according to claim 9, wherein said inspection circuit section includes a CMOS circuit. 12. The matrix array device according to claim 11, wherein said inspection circuit section includes an inverter chain in which a plurality of inverters are connected in cascade. 13. The matrix array device is used in a liquid crystal display device that is disposed to face a counter substrate and sandwiches a liquid crystal composition, and the inspection circuit section is a region on the insulating substrate that does not face the counter substrate. 13. The matrix array device according to claim 9, wherein the matrix array device is arranged in a matrix. 14. The matrix array device further includes an external circuit provided on a substrate different from the insulating substrate and connected to the drive circuit unit, wherein the inspection circuit unit is connected to a pad provided on the substrate. The matrix array device according to any one of claims 9 to 13, wherein