JP2001007389A - Manufacturing semiconductor light emitting element - Google Patents
Manufacturing semiconductor light emitting elementInfo
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- JP2001007389A JP2001007389A JP17413899A JP17413899A JP2001007389A JP 2001007389 A JP2001007389 A JP 2001007389A JP 17413899 A JP17413899 A JP 17413899A JP 17413899 A JP17413899 A JP 17413899A JP 2001007389 A JP2001007389 A JP 2001007389A
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- light emitting
- type
- transparent substrate
- layer
- substrate
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、透明基板を用いた
発光素子の製造方法に係わり、特に、発光素子のエピタ
キシャル膜に透明基板を接着する半導体発光素子の製造
方法に関する。The present invention relates to a method for manufacturing a light emitting device using a transparent substrate, and more particularly, to a method for manufacturing a semiconductor light emitting device in which a transparent substrate is bonded to an epitaxial film of the light emitting device.
【０００２】[0002]
【従来の技術】この種の透明基板を用いた半導体発光ダ
イオード（ＬＥＤ）は、例えば４元ＩｎＧａＡｌＰ系の
ＬＥＤ発光素子部の一方面及び他方面に透明基板が形成
されている。前記４元組成比を変えることで全可視光領
域のＬＥＤを作成することが可能である。しかし、透明
基板と発光素子部の格子定数が一致しないため格子整合
しない。そのため、発光素子部を透明基板上に直接形成
した場合、透明基板上に良好なエピタキシャル膜を形成
することが困難である。2. Description of the Related Art In a semiconductor light emitting diode (LED) using a transparent substrate of this kind, for example, a transparent substrate is formed on one surface and the other surface of a quaternary InGaAlP-based LED light emitting element. By changing the quaternary composition ratio, it is possible to produce an LED in the entire visible light region. However, since the lattice constants of the transparent substrate and the light emitting element do not match, there is no lattice matching. Therefore, when the light emitting element portion is formed directly on the transparent substrate, it is difficult to form a good epitaxial film on the transparent substrate.
【０００３】従って、図８乃至図１４に示すように、Ｇ
ａＡｓ基板上に発光素子部をエピタキシャル成長した後
に、ＧａＡｓ基板を除去し、発光素子部の一方面及び他
方面に順次に透明基板を形成することが一般的である。
以下に、従来の半導体発光素子の製造方法について説明
する。Accordingly, as shown in FIGS.
In general, after a light emitting element portion is epitaxially grown on an aAs substrate, the GaAs substrate is removed, and a transparent substrate is sequentially formed on one surface and the other surface of the light emitting element portion.
Hereinafter, a method for manufacturing a conventional semiconductor light emitting device will be described.
【０００４】まず、図８に示すように、ＧａＡｓ基板３
１上にエッチングストップ層３２が形成され、エッチン
グストップ層３２上にｐ型クラッド層３３が形成され
る。このｐ型クラッド層３３上に活性層３４が形成さ
れ、活性層３４上にｎ型クラッド層３５が形成される。
このｎ型クラッド層３５上にキャップ層３６が形成され
る。このように、エピタキシャル成長によって発光素子
部が形成される。[0004] First, as shown in FIG.
1, an etching stop layer 32 is formed, and a p-type cladding layer 33 is formed on the etching stop layer 32. An active layer 34 is formed on the p-type cladding layer 33, and an n-type cladding layer 35 is formed on the active layer 34.
On this n-type cladding layer 35, a cap layer 36 is formed. Thus, the light emitting element section is formed by epitaxial growth.
【０００５】図９に示すように、エッチングによりキャ
ップ層３６が除去され、ｎ型クラッド層３５の表面が露
出される。[0005] As shown in FIG. 9, the cap layer 36 is removed by etching, and the surface of the n-type cladding layer 35 is exposed.
【０００６】図１０に示すように、エピタキシャル成長
により、ｎ型クラッド層３５の表面に膜厚が例えば１０
乃至５０μｍのｎ型透明基板３７が形成される。[0006] As shown in FIG. 10, a film thickness of, for example, 10
An n-type transparent substrate 37 of about 50 μm is formed.
【０００７】図１１に示すように、エッチングによりＧ
ａＡｓ基板３１が除去され、エッチングストップ層３２
の表面が露出される。[0007] As shown in FIG.
The aAs substrate 31 is removed, and the etching stop layer 32 is removed.
Surface is exposed.
【０００８】図１２に示すように、エッチングによりエ
ッチングストップ層３２が除去され、ｐ型クラッド層３
３の表面が露出される。As shown in FIG. 12, the etching stop layer 32 is removed by etching, and the p-type cladding layer 3 is removed.
3 is exposed.
【０００９】図１３に示すように、熱圧着により、ｐ型
クラッド層３３の表面に膜厚が例えば２５０μｍのｐ型
透明基板３８が接着される。As shown in FIG. 13, a p-type transparent substrate 38 having a thickness of, for example, 250 μm is adhered to the surface of the p-type cladding layer 33 by thermocompression bonding.
【００１０】図１４に示すように、ｎ型透明基板３７及
びｐ型透明基板３８の表面に、それぞれ金属電極３９及
び４０が形成される。As shown in FIG. 14, metal electrodes 39 and 40 are formed on the surfaces of an n-type transparent substrate 37 and a p-type transparent substrate 38, respectively.
【００１１】[0011]
【発明が解決しようとする課題】上記従来の半導体発光
素子の製造方法において、ｐ型クラッド層３３とｐ型透
明基板３８の接着面が良好なオーミックになるために
は、高温な熱圧着により接着することが必要である。し
かし、エピタキシャル成長膜であるｎ型透明基板３７の
膜厚はｐ型透明基板３８の膜厚に比べて薄いため、熱圧
着によりｐ型クラッド層３３表面にｐ型透明基板３８を
接着して、発光素子部を透明基板３７、３８で挟み込む
際、クラッド層３３及び３５と透明基板３８及び３７の
熱膨張係数の差による応力が発生する。主に、透明基板
３７、３８の膜厚差により、発生した応力が打ち消し合
わず、図１５に示すように、発光素子部に反りが生じて
クラック４０が発生する。従って、ＬＥＤの発光特性が
大幅に劣化するという問題があった。In the conventional method of manufacturing a semiconductor light emitting device, in order to make the bonding surface between the p-type cladding layer 33 and the p-type transparent substrate 38 good ohmic, the bonding is performed by high-temperature thermocompression bonding. It is necessary to. However, since the thickness of the n-type transparent substrate 37, which is an epitaxial growth film, is thinner than the thickness of the p-type transparent substrate 38, the p-type transparent substrate 38 is bonded to the surface of the p-type cladding layer 33 by thermocompression bonding to emit light. When the element portion is sandwiched between the transparent substrates 37, 38, a stress is generated due to a difference in thermal expansion coefficient between the cladding layers 33, 35 and the transparent substrates 38, 37. Mainly, due to the difference in film thickness between the transparent substrates 37 and 38, the generated stresses do not cancel each other, and as shown in FIG. 15, the light emitting element portion is warped and cracks 40 are generated. Therefore, there is a problem that the light emission characteristics of the LED are significantly deteriorated.
【００１２】これを解決するためには、ｎ型透明基板３
７の膜厚をｐ型透明基板３８の膜厚と同一にすることが
考えられる。しかし、これはエピタキシャル成長の時間
を長くする必要があるため、処理時間が長くなり、得策
ではない。In order to solve this, the n-type transparent substrate 3
It is conceivable to make the film thickness of 7 the same as the film thickness of the p-type transparent substrate 38. However, this requires a longer epitaxial growth time, which increases the processing time, which is not advantageous.
【００１３】本発明は上記課題を解決するためになされ
たものであり、その目的とするところは、発光素子部の
クラックの発生を抑制することができる半導体発光素子
の製造方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor light emitting device which can suppress the occurrence of cracks in a light emitting device portion. is there.
【００１４】[0014]
【課題を解決するための手段】本発明は、前記目的を達
成するために以下に示す手段を用いている。The present invention uses the following means to achieve the above object.
【００１５】本発明の半導体発光素子の製造方法は、透
明基板を接着する半導体発光素子の製造方法であって、
発光素子部を透明基板で両側から挟み、これらを高温処
理して接着する。The method for manufacturing a semiconductor light emitting device of the present invention is a method for manufacturing a semiconductor light emitting device for bonding a transparent substrate,
The light emitting element portion is sandwiched between the transparent substrates from both sides, and these are subjected to high temperature treatment and bonded.
【００１６】前記高温処理は、前記発光素子部及び両側
の前記透明基板を一括して処理し接着する。In the high temperature treatment, the light emitting element portion and the transparent substrates on both sides are collectively processed and bonded.
【００１７】また、本発明の半導体発光素子の製造方法
は、透明基板を接着する半導体発光素子の製造方法であ
って、化合物半導体基板の表面に発光素子部をエピタキ
シャル成長させる工程と、室温で、前記発光素子部の一
方面に第１の透明基板を接着する工程と、前記化合物半
導体基板を除去し、前記発光素子部の他方面を露出する
工程と、室温で、前記発光素子部の他方面に第２の透明
基板を接着する工程と、前記第１及び第２の透明基板と
前記発光素子を高温処理し、これらを接着する工程とを
含む。Further, a method of manufacturing a semiconductor light emitting device according to the present invention is a method of manufacturing a semiconductor light emitting device in which a transparent substrate is adhered, wherein a step of epitaxially growing a light emitting element portion on a surface of a compound semiconductor substrate comprises: A step of bonding a first transparent substrate to one surface of the light emitting element portion, a step of removing the compound semiconductor substrate and exposing the other surface of the light emitting element portion, and a step of bonding the other surface of the light emitting element portion at room temperature. A step of bonding a second transparent substrate; and a step of subjecting the first and second transparent substrates and the light emitting element to high-temperature treatment and bonding them.
【００１８】前記高温処理の温度は５００℃乃至１２０
０℃である。The temperature of the high temperature treatment is 500 ° C. to 120 ° C.
0 ° C.
【００１９】[0019]
【発明の実施の形態】本発明の実施の形態を以下に図面
を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００２０】図１乃至図６は、本発明を例えば緑色の半
導体発光素子の製造方法に適用した場合について示して
いる。FIGS. 1 to 6 show a case where the present invention is applied to, for example, a method for manufacturing a green semiconductor light emitting device.
【００２１】まず、図１に示すように、膜厚が例えば２
５０μｍのＧａＡｓ基板１１上に、膜厚が例えば０．５
μｍのｎ型ＧａＡｓ層１２が形成され、このｎ型ＧａＡ
ｓ層１２上に、膜厚が例えば０．２μｍのｎ型Ｉｎ0.5
Ｇａ0.5Ｐ層１３が形成される。このｎ型Ｉｎ0.5Ｇａ
0.5Ｐ層１３上に、膜厚が例えば０．６μｍのｎ型クラ
ッド層（Ｉｎ0.5Ａｌ0.5Ｐ層）１４が形成され、このｎ
型クラッド層１４上に、膜厚が例えば１．０μｍのＰ型
活性層（Ｉｎ0.5（Ｇａ0.55Ａｌ0.45）0.5Ｐ層、Ｐ型濃
度が５×１０16乃至２×１０17ｃｍ-3）１５が形成され
る。このＰ型活性層１５上に、膜厚が例えば１．０μｍ
のＰ型クラッド層（Ｉｎ0.5Ａｌ0.5Ｐ層）１６が形成さ
れ、このＰ型クラッド層１６上に、膜厚が例えば０．０
１μｍのＰ型エッチングストップ層（ＧａＡｓ層）１７
が形成される。このエッチングストップ層１７上に、膜
厚が例えば０．０２μｍのｎ型キャップ層（Ｉｎ
0.5（Ｇａ0.7Ａｌ0.3）0.5Ｐ層）１８が形成される。こ
のように、エピタキシャル成長によって、同一バッチで
発光素子部が形成される。First, as shown in FIG.
On a GaAs substrate 11 having a thickness of 50 μm,
A μm n-type GaAs layer 12 is formed.
An n-type In 0.5 layer having a thickness of, for example, 0.2 μm is formed on the s layer 12.
A Ga 0.5 P layer 13 is formed. This n-type In 0.5 Ga
An n-type cladding layer (In 0.5 Al 0.5 P layer) 14 having a thickness of, for example, 0.6 μm is formed on the 0.5 P layer 13.
A P-type active layer (In 0.5 (Ga 0.55 Al 0.45 ) 0.5 P layer, P-type concentration of 5 × 10 16 to 2 × 10 17 cm −3 ) having a thickness of, for example, 1.0 μm is formed on the mold cladding layer 14. Is formed. On this P-type active layer 15, a film thickness of, for example, 1.0 μm
A P-type clad layer (In 0.5 Al 0.5 P layer) 16 is formed, and a thickness of, for example, 0.0
1 μm P-type etching stop layer (GaAs layer) 17
Is formed. On this etching stop layer 17, an n-type cap layer (In
0.5 (Ga 0.7 Al 0.3 ) 0.5 P layer) 18 is formed. As described above, the light emitting element portion is formed in the same batch by the epitaxial growth.
【００２２】次に、図２に示すように、ｎ型キャップ層
１８とｐ型エッチングストップ層１７がエッチングさ
れ、ｐ型クラッド層１６の表面が露出される。その後、
露出されたｐ型クラッド層１６上に形成された自然酸化
膜（図示せず）及びｐ型クラッド層１６表面のパーティ
クルが除去される。また、図３に示すｐ型クラッド層１
６に接着されるｐ型透明基板（ＧａＰ基板）１９表面の
自然酸化膜及びパーティクルも予め除去される。このｐ
型透明基板１９は、発光素子部とは別の製造工程で製造
される。Next, as shown in FIG. 2, the n-type cap layer 18 and the p-type etching stop layer 17 are etched, and the surface of the p-type cladding layer 16 is exposed. afterwards,
The natural oxide film (not shown) formed on the exposed p-type cladding layer 16 and particles on the surface of the p-type cladding layer 16 are removed. Further, the p-type cladding layer 1 shown in FIG.
A natural oxide film and particles on the surface of the p-type transparent substrate (GaP substrate) 19 adhered to 6 are also removed in advance. This p
The mold transparent substrate 19 is manufactured in a different manufacturing process from the light emitting element section.
【００２３】この後、図３に示すように、室温で、ｐ型
クラッド層１６の表面に、膜厚が例えば２５０μｍのｐ
型透明基板１９の表面が接着される。Thereafter, as shown in FIG. 3, a p-type cladding layer 16 having a thickness of, for example, 250 μm is formed on the surface of the p-type cladding layer 16 at room temperature.
The surface of the mold transparent substrate 19 is bonded.
【００２４】次に、図４に示すように、エッチングによ
りｎ型Ｉｎ0.5Ｇａ0.5Ｐ１３下部のＧａＡｓ基板１１及
びｎ型ＧａＡｓ層１２が除去される。Next, as shown in FIG. 4, the GaAs substrate 11 and the n-type GaAs layer 12 under the n-type In 0.5 Ga 0.5 P 13 are removed by etching.
【００２５】この後、図５に示すｎ型Ｉｎ0.5Ｇａ0.5Ｐ
１３に接着されるｎ型透明基板（ＧａＰ基板）２０の表
面の自然酸化膜（図示せず）及びパーティクルが予め除
去される。このｎ型透明基板２０は、発光素子部とは別
の製造工程で製造される。Thereafter, the n-type In 0.5 Ga 0.5 P shown in FIG.
A natural oxide film (not shown) and particles on the surface of an n-type transparent substrate (GaP substrate) 20 adhered to 13 are removed in advance. This n-type transparent substrate 20 is manufactured in a manufacturing process different from that of the light emitting element section.
【００２６】この後、図５に示すように、室温で、ｎ型
Ｉｎ0.5Ｇａ0.5Ｐ１３の表面に、膜厚が例えば２５０μ
ｍのｎ型透明基板２０が接着される。Thereafter, as shown in FIG. 5, at room temperature, a film having a thickness of, for example, 250 μm is formed on the surface of the n-type In 0.5 Ga 0.5 P13.
The m-type n-type transparent substrate 20 is bonded.
【００２７】次に、Ａｒガスを流しながら、例えば８０
０℃に加熱され、ｐ型クラッド層１６とｐ型透明基板１
９の接着面、ｎ型Ｉｎ0.5Ｇａ0.5Ｐ１３を介してｎ型ク
ラッド層１４とｎ型透明基板２０の接着面が一括して高
温接着される。その後、室温で上記ウエハが冷却され
る。尚、高温の接着時の温度としては、８００℃に限定
されるわけではなく、例えば５００℃乃至１２００℃で
あればよい。Next, while flowing Ar gas, for example, 80
Heated to 0 ° C., the p-type cladding layer 16 and the p-type transparent substrate 1
The bonding surface 9 and the bonding surface of the n-type cladding layer 14 and the n-type transparent substrate 20 are bonded together at a high temperature via the n-type In 0.5 Ga 0.5 P13. Thereafter, the wafer is cooled at room temperature. In addition, the temperature at the time of high-temperature bonding is not limited to 800 ° C., and may be, for example, 500 ° C. to 1200 ° C.
【００２８】次に、図６に示すように、ｎ型透明基板２
０上に、膜厚が例えば１乃至１０ｎｍのＧｅを含むＡｕ
（例えばＧｅを０．５％含有するＡｕＧｅ）からなる介
在層２１が形成される。Next, as shown in FIG.
Au containing Ge having a thickness of, for example, 1 to 10 nm
The intervening layer 21 made of (for example, AuGe containing 0.5% of Ge) is formed.
【００２９】次に、スパッタリングにより、介在層２１
上にＩＴＯ（Ｉｎ酸化膜とＳｎ酸化膜の混合膜）膜から
なる透明電極２２が形成される。この際、基板温度は室
温（２２℃）程度で、ＡｒとＯの比（Ａｒ：Ｏ）は例え
ば１００：１とし、真空度は例えば１×１０-3Ｔｏｒｒ
とする。Next, the intermediate layer 21 is formed by sputtering.
A transparent electrode 22 made of an ITO (a mixed film of an In oxide film and a Sn oxide film) is formed thereon. At this time, the substrate temperature is about room temperature (22 ° C.), the ratio of Ar to O (Ar: O) is, for example, 100: 1, and the degree of vacuum is, for example, 1 × 10 −3 Torr.
And
【００３０】次に、透明電極２２上に例えばＡｕからな
る金属電極２３が形成され、ｐ型透明基板１９の表面
に、例えばＢｅを１％含有するＡｕＢｅからなる裏面電
極２４が形成される。その後、Ａｒ雰囲気中で温度が例
えば４５０℃、処理時間が例えば１５分の熱処理が行わ
れる。Next, a metal electrode 23 made of, for example, Au is formed on the transparent electrode 22, and a back electrode 24 made of, for example, AuBe containing 1% of Be is formed on the surface of the p-type transparent substrate 19. Thereafter, heat treatment is performed in an Ar atmosphere at a temperature of, for example, 450 ° C. and a processing time of, for example, 15 minutes.
【００３１】次に、ウエハにスクライブが行われ、チッ
プ化される。その後、樹脂パッケージにより封止され
る。Next, the wafer is scribed to be chipped. Then, it is sealed with a resin package.
【００３２】上記実施の形態によれば、ｐ型クラッド層
１６にｐ型透明基板１９を接着するとともに、このｐ型
透明基板１９と同一の膜厚のｎ型透明基板２０をｎ型Ｉ
ｎ0. 5Ｇａ0.5Ｐ１３を介してｎ型クラッド層１４に接着
している。つまり、ｐ型透明基板１９とｎ型クラッド層
１４の膜厚は同一であるため、高温接着から室温冷却の
際、異種材料からなる透明基板１９及び２０とクラッド
層１６及び１４の熱膨張係数の差により生じたストレス
を、互いに打ち消し合うことができる。このため、発光
素子部の反り及びクラックの発生を抑制することができ
る。According to the above embodiment, the p-type transparent substrate 19 is bonded to the p-type cladding layer 16 and the n-type transparent substrate 20 having the same thickness as the p-type transparent substrate 19 is formed on the n-type I-type substrate.
adhering to the n-type cladding layer 14 through the n 0. 5 Ga 0.5 P13. In other words, since the p-type transparent substrate 19 and the n-type cladding layer 14 have the same thickness, when the substrate is cooled from room temperature to room temperature, the thermal expansion coefficients of the transparent substrates 19 and 20 and the cladding layers 16 and 14 made of different materials are different. The stress caused by the difference can be canceled by each other. For this reason, the occurrence of warpage and cracks in the light emitting element portion can be suppressed.
【００３３】また、図７は、透明基板を接着する前と接
着した後のＬＥＤの発光輝度の様子を示している。この
実施の形態によれば、ＬＥＤに反りやクラックが発生し
ないため、同図に示すように、透明基板を接着した後も
発光輝度が低下しない。このため、ＬＥＤ特性の劣化を
防止できる。FIG. 7 shows the light emission luminance of the LED before and after the transparent substrate is bonded. According to this embodiment, since the LED does not warp or crack, the light emission luminance does not decrease even after the transparent substrate is bonded as shown in FIG. For this reason, deterioration of LED characteristics can be prevented.
【００３４】また、透明基板１９及び２０とクラッド層
１６及び１４を高温で接着する際に、接着時の温度が５
００℃乃至１２００℃の範囲であれば、接着面は良好な
オーミックとなる。When bonding the transparent substrates 19 and 20 and the cladding layers 16 and 14 at a high temperature, the bonding temperature is
When the temperature is in the range of 00 ° C. to 1200 ° C., the bonding surface becomes a good ohmic.
【００３５】また、透明基板１９、２０の接着により発
光素子部を挟み込むため、透明基板をエピタキシャル成
長膜により形成する場合よりも処理時間を短縮できる。Further, since the light emitting element portion is sandwiched between the transparent substrates 19 and 20 by bonding, the processing time can be reduced as compared with the case where the transparent substrate is formed by an epitaxial growth film.
【００３６】更に、処理時間をかけることなく透明基板
１９、２０の膜厚を例えば２５０μｍと厚く形成でき
る。しかも、透明基板１９、２０の膜厚が厚いため、透
明基板１９、２０の側面の面積を広くできる。従って、
透明基板１９、２０による反射面が広いため、側面に反
射された光を有効に活用できる。よって、ＬＥＤの発光
輝度を高めることができる。Further, the transparent substrates 19 and 20 can be formed to have a large thickness of, for example, 250 μm without taking any processing time. Moreover, since the thickness of the transparent substrates 19 and 20 is large, the area of the side surfaces of the transparent substrates 19 and 20 can be increased. Therefore,
Since the reflection surfaces of the transparent substrates 19 and 20 are wide, light reflected on the side surfaces can be effectively used. Therefore, the light emission luminance of the LED can be increased.
【００３７】尚、本発明は、上記実施の形態に限定され
るものではない。例えば、ＬＥＤとしては、緑以外の可
視光製品にも適用でき、上記と同様の効果を得ることが
できる。The present invention is not limited to the above embodiment. For example, as an LED, the present invention can be applied to visible light products other than green, and the same effects as described above can be obtained.
【００３８】また、透明基板１９、２０はＧａＰ基板に
限る必要はなく、例えばＧａＮ基板のように、導電性で
あり、且つ、可視領域で透明（透過率９０％以上）であ
る材料であればよい。The transparent substrates 19 and 20 need not be limited to GaP substrates, but may be made of any material, such as a GaN substrate, which is conductive and transparent in the visible region (transmittance of 90% or more). Good.
【００３９】その他、本発明は、その要旨を逸脱しない
範囲で、種々変形して実施することが可能である。In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
【００４０】[0040]
【発明の効果】以上説明したように本発明によれば、発
光素子部のクラックの発生を抑制することができる半導
体発光素子の製造方法を提供できる。As described above, according to the present invention, it is possible to provide a method for manufacturing a semiconductor light emitting device which can suppress the occurrence of cracks in the light emitting device portion.
【図１】本発明に係わる半導体発光素子の製造工程を示
す断面図。FIG. 1 is a sectional view showing a manufacturing process of a semiconductor light emitting device according to the present invention.
【図２】本発明に係わる半導体発光素子の製造工程を示
す断面図。FIG. 2 is a sectional view showing a manufacturing process of the semiconductor light emitting device according to the present invention.
【図３】本発明に係わる半導体発光素子の製造工程を示
す断面図。FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor light emitting device according to the present invention.
【図４】本発明に係わる半導体発光素子の製造工程を示
す断面図。FIG. 4 is a sectional view showing a manufacturing process of the semiconductor light emitting device according to the present invention.
【図５】本発明に係わる半導体発光素子の製造工程を示
す断面図。FIG. 5 is a sectional view showing a manufacturing process of the semiconductor light emitting device according to the present invention.
【図６】本発明に係わる半導体発光素子の製造工程を示
す断面図。FIG. 6 is a sectional view showing a step of manufacturing the semiconductor light emitting device according to the present invention.
【図７】本発明のＬＥＤの発光輝度特性を示す図。FIG. 7 is a graph showing emission luminance characteristics of the LED of the present invention.
【図８】従来技術による半導体発光素子の製造工程を示
す断面図。FIG. 8 is a cross-sectional view illustrating a manufacturing process of a semiconductor light emitting device according to a conventional technique.
【図９】従来技術による半導体発光素子の製造工程を示
す断面図。FIG. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor light emitting device according to a conventional technique.
【図１０】従来技術による半導体発光素子の製造工程を
示す断面図。FIG. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor light emitting device according to a conventional technique.
【図１１】従来技術による半導体発光素子の製造工程を
示す断面図。FIG. 11 is a cross-sectional view illustrating a manufacturing process of a semiconductor light emitting device according to a conventional technique.
【図１２】従来技術による半導体発光素子の製造工程を
示す断面図。FIG. 12 is a cross-sectional view illustrating a manufacturing process of a semiconductor light emitting device according to a conventional technique.
【図１３】従来技術による半導体発光素子の製造工程を
示す断面図。FIG. 13 is a cross-sectional view showing a manufacturing process of a semiconductor light emitting device according to a conventional technique.
【図１４】従来技術による半導体発光素子の製造工程を
示す断面図。FIG. 14 is a cross-sectional view illustrating a manufacturing process of a semiconductor light emitting device according to a conventional technique.
【図１５】従来技術によるクラックを示す断面図。FIG. 15 is a sectional view showing a crack according to a conventional technique.
１１…ＧａＡｓ基板、 １２…ｎ型ＧａＡｓ基板、 １３…ｎ型Ｉｎ0.5Ｇａ0.5Ｐ層、 １４…ｎ型クラッド層（Ｉｎ0.5Ａｌ0.5Ｐ層）、 １５…Ｐ型活性層（Ｉｎ0.5（Ｇａ0.55Ａｌ0.45）0.5Ｐ
層）、 １６…Ｐ型クラッド層（Ｉｎ0.5Ａｌ0.5Ｐ層）、 １７…Ｐ型エッチングストップ層（ＧａＡｓ層）、 １８…ｎ型キャップ層（Ｉｎ0.5（Ｇａ0.7Ａｌ0.3）0.5
Ｐ層）、 １９…ｐ型透明基板（ＧａＰ基板）、 ２０…ｎ型透明基板（ＧａＰ基板）、 ２１…介在層、 ２２…透明電極、 ２３…金属電極、 ２４…裏面電極。11 GaAs substrate, 12 n-type GaAs substrate, 13 n-type In 0.5 Ga 0.5 P layer, 14 n-type clad layer (In 0.5 Al 0.5 P layer), 15 P-type active layer (In 0.5 (Ga 0.55 Al 0.45 ) 0.5 P
16) P-type cladding layer (In 0.5 Al 0.5 P layer) 17: P-type etching stop layer (GaAs layer) 18: n-type cap layer (In 0.5 (Ga 0.7 Al 0.3 ) 0.5
P layer), 19 p-type transparent substrate (GaP substrate), 20 n-type transparent substrate (GaP substrate), 21 intervening layer, 22 transparent electrode, 23 metal electrode, 24 back electrode.
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F041 AA41 AA43 CA04 CA12 CA34 CA35 CA37 CA74 CA76 CA85 CA88 CA92 DA12 DA43 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F041 AA41 AA43 CA04 CA12 CA34 CA35 CA37 CA74 CA76 CA85 CA88 CA92 DA12 DA43
Claims (4)
造方法であって、 発光素子部を透明基板で両側から挟み、これらを高温処
理して接着することを特徴とする半導体発光素子の製造
方法。1. A method of manufacturing a semiconductor light emitting device, comprising: bonding a transparent substrate to a transparent substrate; .
側の前記透明基板を一括して処理し接着することを特徴
とする請求項１記載の半導体発光素子の製造方法。2. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein said high-temperature processing is to collectively process and bond said light emitting element portion and said transparent substrates on both sides.
造方法であって、 化合物半導体基板の表面に発光素子部をエピタキシャル
成長させる工程と、 室温で、前記発光素子部の一方面に第１の透明基板を接
着する工程と、 前記化合物半導体基板を除去し、前記発光素子部の他方
面を露出する工程と、 室温で、前記発光素子部の他方面に第２の透明基板を接
着する工程と、 前記第１及び第２の透明基板と前記発光素子を高温処理
し、これらを接着する工程とを含むことを特徴とする半
導体発光素子の製造方法。3. A method of manufacturing a semiconductor light emitting device, wherein a transparent substrate is adhered, wherein a step of epitaxially growing a light emitting device portion on a surface of a compound semiconductor substrate; Bonding a substrate; removing the compound semiconductor substrate to expose the other surface of the light emitting element unit; and bonding a second transparent substrate to the other surface of the light emitting element unit at room temperature. A process of subjecting the first and second transparent substrates and the light emitting device to high-temperature treatment and bonding them to each other.
００℃であることを特徴とする請求項１又は３記載の半
導体発光素子の製造方法。4. The temperature of the high-temperature treatment is 500 ° C. to 12 ° C.
The method according to claim 1, wherein the temperature is 00 ° C. 5.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17413899A JP2001007389A (en) | 1999-06-21 | 1999-06-21 | Manufacturing semiconductor light emitting element |
| DE60042187T DE60042187D1 (en) | 1999-06-09 | 2000-06-08 | Bond-type semiconductor substrate, semiconductor light-emitting device, and manufacturing method |
| EP00304862A EP1065734B1 (en) | 1999-06-09 | 2000-06-08 | Bonding type semiconductor substrate, semiconductor light emitting element, and preparation process thereof. |
| TW089111181A TW502458B (en) | 1999-06-09 | 2000-06-08 | Bonding type semiconductor substrate, semiconductor light emission element and manufacturing method thereof |
| US09/589,452 US6465809B1 (en) | 1999-06-09 | 2000-06-08 | Bonding type semiconductor substrate, semiconductor light emitting element, and preparation process thereof |
| US10/211,707 US6815312B2 (en) | 1999-06-09 | 2002-08-05 | Bonding type semiconductor substrate, semiconductor light emitting element, and preparation process thereof |
| US10/961,066 US7217635B2 (en) | 1999-06-09 | 2004-10-12 | Process for preparing a bonding type semiconductor substrate |
| US11/621,638 US7364982B2 (en) | 1999-06-09 | 2007-01-10 | Process for preparing a bonding type semiconductor substrate |
| US12/042,561 US20080308827A1 (en) | 1999-06-09 | 2008-03-05 | Process for preparing a bonding type semiconductor substrate |
| US13/595,284 US8829488B2 (en) | 1999-06-09 | 2012-08-27 | Process for preparing a bonding type semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17413899A JP2001007389A (en) | 1999-06-21 | 1999-06-21 | Manufacturing semiconductor light emitting element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001007389A true JP2001007389A (en) | 2001-01-12 |
Family
ID=15973337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17413899A Pending JP2001007389A (en) | 1999-06-09 | 1999-06-21 | Manufacturing semiconductor light emitting element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001007389A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100630306B1 (en) | 2004-04-07 | 2006-09-29 | 에피테크 테크놀로지 코포레이션 | Nitride light-emitting diode and method for manufacturing the same |
| KR100710102B1 (en) | 2003-02-20 | 2007-04-23 | 도요다 고세이 가부시키가이샤 | Light emitting apparatus |
-
1999
- 1999-06-21 JP JP17413899A patent/JP2001007389A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100710102B1 (en) | 2003-02-20 | 2007-04-23 | 도요다 고세이 가부시키가이샤 | Light emitting apparatus |
| KR100630306B1 (en) | 2004-04-07 | 2006-09-29 | 에피테크 테크놀로지 코포레이션 | Nitride light-emitting diode and method for manufacturing the same |
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