JP2001007297A - Cmos integrated circuit and timing signal generating device provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS integrated circuit which functions as a timing generator which is used in a semiconductor test device or the like and capable of restraining timing drift or timing jitter from occurring in its timing signal output even if the CMOS integrated circuit varies in operation rate and a timing signal generating device equipped with the same. SOLUTION: A CMOS integrated circuit is equipped with a timing generating block 30 which generates timing signals and a control circuit block 20 which controls the timing of the timing generating block 30 to generate timing signals. A heater circuit 40 where a power supply current is controlled by a control voltage, a current detecting means which detects a power supply current which flows through the timing generating block 30, the control circuit block 20, and the heater circuit 40, a heater control circuit 50 which feedback controls a current that flows through the heater circuit 40, and a power supply regulator which makes an applied voltage constant controlling it by sensing a power supply voltage on a CMOS integrated circuit side are provided so as to make a CMOS integrated circuit constant in power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit for generating a timing signal requiring high timing accuracy in a semiconductor test device and the like, and a timing signal generating device using the CMOS integrated circuit.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. First, a description will be given of a main configuration and each operation of a CMOS integrated circuit that generates a timing signal requiring timing accuracy in a conventional semiconductor test device or the like. As shown in FIG. 4, one example of a conventional CMOS integrated circuit that generates a timing signal includes a power supply 10, a control circuit block 20, and a timing generation block 30.

A power supply 10 is a constant voltage power supply for supplying a power supply current to a CMOS integrated circuit. For example, the VDD side is GN
D and a negative voltage is supplied as VSS.

The control circuit block 20 synchronizes with a clock signal to control the delay circuit 31 of the timing generation block 30.
Is a logic-related circuit that generates the control signal.

The timing generation block 30 is composed of a plurality of variable delay circuits 31 for delaying a clock signal by a desired time by a control signal. The variable delay circuit 31 is a variable delay circuit having a configuration in which, for example, a path with a propagation delay of a CMOS gate and a path without a propagation delay are selected, and the delay time of the difference is combined.

Next, a conventional timing signal generating C
The operation of the MOS integrated circuit will be described. Since the control circuit block 20 is composed of a logic circuit, even if the propagation delay time of the logic element fluctuates to some extent, if the timing margin is secured for data transfer between stages, the logic operation is not affected. Do not give.

On the other hand, since the timing generation block 30 uses the output timing signal itself as a timing reference, a change in the propagation delay time causes an error in the output timing signal. Therefore, in order to obtain a highly accurate timing signal output, it is necessary to eliminate a factor that causes the propagation delay time of the timing generation block 30 to vary.

Factors that cause the delay time of the timing generation block 30 to fluctuate include the ambient temperature, the chip temperature determined by the amount of self-heating, and the fluctuation of the power supply voltage. The ambient temperature can be stabilized by improving the cooling means, for example, by keeping the refrigerant temperature constant. The power supply voltage is, for example, C
It can be stabilized by using a high-precision voltage regulator that senses the voltage supplied to the MOS integrated circuit chip.

[0009] However, it is difficult to stabilize the self-heating of the chip of the CMOS integrated circuit. Generally, CMOS
The logic gate of the integrated circuit consumes power when a power supply current flows at the moment when the output is inverted, and there is no steady power consumption.
For example, FIG. 5 shows the relationship between the operating rate of a chip of an integrated circuit and the amount of self-heating. Here, the operation rate is the total number of times that the gate output per unit time is inverted when the integrated circuit chip is operated. As shown by the dotted line in FIG. 5, the self-heating amount of the chip of the ECL integrated circuit is constant regardless of the operation rate. However, as shown by the solid line in FIG. 5, the self-heating value of the CMOS integrated circuit chip is proportional to the operation rate.

Accordingly, a change in the operation rate of the CMOS integrated circuit results in a change in the amount of self-heating, a change in the temperature of the chip, and a change in the propagation delay time. For example, as shown in FIG.
As the chip temperature of the CMOS integrated circuit increases, the propagation delay time increases. In other words, when the operation rate of the CMOS integrated circuit changes, the temperature of the chip changes, and the propagation delay time changes, resulting in timing drift and timing jitter in the output of the timing signal.

Incidentally, in a semiconductor test apparatus, it is necessary to be able to freely set the cycle and timing of a generated test signal in order to flexibly correspond to the test specifications of a device under test. Therefore, the timing signal of the output of the timing generator can be freely set for each test cycle.

For example, a timing signal is output at a cycle of 4 ns in a certain test cycle and at a cycle of 1 μs in the next test cycle. As a result, the operation rate of the CMOS integrated circuit of the timing generator changes, and the temperature of the chip changes.

Therefore, with respect to the timing generation block 30, a dummy delay circuit is provided for each variable delay circuit 31 of each timing signal, and based on the information data of the number of inverted outputs of the control circuit block 20, the dummy delay circuit is provided. Are inverting output operation to make the operation rate constant to some extent in real time.

However, since the operation rate of the control circuit block 20 itself is not fixed, the temperature changes due to the change in the operation rate, and the temperature change is transmitted to the timing generation block 30 in the same chip by heat transfer. The delay time varies, resulting in timing drift and timing jitter in the timing signal output.

[0015]

As described above, in the semiconductor test apparatus, the operation rate of the CMOS integrated circuit of the timing generator changes, resulting in timing drift and timing jitter in the output of the timing signal. Accordingly, the present invention has been made in view of such a problem, and an object of the present invention is to provide a timing drift in a timing signal output even when an operation rate of a CMOS integrated circuit of a timing generator used in a semiconductor test device or the like changes. Another object of the present invention is to provide a CMOS integrated circuit of a timing generator in which no timing jitter occurs.

[0016]

That is, the first object of the present invention to achieve the above object is to provide a timing generating block for generating a timing signal, and a control circuit block for controlling the timing of the timing generating block. In a CMOS integrated circuit that generates a timing signal, a current detection means detects a power supply current flowing through a heater circuit whose power supply current is controlled by a control voltage, the timing generation block, the control circuit block, and the heater circuit. A heater control circuit that performs negative feedback control on a current flowing through the heater circuit as a control voltage of the heater circuit;
And the power consumption of the CMOS integrated circuit is kept constant.

In order to achieve the above object, a second aspect of the present invention is to provide a power supply regulator which senses a power supply voltage on the CMOS integrated circuit side and controls the applied voltage to be constant. The gist is the CMOS integrated circuit according to the first aspect of the present invention, further comprising:

According to a third aspect of the present invention, which has been made to achieve the above object, the heater circuit comprises a current control element for controlling a power supply current by controlling an applied signal. Of the present invention.

In order to achieve the above object, a fourth aspect of the present invention is to provide a switch element capable of cutting a current by controlling an applied signal so as to cut a power supply current flowing through a heater circuit. CMO according to 1 or 3
The gist is an S integrated circuit.

A fifth aspect of the present invention to achieve the above object is a CMOS integrated circuit according to the third aspect of the present invention, wherein the current control element is constituted by a MOSFET.

A sixth aspect of the present invention, which has been made to achieve the above object, is a gist of the CMOS integrated circuit according to the fourth aspect of the present invention, wherein the switch element is constituted by a MOSFET.

A seventh aspect of the present invention to achieve the above object is a CMOS integrated circuit according to the first aspect of the present invention, wherein each heater cell of the heater circuit is arranged so as to be evenly distributed over the entire chip. It is a gist.

According to an eighth aspect of the present invention, there is provided a CMOS integrated circuit according to the first aspect, wherein each heater cell of the heater circuit is arranged only in the control circuit block. The main point is.

According to a ninth aspect of the present invention, there is provided a timing generating block for generating a timing signal, and a control circuit block for controlling the timing of the timing generating block. In a timing signal generating device having a CMOS integrated circuit, a heater circuit whose power supply current is controlled by a control voltage is provided in the CMOS integrated circuit, and the timing generating block is provided outside the CMOS integrated circuit; A CMOS integrated circuit comprising: a control circuit block; and a heater control circuit that detects a power supply current flowing through the heater circuit by current detection means and performs negative feedback control on a current flowing through the heater circuit as a control voltage of the heater circuit. Timing signal characterized by constant power consumption It has a raw device and the gist.

A tenth aspect of the present invention to achieve the above object is a power supply regulator which senses a power supply voltage on the CMOS integrated circuit side and controls the applied voltage to be constant. The gist is the timing signal generator according to the ninth aspect of the present invention, further comprising:

According to an eleventh aspect of the present invention, there is provided a heater circuit comprising a current control element for controlling a power supply current by controlling an applied signal. Of the present invention.

A twelfth aspect of the present invention, which has been made to achieve the above object, is to provide a switch element capable of cutting an electric current by controlling an applied signal so as to cut a power supply current flowing through a heater circuit. The gist is the timing signal generator described in 9 or 11.

According to a thirteenth aspect of the present invention, which has been made to achieve the above object, the current control element is a MOSFET.
The gist is the timing signal generator according to the eleventh aspect of the present invention, comprising:

According to a fourteenth aspect of the present invention, which has been made to achieve the above object, the switch element is a MOSFET.
The gist is the timing signal generator according to the twelfth aspect of the present invention.

A fifteenth aspect of the present invention to achieve the above object is a ninth aspect of the present invention in which the heater cells of the heater circuit are arranged so as to be evenly distributed over the entire chip.
The gist is the described timing signal generator.

According to a sixteenth aspect of the present invention, there is provided a timing signal generating apparatus according to the ninth aspect, wherein each heater cell of the heater circuit is arranged to be distributed only to the control circuit block. The device is the gist.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. First, a description will be given of a main configuration and each operation of a CMOS integrated circuit for generating a timing signal requiring timing accuracy according to the present invention. As shown in FIG.
An example of a CMOS integrated circuit that generates a timing signal according to the present invention includes a control circuit block 20, a timing generation block 30, a heater circuit 40, and a heater control circuit 50.
And a power supply regulator 60. In this configuration, the control circuit block 20 and the timing generation block 30 are the same as those in the related art, and thus description thereof will be omitted.

The heater circuit 40 is composed of a plurality of N-type MOSFET 1 heater cells connected in parallel, for example, as shown in FIG. However, the heater cells of the heater circuit 40 are arranged so as to be evenly distributed over the entire chip. The drain and source of MOSFET 1 of each heater cell are connected to VDD and VSS of the power supply, respectively.
The gate control voltage Hc is supplied from the heater control circuit 50. The power supply current flowing through each heater cell, that is, the heater circuit 40, is controlled by the gate control voltage Hc.

As shown in FIG. 1, the heater control circuit 50 includes a low-resistance resistor Rs for detecting a power supply current ISS flowing through the heater circuit 40, the control circuit block 20, the timing generation block 30, and a reference voltage. It consists of Vref and a differential amplifier. Further, the heater control circuit 50 performs negative feedback by the heater control voltage Hc of the heater circuit 40 so as to obtain the following equation (1), and controls the power supply current ISS to be constant. ISS × Rs = Vref (1)

For example, when the operation ratio between the control circuit block 20 and the timing generation block 30 increases and the power supply current ISS increases, the potential of the heater control voltage Hc is reduced so that the power supply current flowing through the heater circuit 40 decreases. And the power supply current ISS is controlled to be constant.
Conversely, when the operation ratio between the control circuit block 20 and the timing generation block 30 decreases and the power supply current ISS decreases, the potential of the heater control voltage Hc is lowered so that the power supply current flowing through the heater circuit 40 increases. Thus, the power supply current ISS is controlled to be constant.

The power supply regulator 60 is a constant voltage power supply for supplying a power supply current to the CMOS integrated circuit. And G
The ND potential VDD is supplied (forced) as a negative voltage VSS via the power supply current detection resistor Rs of the heater control circuit 50. And V of the timing generation circuit
By detecting (sense) the voltage on the SS side, the negative voltage of VSS is stabilized so as to be the internal reference voltage of the power supply regulator 60.

Therefore, even if the operation rate of the CMOS integrated circuit changes, the power supply voltage between VDD and VSS supplied to the chip is controlled to be constant and the power supply current ISS is controlled to be constant. The power consumption of the entire chip is always a constant value, and the temperature of the chip can be kept constant.

Therefore, even if the operating rate of the CMOS integrated circuit changes, the temperature of the chip is kept constant, so that the propagation delay time does not change. In other words, even if the operation rate of the CMOS integrated circuit changes, the propagation delay time does not change, so that timing drift and timing jitter in the timing signal output hardly occur, so that a highly accurate timing signal can be generated.

Incidentally, there is IDDQ (quiescent power supply current measurement), which is one of the testing methods for CMOS integrated circuits. This ID
The circuit of the heater cell for performing the DQ measurement includes, for example, an N-type MOSFET 1 and a P-type MOSFET 2 as shown in FIG. N type MO
The gate voltage Hc of the SFET 1 includes the heater control circuit 50
From the heater control voltage Hc. P-type MOS
The gate voltage CONT of the FET 2 is a current cut control terminal. The power supply current flowing through the heater circuit is cut when CONT = VDD, and the power supply current flows through the heater circuit 40 when CONT = VSS. Therefore, when performing the IDDQ measurement, the heater circuit 40 is set with CONT = VDD.
It cuts the power supply current that flows through it.

In the above embodiment, the heater cells of the heater circuit 40 are arranged so as to be evenly distributed over the entire chip. However, in the timing generation block 30, a dummy delay circuit is provided for each variable delay circuit 31 of each timing signal, and based on the information data on the number of inversion outputs of the control circuit block 20, the dummy delay circuit operates in an inversion output operation. To make the operation rate constant to some extent in real time, and if it is sufficiently compensated for practical use,
The arrangement of the heater cells in this portion may be omitted. That is, each heater cell of the heater circuit 40 may be arranged so as to be distributed only in the control circuit block 20.

In the above embodiment, the heater circuits in FIGS. 2 and 3 are constituted by MOSFETs. However, the present invention is not limited to MOSFETs, and may be any current control element that operates according to a control voltage.

In the above embodiment, the power supply current cutting means in FIG. 3 uses a MOSFET. However, the switching element is not limited to the MOSFET, and may be any switching element that operates according to a current cut control signal.

Further, in the above embodiment, the element of the present invention is configured as a CMOS integrated circuit. However, some elements may be arranged outside the CMOS integrated circuit, and may be configured as a timing signal generator using the CMOS integrated circuit as a whole. For example, the power supply regulator 60 is disposed outside the CMOS integrated circuit, and the control circuit block 20, the timing generation block 30, the heater circuit 40, and the heater control circuit 50 are disposed inside the CMOS integrated circuit, and the timing signal It may be configured as a generator. As another example, the heater control circuit 50 and the power supply regulator 60 are arranged outside the CMOS integrated circuit,
Control circuit block 20 and timing generation block 30
And the heater circuit 40 may be arranged in a CMOS integrated circuit to constitute a timing signal generator.

[0045]

According to the present invention, as described above, the CMO
Even if the operating rate of the S integrated circuit changes, the power supply voltage between VDD and VSS supplied to the chip is stabilized and the power supply current ISS is controlled to be constant, so that the power consumption of the entire chip Is always a constant value, and the temperature of the chip can be kept constant, so that the following effects can be obtained. That is, even if the operation rate of the CMOS integrated circuit changes, the propagation delay time does not change, so that timing drift and timing jitter in the timing signal output hardly occur. In addition, since the chip temperature becomes constant, the temperature change of the control circuit block is reduced, so that the timing margin on the circuit can be easily obtained, and the control circuit block can be simplified. Furthermore, if a heater circuit with a current cut control terminal is used, IDDQ (static power supply current measurement), which is one of the testing methods for CMOS integrated circuits, can be used.
Is also possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a CMOS integrated circuit of the present invention.

FIG. 2 is a basic circuit diagram of a heater cell.

FIG. 3 is a circuit diagram of a heater cell with a current cut control terminal.

FIG. 4 is a block diagram of a conventional CMOS integrated circuit.

FIG. 5 is a relationship diagram between the operation rate of the integrated circuit and the amount of self-heating.

FIG. 6 is a diagram illustrating a relationship between a chip temperature of a CMOS integrated circuit and a propagation delay time.

[Description of Signs] 10 power supply 20 control circuit block 30 timing generation block 31 variable delay circuit 40 heater circuit 50 heater control circuit 60 power supply regulator

Claims (16)

[Claims] A CMO that generates a timing signal by a timing generation block that generates a timing signal, and a control circuit block that controls the timing of the timing generation block
In the S integrated circuit, a power supply current is controlled by a control voltage, a power supply current flowing through the timing generation block, the control circuit block, and a power supply current flowing through the heater circuit is detected by current detection means, And a heater control circuit for performing negative feedback control of a current flowing through the heater circuit as a control voltage, wherein the power consumption of the CMOS integrated circuit is made constant. 2. The CMOS integrated circuit according to claim 1, further comprising: a power supply regulator that senses a power supply voltage on the CMOS integrated circuit side and controls the applied voltage to be constant. 3. The heater circuit according to claim 1, wherein the heater circuit includes a current control element that controls a power supply current by controlling an applied signal.
A CMOS integrated circuit as described in the above. 4. The CMOS integrated circuit according to claim 1, wherein a switch element capable of controlling an applied signal to cut a current is provided to cut a power supply current flowing through the heater circuit. 5. The CMOS integrated circuit according to claim 3, wherein said current control element is constituted by a MOSFET. 6. The CMOS integrated circuit according to claim 4, wherein said switch element is constituted by a MOSFET. 7. The CMOS integrated circuit according to claim 1, wherein each heater cell of said heater circuit is arranged so as to be evenly distributed over the entire chip. 8. The CMOS integrated circuit according to claim 1, wherein each heater cell of said heater circuit is arranged so as to be distributed only in said control circuit block. 9. A CMO for generating a timing signal by a timing generation block for generating a timing signal, and a control circuit block for controlling the timing of the timing generation block.
In the timing signal generation device having the S integrated circuit, a heater circuit whose power supply current is controlled by a control voltage is provided in the CMOS integrated circuit, and the timing generation block is provided outside the CMOS integrated circuit. A CMOS integrated circuit, comprising: a control circuit block; and a heater control circuit that detects a power supply current flowing through the heater circuit by current detection means and performs negative feedback control on a current flowing through the heater circuit as a control voltage of the heater circuit. Wherein the power consumption is constant. 10. The timing signal generator according to claim 9, further comprising: a power supply regulator that senses a power supply voltage on the CMOS integrated circuit side and controls the applied voltage to be constant. 11. The timing signal generator according to claim 9, wherein the heater circuit is constituted by a current control element that controls a power supply current by controlling an applied signal. 12. The timing signal generator according to claim 9, wherein a switch element capable of controlling an applied signal to cut the current is provided to cut a power supply current flowing through the heater circuit. 13. The timing signal generator according to claim 11, wherein said current control element is constituted by a MOSFET. 14. The timing signal generator according to claim 12, wherein said switch element is constituted by a MOSFET. 15. The timing signal generator according to claim 9, wherein each heater cell of said heater circuit is arranged so as to be evenly distributed over the entire chip. 16. The timing signal generator according to claim 9, wherein each heater cell of said heater circuit is arranged so as to be distributed only in said control circuit block.