JP2001007284A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To utilize a capacitor for adjustment with a fixed value that does not follow changes in input/output level by using an element separation oxide film as the dielectric film of the capacitor for adjusting each input/output terminal capacity. SOLUTION: An element isolation oxide film (LOCOS) 2 is formed on a substrate 4, for example, to be electrically insulated from adjacent elements. The element isolation oxide film 2 is an insulation film and separates MOS transistors used as the dielectric film of a capacitor. The element isolation oxide film 2 for insulating the adjacent element formation regions is used as the dielectric film of a capacitor 1 for adjustment to compose the capacitor. A contact 3b is branched from the middle of metal wiring 3a for connecting an input terminal IN to an initial-stage circuit and is connected to a lower-layer polysilicon 3c. The capacitor 1 for adjustment is composed by using the element isolation oxide film 2 as a dielectric film and including the element separation oxide film 2, as a dielectric film, between the polysilicon 3c as an electrode, that is penetrated through an interlayer insulation film 6 and the substrate(SUB) 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used as an adjusting capacitor for adjusting each input / output terminal capacitance.

[0002]

2. Description of the Related Art When a plurality of active circuits are formed on a substrate and wiring between the circuits is performed, it is necessary to adjust the input capacitance on the input terminal side of the circuit depending on the position of the circuit to be connected. There is.

Therefore, a semiconductor device has been developed which is used as an adjusting capacitor for adjusting the capacitance of each input terminal.

FIGS. 3A and 3B show a conventional semiconductor device of this type. The semiconductor device shown in FIG. 3A uses the gate capacitance of the nMOS transistor 20. Both the source and the drain of the nMOS transistor 20 are at the ground level, and the MOS transistor 20 between the ground level and the input terminal is used. The gate oxide film is used as an insulating film to form a capacitor.

The semiconductor device shown in FIG.
The junction capacitor using the OS transistor 20 is used.
Is connected to the input terminal IN, its source is set to the ground level, and a capacitance is formed by using a junction between the n-type diffusion layer and the p-type substrate which constitute the source.

[0006]

By the way, an adjusting capacitor for adjusting the capacitance of each input terminal is required to have a fixed value that does not follow a change in input level.

However, in the semiconductor device shown in FIG. 3B, the extent of the depletion layer at the junction changes according to the input level of the input terminal IN, and the capacitance value changes according to the input level. There is a problem in using it as an adjusting capacitor for adjusting the terminal capacitance.

Further, in the semiconductor device shown in FIG. 3A, like the configuration of the semiconductor device shown in FIG. 3B, the capacitance value changes depending on the input level, and adjustment for adjusting the capacitance of each input terminal is performed. There is a problem in using it as a storage capacity.

When the input level is equal to or lower than the threshold voltage of the nMOS transistor 20,
Channel is not formed, that is, it does not function as a capacitor having a predetermined capacitance value, and it becomes impossible to adjust the input terminal capacitance.

Further, the gate oxide film of the nMOS transistor 20 is used as a capacitance film. However, since the gate oxide film is generally formed of a thin film, the gate oxide film is protected from external high voltage surge due to electrostatic discharge (ESD) or the like. On the other hand, it is easily broken, and may cause a leak failure.

Further, since the above-mentioned adjusting capacitor uses the gate oxide film or the junction (junction) of the nMOS transistor 20, it is incorporated in the element forming region, so that a new forming region as the adjusting capacitor is newly secured. Therefore, there is a problem that the chip size is increased.

An object of the present invention is to provide a semiconductor device as an adjusting capacitor having a fixed value that does not follow a change in input / output level.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device used as an adjusting capacitor for adjusting the capacitance of each input / output terminal. An element isolation oxide film is used as the film.

Further, a wiring layer and a substrate are used as electrodes of the adjusting capacitor.

Further, the electrode of the adjusting capacitor is arranged in parallel on the element isolation oxide film, and the adjusting capacitor is connected in parallel.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a state in which an embodiment of the present invention is connected to an input first-stage circuit section. FIG. 2A is a circuit diagram showing a semiconductor device according to an embodiment of the present invention. b)
1 is a sectional view showing a semiconductor device according to one embodiment of the present invention.

As shown in FIGS. 2 (a) and 2 (b), the semiconductor device according to the present invention is capable of isolating adjacent element formation regions from each other without using the junction of the MOS transistor or the MOS transistor itself. The capacitor is characterized by using the oxide film 2 as a dielectric film of the adjusting capacitor 1 and using the existing wiring layer 3 and the substrate 4 as electrodes of the adjusting capacitor 1. The electrodes of the adjusting capacitor 1 include the wiring layer 3 and the substrate 4
Other than these may be used.

In the semiconductor device according to one embodiment of the present invention shown in FIG. 2A, one end of the adjustment capacitor 1 is connected to the input terminal IN, and the circuit on the base 4 is connected to the input / output protection resistor R. 5 (see FIG. 1). Circuit 5
May use a circuit configuration other than that shown in FIG.

Further, a specific example of the semiconductor device according to the present invention shown in FIG. 2 will be described in detail as an embodiment.

As shown in FIG. 2B, to form the MOS transistor 20 shown in FIG.
When forming the MOS transistor 20, the MO
The S transistor 20 is connected to an adjacent element (for example, another MOS
An element isolation oxide film (LOCOS) 2 is formed for electrical insulation from the transistor.

Generally, the element isolation oxide film 2 is for isolating adjacent elements and is not used for any purpose other than the intended use. However, the present inventor has found that the element isolation oxide film 2 is an insulating film and has a small capacitance. The element isolation oxide film 2 can be used as a dielectric film, and the element isolation oxide film 2 isolates MOS transistors from each other and has a thickness.
Paying attention to the fact that the portion is an empty space, etc., a capacitor is formed by using an element isolation oxide film 2 which insulates adjacent element formation regions from each other as a dielectric film of the adjusting capacitor 1.

That is, the element isolation oxide film 2 is formed on the base 4.
Are formed. In FIG. 2B, the transistor in the element formation region is not shown because the cross section is centered on the element isolation oxide film 2, but in the case of FIG. 2B, the transistor in the element formation region is sandwiched by the element isolation oxide film 2. It will be formed in the vertical direction in the figure.

Further, the contact 3b is branched from the middle of the wiring 3a connecting the input terminal IN shown in FIGS. 1 and 2 (a) to the first stage circuit 5 shown in FIG. 1, and the contact 3b is connected to the lower polysilicon 3c. Are connected to each other to form the adjusting capacitor 1 in which the element isolation oxide film 2 is interposed as a dielectric film between the polysilicon 3c as an electrode and the substrate (SUB) 4 using the element isolation oxide film 2 as a dielectric film. are doing. The lower polysilicon 3c is formed in the same layer as the polysilicon layer forming the gate electrode of the transistor formed in the element formation region. The contact 3b is formed penetrating through the interlayer insulating film 6.

The wiring layer forming the electrode of the adjusting capacitor 1 is made of a combination of the wiring 3a, the contact 3b, and the polysilicon 3c. However, the present invention is not limited to this. If the configuration is such that the electrode of the adjusting capacitor 1 is connected to the wiring 3a connecting the first-stage circuit 5,
Any one may be used.

As shown in FIGS. 2A and 2B, according to one embodiment of the present invention, the adjusting capacitor 1 is configured without using the junction of the MOS transistor or the MOS transistor itself.

According to one embodiment of the present invention, the element isolation oxide film 2 for isolating the element formation regions from each other is used as the dielectric film of the capacitor 1. The element isolation oxide film 2 has a film thickness. In general, the film thickness is about 2000 mm, and the input terminal IN
Is hardly affected by the input level, and its thickness is large, so that it is not damaged due to an increase in withstand voltage against an external high-voltage surge due to electrostatic discharge (ESD) or the like. Things.

Further, an element isolation oxide film 2 as a dielectric film
Is thicker than a gate oxide film and the like, so that the element area required to form the same capacitance value is larger than that of a conventional device, but the lower layer vacant space such as a wiring layer (bus line) is used. And can be easily formed.

Further, the withstand voltage against a high-voltage surge is increased, and the p-type and n-type diffusion layers forming the source and drain of the transistor are not used.
Almost no restrictions are imposed on the layout for forming the capacitance, and an increase in chip size can be avoided. Here, the regulation of the layout and the like refers to the restriction of the arrangement and the like in consideration of the distance to other transistor components.

In the embodiment, the capacitor is provided on the input side to provide a capacity independent of the level of the input terminal. However, the configuration of the present invention is provided on the output side to provide a capacity independent of the level of the output terminal. May be used.

Also, the configuration is such that the electrodes (the wiring layer 3 and the substrate 4 in the embodiment shown in FIGS. 1 and 2) of the adjusting capacitor 1 are arranged in parallel on the element isolation oxide film 2 and the adjusting capacitor 1 is connected in parallel. It is good.

[0032]

As described above, according to the present invention, it is possible to provide a capacitance independent of the level of the input / output terminal, to improve the withstand voltage against a high-voltage surge from the outside, and to further regulate the layout. The capacity which does not receive can be constituted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a state in which an embodiment of the present invention is connected to an input first-stage circuit unit.

FIG. 2A is a circuit diagram showing a semiconductor device according to one embodiment of the present invention, and FIG. 2B is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor device used as an adjustment capacitor for adjusting an input terminal capacitance according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Adjusting capacity 2 Element isolation oxide film 3a Wiring 3b Contact 4 Base 5 Circuit

Claims (3)

[Claims] 1. A semiconductor device used as an adjusting capacitor for adjusting each input / output terminal capacitance, wherein an element isolation oxide film is used as a dielectric film of the adjusting capacitor. 2. The semiconductor device according to claim 1, wherein a wiring layer and a substrate are used as the electrodes of the adjusting capacitor. 3. The semiconductor device according to claim 1, wherein an electrode of the adjusting capacitor is arranged in parallel on the element isolation oxide film, and the adjusting capacitor is connected in parallel.