JP2001006355A - Memory cell and semiconductor memory using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce area of a memory cell and to realize simplification of refresh operation by reducing the number of bit contacts of a memory cell. SOLUTION: A memory cell MC1 is connected to a bit line BL, a reference cell DMC is connected to a bit complementary line /BL, transistors Q1 and Q2 are turned on at the time of write-in, a potential of the bit line BL is applied to a gate of a memory transistor Q3, and it is held by the memory transistor Q3. Before read-out, a discharge 20 holds the bit lines BL, /BL at a ground potential, writes '1' in a reference cell DMC, read-out word lines DRWL, RWL are activated, potential difference is caused between the bit line BL and the bit line /BL in accordance with storage data of the memory cell MC1, and it is amplified by a sense amplifier 30. After that, refresh is performed by writing a bit line potential again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a dynamic random access memory (DRAM) in which a memory cell includes three transistors.

[0002]

2. Description of the Related Art FIG. 7 shows an example of a configuration of a memory cell of a semiconductor memory device in which the memory cell is composed of three transistors. As shown, this memory cell MC0
Is composed of a write transistor Q10, a memory transistor Q20, and a read transistor Q30.

The write transistor Q10 has a gate connected to the write word line WWL, a drain connected to the bit line BL, and a source connected to the memory transistor Q2.
0 is connected to the gate. Read transistor Q
At 30, the gate is connected to the read word line RWL, the drain is connected to the bit line BL, and the source is connected to the drain of the memory transistor Q20. The source of the memory transistor Q20 is grounded.

A memory cell MC0 shown in FIG. 7 is formed of three transistors, and a bit line BL, a write word line WWL, a read word line RWL, and a source line SL for supplying a ground potential are connected to the memory cell MC0. Have been. Since the source line SL is shared by adjacent memory cells, such a memory cell MC0 is also called a 3.5-line DRAM cell.

Next, the operation of memory cell MC0 will be described. The writing is performed in such a state that after holding the bit line BL at a voltage corresponding to the write data, a high-level write voltage is applied to the write word line WWL to turn on the write transistor Q10. In this case, the voltage of the bit line BL is applied to the gate of the memory transistor Q20 via the write transistor Q10, and is held by the gate capacitance of the memory transistor Q20. That is, the potential corresponding to the write data is held at the gate of the memory transistor Q20 by the writing. Information corresponding to the potential is held in the memory cell MC0.

For reading, after the bit line BL is precharged to a predetermined precharge potential, the read word line R
This is performed by applying a high-level read voltage to WL and turning on the read transistor Q30.
When the gate voltage of the memory transistor Q20 is held at a high level, the memory transistor Q20 is turned on, and the bit line BL is discharged to the source line SL through the read transistor Q30 and the memory transistor Q20, so that the potential is reduced. . On the other hand, when the gate voltage of the memory transistor Q20 is held at a low level, the memory transistor Q20 turns off,
The potential of the bit line BL is maintained at the precharge potential at the start of reading. As described above, the potential of the bit line BL changes in accordance with the gate potential of the memory transistor Q20, that is, the potential of the bit line BL according to the storage data of the memory cell MC0. The data stored in the cell MC0 can be read.

Since the gate potential of the memory transistor Q20 is held by the gate capacitance of the memory transistor Q20, the charge held in the gate is gradually released over time, so that the stored data is lost. Resulting in. For this reason, like the other DRAMs, it is necessary to perform a refresh operation by reading and rewriting on the memory cell MC0 at regular intervals.

At the time of refreshing, first, the memory cell M
Reading is performed in C0. Thereby, the bit line B according to the gate voltage of the memory transistor Q20 is
The potential of L is set. For example, as described above, when the gate voltage of the memory transistor Q20 is at a high level, the potential of the bit line BL is set low. Conversely, when the gate voltage of the memory transistor Q20 is at a low level, the potential of the bit line BL is almost It does not change and is kept at the precharge voltage before reading. That is, by reading,
Bit line BL is set to a voltage at which the logic is inverted from the gate voltage of memory transistor Q20. Each time one refresh operation is performed, the memory transistor Q20
Is inverted from the high level to the low level or from the low level to the high level. Therefore,
Read word line R connected to memory cell MC0
A monitor circuit for monitoring the number of times WL and the write word line WWL are selected is provided for each word line, and the information stored in the memory cell MC0 is correctly read by the information from the monitor circuit and the voltage read to the bit line BL. To detect.

[0009]

In the above-described semiconductor memory device including the conventional memory cell MC0, the refresh operation is complicated, and the scale of the circuit is reduced by a monitor circuit added for refreshing. And the circuit area increases. Furthermore, in each memory cell, the write transistor Q10 and the read transistor Q20 are each connected to the bit line BL via a bit contact, so that two bit contacts are required for each memory cell, and the area of the memory cell increases. There is a disadvantage.

The present invention has been made in view of such circumstances, and an object of the present invention is to reduce the number of bit contacts of a memory cell, thereby reducing the area of the memory cell.
Another object of the present invention is to provide a memory cell capable of realizing a simplified refresh operation and a semiconductor memory device using the same.

[0011]

In order to achieve the above object, a memory cell according to the present invention comprises a bit line, a write word line, a read word line, one terminal connected to the bit line, and a control terminal. Is connected to the read word line, and at the time of writing and reading, a first transistor that is kept on by an applied voltage of the read word line and one terminal is connected to the other terminal of the first transistor A control terminal is connected to the write word line, and at the time of writing, a second transistor held in an on state by a voltage applied to the write word line, and a control terminal connected to the other terminal of the second transistor. One terminal is connected to the other terminal of the first transistor, the other terminal is connected to the power supply voltage line, Can the control terminal and a memory transistor to be held at a potential corresponding to the bit line potential.

Further, in the present invention, preferably, a bit contact is formed between the bit line and one terminal of the first transistor.

In the present invention, preferably, at the time of writing, a read voltage for holding the first transistor in an on state is applied to the read word line, and a voltage corresponding to write data is applied to the bit line. Is applied, and a write voltage for holding the second transistor in an ON state is applied to the write word line.

In the present invention, preferably, at the time of reading, the bit line is held at a reference voltage lower than the power supply voltage, and the read word line holds the first transistor in an ON state. Is applied, the conduction state of the memory transistor is controlled according to the holding voltage of the control terminal of the memory transistor, and the bit line is connected to the reference voltage or a predetermined voltage between the reference voltage and the power supply voltage. Is held in any of

Further, the semiconductor memory device of the present invention includes a write word line, a read word line, a reference write word line, a reference read word line, a first bit line,
A second bit line, a discharge circuit for holding the first and second bit lines at a reference potential before the start of reading, a sense amplifier for detecting a potential difference between the first and second bit lines at the time of reading, A reference cell connected to the second bit line, and at least one memory cell connected to the first bit line, the memory cell having one terminal connected to the first bit line; A first transistor connected to the read word line, a control terminal connected to the read word line, and a write-in and read-out operation. A control terminal is connected to the other terminal of the transistor, and a control terminal is connected to the write word line. At the time of writing, the write terminal is kept on by an applied voltage of the write word line. And a control terminal is connected to the other terminal of the second transistor, one terminal is connected to the other terminal of the first transistor, and the other terminal is connected to a power supply voltage line. A memory transistor in which the control terminal is maintained at a potential corresponding to the first bit line potential during writing; the reference cell has one terminal connected to the second bit line; Is connected to the reference read word line,
At the time of reading, a first reference transistor which is kept on by an applied voltage of the reference read word line, one terminal is connected to the other terminal of the first reference transistor, and a control terminal is connected to the reference write A second reference transistor connected to a word line and held on by an applied voltage of the reference write word line before reading, and a control terminal connected to the other terminal of the second reference transistor; Is connected to the other terminal of the first reference transistor, the other terminal is connected to the power supply voltage supply line, and the control terminal is held at a potential corresponding to the power supply voltage before reading. A transistor.

In the present invention, preferably, the reference cell has a control terminal connected to a discharge control signal supply terminal, one terminal connected to the power supply voltage supply line, and the other terminal connected to the power supply voltage supply line. A third reference transistor connected to the other terminal of the first reference transistor and held in an on state in response to the discharge control signal before reading.

In the present invention, preferably, the memory transistor has a gate width larger than that of the reference memory transistor.

In the present invention, preferably, the discharge circuit has a control terminal connected to a discharge control signal supply terminal and a first discharge line connected between the first bit line and a reference potential. A transistor, a control terminal is connected to a supply terminal of the discharge control signal, a second discharge transistor connected between the second bit line and a reference potential, and a control terminal is connected to the discharge control signal terminal. , A third discharge transistor connected between the first and second bit lines.

Further, in the present invention, preferably, the control terminal is connected to the supply terminal of the read control signal, and the first read drive transistor connected between the first bit line and the reference potential; A terminal is connected to a supply terminal of the read control signal, and has a second read drive transistor connected between the second bit line and the reference potential. When reading, the read word line and the read word transistor are connected. According to the application of the read voltage to the reference read word line, a read control signal having a predetermined level is applied to the upper read control signal line, and the first and second read drive transistors are held in the on state.

According to the present invention, the memory cell including the first, second, and memory transistors is connected to the first bit line. In the memory cell, the first transistor has a control terminal connected to the read word line, one terminal of which, for example, a source electrode is connected to the first bit line via a bit contact, and the second transistor has , A control terminal is connected to the write word line, and one terminal, for example, a drain electrode is connected to the drain of the first transistor. Further, the memory transistor has a control terminal connected to the source of the second transistor, one terminal, for example, a source connected to the drain of the first transistor, and the other terminal connected to a power supply voltage supply line. Have been. Therefore, the memory cell
It is connected to the first bit line via only one bit contact. The reference cell connected to the second bit line has substantially the same configuration as the memory cell.

At the time of writing, the potential of the first bit line is set in accordance with the write data, the first and second transistors are controlled to be turned on, and the potential corresponding to the first bit line potential is set in the memory. Applied to the control terminal of the transistor. After that, the first and second transistors are kept off, so that the potential of the control terminal of the memory transistor is kept. By associating the potential level of the control terminal of the memory transistor with data "1" or "0", data "1" or "0" is stored according to the holding potential of the control terminal of the memory transistor. At the time of reading, the first and second bit lines are each held at a reference potential, for example, a ground potential by discharging, and after the control terminal of the reference memory transistor of the reference cell holds a high potential corresponding to the power supply voltage, Since both the first transistor of the memory cell and the first reference transistor of the reference memory cell are set to the ON state, the potentials of the first and second bit lines become the potentials of the control terminals of the memory transistor and the reference memory transistor, respectively. Therefore, the potential of the control terminal of the memory transistor of the memory cell can be determined by detecting the potential difference between the first and second bit lines by the sense amplifier,
The storage data corresponding to the data can be read. Refresh can be realized by sequentially executing reading and writing. At the time of reading, the potential difference between the first and second bit lines is amplified by the sense amplifier, and the bit line potential is determined. At the time of writing, the determined bit line potential is applied to the control terminal of the memory transistor of the memory cell, so that the charge escaping from the gate of the memory transistor is supplemented, and the data stored in the memory cell is retained.

[0022]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention. As illustrated, the semiconductor memory device according to the present embodiment includes a word line driving circuit 10,
Discharge circuit (CHR) 20, sense amplifier (S
/ A) 30, a reference cell (reference cell) DMC and m memory cells MC1, MC2,..., MCm. Although FIG. 1 shows only one row of memory cells, an actual semiconductor memory device is composed of a plurality of rows of memory cells having substantially the same configuration as the illustrated memory row.

Discharge circuit 20 and sense amplifier 3
The bit line BL and the complementary bit line / BL are connected between the bit line BL and the bit line 0. The reference cell DMC includes a reference read word line (reference read word line) DRWL,
It is connected to a reference write word line (reference write word line) DWWL and a bit auxiliary line / BL.
The memory cells MC1, MC2,..., MCm are all connected to a bit line BL, the memory cell MC1 is connected to a read word line RWL1 and a write word line WWL1, and the memory cell MC2 is a read word line RWL2 and a write word line WWL2. Connected to the memory cell MC
m is a read word line RWLm and a write word line WW
Lm.

The reference read word line DRWL,
The reference write word line DWWL, read word line RWL1, write word line WWL1, read word line RWL2, write word lines WWL2,..., Read word line RWLm, and write word line WWLm
It is connected to the word line drive circuit 10. The word line drive circuit 10 drives each word line and reference word line to a predetermined potential at the time of reading, writing, and refreshing. For example, at the time of reading, a high-level read voltage is applied to a read word line connected to a selected memory cell among a plurality of read word lines, and a read transistor of the selected memory cell is turned on. At the time of writing, a high-level write voltage and a read voltage are applied to the write word line and the read word line connected to the selected memory cell, respectively.
The write transistor and the read transistor of the selected memory cell are turned on. On the other hand, at the time of refresh, the respective memory cells are sequentially selected, and the read word line and the write word line are held at predetermined potentials so that reading and rewriting are sequentially performed on the selected memory cells.

Before reading, the discharge circuit 20 holds both the bit line BL and the bit auxiliary line / BL at a predetermined reference potential, for example, a ground potential. At the time of reading in the reading and refresh operations, the sense amplifier 30 detects a potential difference between the bit line BL and the bit auxiliary line / BL, and reads data stored in a selected memory cell according to the potential difference. Sense amplifier 30 amplifies a slight potential difference between bit line BL and bit auxiliary line / BL, and holds bit line BL and bit auxiliary line / BL at either power supply voltage V _CC or ground potential, respectively. At the time of refresh, the potential of the bit line BL amplified by the sense amplifier 30 is applied again to the gate of the memory transistor through the write transistor and the read transistor of the memory cell.

FIG. 2 shows an example of the configuration of a memory cell MC1 constituting the semiconductor memory device of the present embodiment. In the present embodiment, the other memory cells have substantially the same configuration as the memory cell MC1.

As shown in FIG. 2, the memory cell MC1 has
It comprises a read transistor Q1 (first transistor), a write transistor Q2 (second transistor) and a memory transistor Q3.

In the read transistor Q1, the source is connected to the bit line BL, and the gate is connected to the read word line RWL. In the write transistor Q2, the drain is the read transistor Q2.
1 and the gate is connected to the write word line W.
Connected to WL. In the memory transistor Q3, the gate is connected to the source of the write transistor Q2, the source is connected to the drain of the read transistor Q1, and the drain is connected to the supply line of the power supply voltage V _CC .

In the memory cell MC1 of this embodiment,
The source of the read transistor Q1 is connected to the bit line BL via a bit contact. The drain of the writing transistor Q2 is connected to the drain of the reading transistor Q1. Therefore, the number of bit contacts is only one. Since the number of bit contacts is reduced as compared with the conventional memory cell MC0 shown in FIG. 7, the area of the memory cell of the present invention can be reduced as compared with the conventional memory cell MC0.

FIG. 3 is a waveform chart showing the operation of the memory cell MC1 of the present embodiment shown in FIG. FIG.
(C) shows waveforms of signals on the read word line RWL, write word line WWL, and bit line BL at the time of read, write, and refresh. Hereinafter, the read, write, and refresh operations of the memory cell MC1 of the present embodiment will be described with reference to FIG.

As shown in FIG. 3A, before reading,
The bit line BL is held at, for example, the ground potential by the discharge circuit. During reading, the write word line WWL is kept at a low level. At the time of reading, first, a high-level read voltage is applied to the read word line RWL. In response, in the memory cell MC1 shown in FIG. 2, the read transistor Q1 turns on.
According to the holding potential of the gate of the memory transistor Q3,
The potential of the bit line BL is determined. For example, when the gate potential of the memory transistor Q3 is kept at a low level, the potential of the bit line BL does not change because the memory transistor Q3 is kept off. On the other hand, when the gate potential of the memory transistor Q3 is held at the high level, the memory transistor Q3 is turned on, and the bit line BL is charged by the power supply voltage V _CC through the read transistor Q1 and the memory transistor Q3. The potential rises. As described above, the potential of the bit line BL is set according to the gate potential of the memory transistor Q3 at the time of reading. Therefore, the potential of the bit line BL is detected by the sense amplifier, so that the gate potential of the memory transistor Q3, that is, The information stored in the memory cell MC1 can be read.

As shown in FIG. 3B, at the time of writing, first, a high-level read voltage is applied to the read word line RWL. In response, read transistor Q1 shown in FIG. 2 is held in the ON state. And
The potential of the bit line BL is set according to the write data. When the set potential of the bit line BL is stabilized, a high-level write voltage is applied to the write word line WWL, and the write transistor Q2 is turned on accordingly, so that the memory transistor Q3 is set according to the set potential of the bit line BL. Is set. Since both the write word line WWL and the read word line RWL are held at low level, the read transistor Q
1 and the write transistor Q2 are both kept off, a constant charge is held at the gate of the memory transistor Q3, and information according to the charge amount is stored in the memory transistor Q3.

The electric charge held at the gate of the memory transistor Q3 is released over time, so that the information stored in the memory transistor Q3 is lost. For this reason, it is necessary to perform refresh at regular time intervals. FIG. 3C shows a waveform during the refresh operation.

As shown, before the refresh, the bit line BL is held at a low level, for example, a ground potential by a discharge circuit. At the time of refresh, first, a high-level read voltage is applied to the read word line RWL. In response, the read transistor Q1 of the memory cell MC1 is turned on, and the potential of the bit line BL is set according to the gate voltage of the memory transistor Q3. For example, when the gate voltage of the memory transistor Q3 is at a high level, the memory transistor Q3 is turned on, so that the bit line BL is charged by the power supply voltage V _CC through the read transistor Q1 and the memory transistor Q3, and the potential of the bit line BL is high. Retained on level. On the other hand, when the gate potential of the memory transistor Q3 is at the low level, the memory transistor Q3 is held in the off state, so that the potential of the bit line BL remains unchanged as the discharged potential. By the sense amplifier,
The bit line BL potential is amplified and, for example, when it is at a high level, it is amplified to the power supply voltage V _CC level, and conversely, when it is at a discharge potential, that is, when it is at a low level, it is held at the ground potential.

After the bit line potential is determined, a high-level write voltage is applied to the write word line WWL,
In response, the write transistor Q2 is turned on, so that the bit line potential changes via the read transistor Q1 and the write transistor Q2 to the memory transistor Q2.
3 is applied to the gate. After that, since both the read transistor Q1 and the write transistor Q2 are held in the off state, the gate potential of the memory transistor Q3 is held.

As described above, refresh is performed by executing read and write operations once each. During the refresh operation, the bit line potential is set according to the gate voltage of the memory transistor Q3, and the amplified bit line potential is directly applied to the gate of the memory transistor Q3. Is simple, no special additional circuit is required for refreshing, and the circuit can be simplified.

FIG. 4 shows a specific circuit example of the semiconductor memory device of the present embodiment. FIG. 4 shows the discharge circuit 20, the reference cell DMC, the memory cell MC1, and the sense amplifier 30, respectively. FIG.
Shows one memory cell MC1 for convenience,
In an actual semiconductor memory device, as shown in FIG. 1, a plurality of memory cells MC1, MC2,..., MCm are connected to a bit line BL. Hereinafter, the configuration of each part of the semiconductor memory device of the present embodiment will be described with reference to FIG.

The discharge circuit 20 is composed of transistors QC1, QC2 and QC3. The transistor QC1 is connected between the bit line BL and the ground potential,
Transistor QC2 is connected between bit auxiliary line / BL and ground potential, and transistor QC3 is connected between bit line BL and bit auxiliary line / BL. Transistor QC
1, the gates of QC2 and QC3 are all connected to the supply line of the discharge control signal D. The discharge control signal D is normally kept at a low level. When performing the discharge operation, the discharge control signal D is held at a high level. In response, transistors QC1, QC2 and QC3 are turned on, and both bit line BL and bit auxiliary line / BL are held at the ground potential.

The reference cell DMC includes a reference read transistor DQ1, a reference write transistor DQ2, and a reference memory transistor DQ.
Q3 and the transistor DQ4. The reference cell DMC has a configuration similar to that of the memory cell MC1. The gate of the transistor DQ1 is connected to the reference read word line DRWL, and the source is connected to the auxiliary bit line / BL. The drain of the transistor DQ2 is connected to the drain of the transistor DQ1, and the gate is connected to the reference write word line DWWL. A node ND1 is formed by a connection point between the drains of the transistors DQ1 and DQ2. The gate of the transistor DQ3 is connected to the source of the transistor DQ2, the drain is connected to the supply line of the power supply voltage V _CC , and the source is connected to the node ND1. The gate of the transistor DQ4 is connected to the supply line of the discharge control signal D, its drain connected to the supply line of the power supply voltage V _CC, the source is connected to the node ND1.

The reference cell DMC sets the potential of the bit auxiliary line / BL at the time of reading. Before reading, the discharge control signal D is held at a high level, so that the discharge circuit 20 operates. As described above, the discharge circuit 20 causes the bit line BL
And bit complementary line / BL are both held at the ground potential.
In the reference cell DMC, the node ND1 is charged by the power supply voltage V _CC by turning on the transistor DQ4 almost simultaneously with the discharge of the bit line BL and the bit auxiliary line / BL. Further, since the reference write word line DWWL is held at the high level, the reference write transistor DQ2 is turned on, the potential of the node ND1 is applied to the gate of the reference memory transistor DQ3, and the gate of the reference memory transistor DQ3 is held at the high level Is done. Here, the state where the gate of the reference memory transistor DQ3 is held at the high level is made to correspond to the storage data “1”. That is, the bit line BL and the bit auxiliary line / BL are both held at the ground potential by the discharge operation before reading, and the reference cell DMC
Is written with data "1".

At the time of reading, since a high-level read voltage is applied to the reference read word line DRWL, the reference read transistor DQ1 of the reference cell DMC turns on. For this reason, the potential of the bit auxiliary line / BL becomes higher than the potential of the reference memory transistor DQ.
3 is set according to the gate potential. On the other hand, bit line B
When the potential of L is equal to the memory transistor Q3 of the memory cell MC1.
Is set in accordance with the gate potential of
By detecting 0, the data stored in the memory cell MC1 can be read by detecting the potential difference between the bit line BL and the bit auxiliary line / BL.

Memory cell MC1 has the same configuration as the memory cell shown in FIG. That is, the memory cell MC1 is connected to the bit line BL, and when writing, the bit line BL
The gate potential of the memory transistor Q3 is set according to the potential of the memory transistor Q3.
Of the bit line BL is set according to the gate potential of the bit line BL. Here, by writing, the memory transistor Q3
The state where the gate of the memory transistor Q3 is held at a low level corresponds to the storage data "0", and the state where the gate of the memory transistor Q3 is held at a low level corresponds to the storage data "0".

The sense amplifier 30 includes a CMOS inverter constituted by a pMOS transistor PS1 and an nMOS transistor NS1, and a pMOS transistor PS2.
And a CMO constituted by the nMOS transistor NS2
It is composed of an S inverter. As shown, the sense amplifier 30 is a latch circuit in which input terminals and output terminals of these inverters are connected alternately.

In the sense amplifier 30, the sources of the pMOS transistors PS1 and PS2 are both connected to the supply terminal of the positive drive voltage SPL, and the nMOS transistor N
The sources of S1 and NS2 are both connected to the supply terminal of the negative drive voltage SNL. At the time of the sensing operation, the positive drive voltage SPL is held at a positive high voltage, for example, the power supply voltage V _CC , the negative drive voltage SNL is held at, for example, the ground potential, and the sense amplifier 30 is activated. The sense amplifier 30 amplifies the potential difference between bit line BL and bit auxiliary line / BL, and as a result, data stored in the selected memory cell is read.

The write operation of the semiconductor memory device shown in FIG. 4 can be described with reference to the waveform diagram of FIG. That is, first, the read word line RWL is held at a high level,
After that, the potentials of the bit line BL and the bit auxiliary line / BL are set according to the write data. Bit line B
When the potential of L and the bit auxiliary line / BL is determined, the write word line WWL is held at the high level. As a result, the write transistor Q2 of the memory cell MC1 is turned on, and the potential of the bit line BL is changed to the read transistor Q2.
1 and the gate of the memory transistor Q3 via the write transistor Q2. Then, both the write word line WWL and the read word line RWL are held at the low level, and the gate potential of the memory transistor Q3 is held. Data corresponding to the gate potential is stored in the memory cell MC1. For example, when the gate potential is at a high level, data “1” is stored, and when the gate potential is at a low level, data “0” is stored.

FIG. 5 is a timing chart at the time of reading of the semiconductor memory device shown in FIG. Hereinafter, FIG.
The read operation of the semiconductor memory device according to the present embodiment will be described in more detail with reference to FIG.

As shown in FIG. 5, at time t1, the discharge control signal D and the potential of the reference write word line DWWL are held at the high level. Accordingly, bit line BL and bit supplementary line / BL
Are both held at the ground potential. Further, data “1” is written in the reference cell DMC. That is, the reference memory transistor D of the reference cell DMC
The gate of Q3 is held at high level.

After the discharge control signal D and the reference write word line DWWL are switched to low level, at time t2, a high-level read voltage is applied to both the reference read word line DRWL and read word line RWL. In response,
The reference read transistor DQ1 of the reference cell DMC and the read transistor Q1 of the memory cell MC1 turn on.

By the discharge operation, data "1" is written to the reference cell DMC. That is, the gate voltage of the reference memory transistor DQ3 of the reference cell DMC is held at a high level. As a result, the reference memory transistor DQ3 is turned on, and the bit supplementary line / BL becomes the reference memory transistor DQ3 and the reference read transistor DQ1.
Through the power supply voltage V _CC , and its potential rises.

At time t3, read control signal R is held at the high level. As shown in FIG. 4, a drive transistor Q5 is connected between the bit line BL and the ground potential,
Driving transistor DQ between bit auxiliary line / BL and ground potential
5 is connected. The gates of the transistors Q5 and DQ5 are both connected to the supply line of the read control signal R. Therefore, when the read control signal R is held at a high level, both the drive transistors Q5 and DQ5 are turned on.

At this time, in addition to the driving transistor Q5, the memory transistor Q3 is connected to the bit line BL via the reading transistor Q1 in the memory cell MC1. On the other hand, in addition to the drive transistor DQ5, the reference memory transistor DQ3 in the reference cell DMC is connected to the bit auxiliary line / BL via the reference read transistor DQ1. At this time, the bit line BL and the bit supplementary line / BL
6 are shown in FIGS. 6A and 6B, respectively.

Since both the read transistor Q1 of the memory cell MC1 and the reference read transistor DQ1 of the reference cell DMC are on, these transistors are omitted in the equivalent circuits of FIGS. 6A and 6B. According to the data stored in the memory cell MC1, the gate potential of the memory transistor Q3 is held at either the high level or the low level.
Since data "1" is always stored in the reference cell DMC, the reference memory transistor DQ3
Is held at a high level.

When the read control signal R is held at a high level, both the transistors Q5 and DQ5 are turned on. At this time, for example, assuming that data “0” is stored in the memory cell MC1, the memory transistor Q3 is held in the off state. Therefore, the bit line BL
Are held at the low level, that is, the ground potential. On the other hand, assuming that data "1" is stored in the memory cell MC1, the gate of the memory transistor Q3 is held at a high level, and the memory transistor Q3 is turned on. Therefore, the potential of the bit line BL is determined by the respective driving capabilities of the memory transistor Q3 and the driving transistor Q5. Since the gate width of the driving transistor Q5 is formed small, that is, the driving capability is set lower than that of the memory transistor Q3, the bit line BL is mainly driven to a high level by the memory transistor Q3.

In the reference cell DMC, since the gate of the reference memory transistor DQ3 is held at the high level, both the transistor DQ3 and the driving transistor DQ5 are held in the ON state. For this reason, the potential of the bit auxiliary line / BL is determined by the respective drive capabilities of the reference memory transistor DQ3 and the drive transistor DQ5. Since the driving transistor DQ5 is formed with substantially the same gate width as the driving transistor Q5 on the bit line BL side, its driving capability is
It is set to be almost the same as 5, On the other hand, since the gate width of the reference memory transistor DQ3 is formed smaller than the gate width of the memory transistor Q3 of the memory cell MC1,
The driving capability of Q3 is set lower than the driving capability of memory transistor Q3. For this reason, when data “1” is stored in the memory cell MC1, when reading,
The potential of bit line BL is maintained higher than the potential of bit auxiliary line / BL. Conversely, when data "0" is stored in the memory cell MC1, at the time of reading, the potential of the bit line BL is kept lower than the potential of the bit auxiliary line / BL. That is, regardless of the data stored in the memory cell MC1, there is always a potential difference between the bit line BL and the bit auxiliary line / BL at the time of reading. This potential difference is amplified by the sense amplifier 30. As a result, data stored in the memory cell MC1 can be read.

At time t4, drive signal SPL of the sense amplifier is held at power supply voltage V _CC , so that sense amplifier 30 is activated and bit line BL and bit auxiliary line / BL
Is amplified by the sense amplifier 30. When the potential of the bit line BL is higher than the potential of the bit auxiliary line / BL,
As a result of amplification by the sense amplifier 30, the potential of the bit line BL is held at a high level, for example, the power supply voltage V _CC ,
The potential of bit auxiliary line / BL is held at a low level, for example, a ground potential. Conversely, when the potential of bit line BL is lower than the potential of bit auxiliary line / BL, as a result of amplification by sense amplifier 30, the potential of bit line BL is held at the ground potential, and the potential of bit auxiliary line / BL becomes the power supply voltage. It is held at V _CC .

As described above, as a result of the reading, the potentials of the bit line BL and the bit auxiliary line / BL are respectively determined according to the data stored in the memory cell MC1. Bit line BL
And memory cell MC according to the potential of bit complement line / BL.
1 stored data can be read.

After the end of reading, the discharge control signal D is held at a high level as shown in FIG. The discharge circuit 20 operates in response to this, and the bit line B
Both L and bit auxiliary line / BL are held at the ground potential.

The refresh operation is performed by performing a rewrite following the above-described read operation.
That is, the potential difference between the bit line BL and the bit auxiliary line / BL caused by the data stored in the memory cell MC1 is amplified by the sense amplifier 30, and the bit line BL and the bit auxiliary line / B are amplified.
The potential of L is set respectively. Then, the memory cell MC1 is rewritten according to the potential of the bit line BL.
Is set, the memory transistor Q
The escape of the charge accumulated in the gate of No. 3 is supplemented, and the loss of the data stored in the memory cell due to the escape of the charge is avoided. As described above, no special additional circuit is required for refreshing, and the circuit configuration of the semiconductor memory device can be simplified.

[0059]

As described above, according to the semiconductor memory device of the present invention, the number of bit contacts in a memory cell constituted by three transistors is reduced to one, so that the area of the memory cell is reduced. Can be realized.
Furthermore, according to the present invention, the refresh operation can be realized by reading and rewriting, and the bit line potential determined by reading is used for rewriting as it is,
In addition to the simplification of the refresh operation, there is an advantage that the circuit can be simplified without requiring an additional circuit for refreshing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram illustrating a configuration example of a memory cell included in a semiconductor memory device according to the present invention;

FIG. 3 is a waveform diagram showing read, write, and refresh operations of the memory cell shown in FIG. 2;

FIG. 4 is a circuit diagram showing a specific example of the semiconductor memory device of the present invention.

FIG. 5 is a timing chart showing a read operation of the semiconductor memory device of the present invention.

FIG. 6 is a circuit diagram showing an equivalent circuit in a memory cell and a reference memory cell at the time of reading.

FIG. 7 is a diagram showing a configuration of a memory cell of a conventional semiconductor memory device.

[Explanation of symbols]

10: word line drive circuit, 20: discharge circuit,
30: sense amplifier, DMC: reference cell, MC
1, MC2,..., MCm: memory cell, Q1: read transistor, Q2: write transistor, Q3: memory transistor, DQ1: reference read transistor, DQ2: reference write transistor, DQ3: reference memory transistor, RWL
... read word line, WWL ... write word line, DR
WL: Reference read word line, DWWL: Reference write word line, V _CC : Power supply voltage, GND ...
Ground potential.

Claims (9)

[Claims] 1. A bit line, a write word line, a read word line, one terminal is connected to the bit line, and a control terminal is connected to the read word line. A first transistor that is kept on by an applied voltage of a line, one terminal is connected to the other terminal of the first transistor, and a control terminal is connected to the write word line;
At the time of writing, a second transistor held in an on state by the voltage applied to the write word line, a control terminal connected to the other terminal of the second transistor, and one terminal connected to the first transistor A memory transistor connected to the other terminal, the other terminal connected to a power supply voltage line, and the control terminal being kept at a potential corresponding to the bit line potential at the time of writing. 2. The memory cell according to claim 1, wherein a bit contact is formed between said bit line and one terminal of said first transistor. 3. A write operation, wherein a read voltage for holding the first transistor in an ON state is applied to the read word line, a voltage corresponding to write data is applied to the bit line, and the write word line is written. 2. The memory cell according to claim 1, wherein a write voltage for holding said second transistor in an on state is applied to said memory cell. 4. In reading, the bit line is held at a reference voltage lower than the power supply voltage, a read voltage for holding the first transistor in an on state is applied to the read word line, The conduction state of the memory transistor is controlled according to the holding voltage of the control terminal,
2. The memory cell according to claim 1, wherein the bit line is held at either the reference voltage or a predetermined voltage between the reference voltage and the power supply voltage. 5. A write word line, a read word line, a reference write word line, a reference read word line, a first bit line, a second bit line, and the first and second bit lines before the start of reading. A discharge circuit that holds a bit line at a reference potential, a sense amplifier that detects a potential difference between the first and second bit lines during reading, a reference cell connected to the second bit line, At least one memory cell connected to a first bit line, the memory cell having one terminal connected to the first bit line, a control terminal connected to the read word line, A first transistor that is held in an on state by a voltage applied to the read word line during writing and reading; and one terminal is the other terminal of the first transistor. Is connected, a control terminal connected to the write word line,
At the time of writing, a second transistor held in an on state by the voltage applied to the write word line, a control terminal connected to the other terminal of the second transistor, and one terminal connected to the first transistor A memory transistor connected to the other terminal, the other terminal connected to a power supply voltage supply line, and the control terminal being held at a potential corresponding to the first bit line potential at the time of writing; In the cell, one terminal is connected to the second bit line, the control terminal is connected to the reference read word line, and the first terminal is held in an on state by a voltage applied to the reference read word line during reading. One terminal is connected to the other terminal of the first reference transistor, a control terminal is connected to the reference write word line, Before output, a second reference transistor held in an on state by an applied voltage of the reference write word line, a control terminal connected to the other terminal of the second reference transistor, and one terminal connected to the first terminal A semiconductor memory device having a reference memory transistor connected to the other terminal of the reference transistor, the other terminal connected to the power supply voltage line, and the control terminal being held at a potential corresponding to the power supply voltage before reading; . 6. The reference cell has a control terminal connected to a discharge control signal supply terminal, one terminal connected to the power supply voltage supply line, and another terminal connected to the other of the first reference transistor. 6. The semiconductor memory device according to claim 5, further comprising a third reference transistor connected to a terminal and held in an on state in response to said discharge control signal before reading. 7. The semiconductor memory device according to claim 5, wherein said memory transistor has a gate width larger than a gate width of said reference memory transistor. 8. The discharge circuit according to claim 1, wherein a control terminal is connected to a discharge control signal supply terminal, and
A first discharge transistor connected between the second bit line and the reference potential; a second discharge transistor connected between the second bit line and the reference potential; a control terminal connected to the discharge control signal supply terminal; And a third discharge transistor having a control terminal connected to the discharge control signal terminal and connected between the first and second bit lines.
13. The semiconductor memory device according to claim 1. 9. A first read drive transistor having a control terminal connected to a read control signal supply terminal, connected between the first bit line and a reference potential, and a control terminal connected to the read control signal supply terminal. A second read drive transistor connected to the terminal and connected between the second bit line and the reference potential, and when reading, a read voltage to the read word line and the reference read word line. 6. The semiconductor memory device according to claim 5, wherein a read control signal having a predetermined level is applied to a higher-order read control signal line in accordance with the application of the control signal, and the first and second read drive transistors are held in an on state.