JP2001005853A - Method for automatically arranging flip-flop inside of macro cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To equalize the clock wiring delay of flip-flop with data wiring delay by arranging a flip-flop to be terminal-designated at an optional position on a perpendicular bisector passing through the midpoint of a virtual straight line connecting a clock terminal and a data terminal to vertically cross with it in a horizontal direction. SOLUTION: One external DATA terminal stored in an external DATA terminal coordinate file F4 is extracted and one external CLK terminal stored in an external CLK terminal coordinate file F5 is extracted. Next, a straight line being a virtual line segment drawn between the two points of the extracted external DATA terminal and external CLK terminal is calculate-processed. Next, the virtual line segment passing through the midpoint of this straight line to vertically cross with it in a vertical direction is similarly obtained by calculating processing. Continually, a flip-flop to be terminal-designated where the name of a DATA terminal and the name of a CLK terminal used at the time of calculating the straight line and a perpendicular bisector are matched with each other is read from an FF information file F2 and arranged at an optional position on the perpendicular bisector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically arranging flip-flops inside a macro cell in a standard cell type chip layout design using an automatic layout design apparatus for a semiconductor integrated circuit, and more particularly to a clock wiring delay and data. And a method of automatically arranging flip-flops inside a macro cell, which is improved so that the wiring delays of the macro cells become equal.

[0002]

2. Description of the Related Art In recent years, the degree of integration of circuit elements of a semiconductor integrated circuit has been dramatically increased with the progress of semiconductor miniaturization technology, and the functions incorporated in the integrated circuit have also been enhanced. This high functionality is achieved by application-specific integrated circuits, so-called A
SIC (Application Specific I)
The same applies to the field C). One of the ASIC manufacturing methods is a standard cell method.

In the standard cell (cell-based) type circuit, a signal path must be propagated within a signal delay time limit range determined from the entire system. (Hereinafter referred to as a critical path), but the circuit may not operate properly due to the parasitic capacitance of the critical path.

Therefore, conventionally, as a method of shortening the signal propagation time of the critical path between the semiconductor elements,
For example, by arranging elements as much as possible, reducing the number of necessary isolation diffusion regions, and designing a large transistor area of a functional element constituting a critical path, by increasing the driving capability of the transistor, Critical path delay time is reduced.

[0005] Therefore, when the placement and routing is performed by the automatic placement and routing tool, the signal delay due to the routing is affected even in the critical path, and the signal delay time and timing verification after layout may not satisfy the required standard. However, it is difficult to design in a short period, which is an advantage of the gate array.

As means for improving the signal delay due to the influence of the layout, forcible placement by hand and insertion of a signal driving buffer into a long wiring path are performed.

FIG. 6 and a schematic schematic layout diagram showing a macro cell layout design flow as an example of a method of automatically arranging flip-flop circuits among cells frequently used in this kind of conventional standard cell system. A conventional technique will be described with reference to FIG.

Referring to FIG. 6, connection information is read from a circuit connection information file F1 in which wiring connection information between input and output of a component (cell) including a flip-flop constituting a circuit to be laid out is stored. Then, an arrangement area setting process S11 for setting an area for arranging each cell is executed.

When the placement area setting process S11 is completed, a signal is supplied to each cell or an external terminal position setting process S for determining the position of an external terminal for outputting a signal is performed.
Step 12 is executed. In this case, terminal information prepared in advance may be read.

[0010] Thereafter, by the automatic placement processing S13, the wiring is arranged so that the congestion degree of the wiring connecting the cells and the length of the wiring connecting the cells are as short as possible. After all the cells are arranged, the automatic wiring process S14 is executed.

Referring now to FIG. 7, FIG. 7 shows the positional relationship between the flip-flops and the external terminals of the macro cell when executing the processes S13 to S14 shown in FIG. This figure shows a macro cell in which the whole rectangle is G1. An external clock is supplied to the inside, and flip-flops 1, 2, 3 for inputting data in synchronization with this clock, and an external data terminal as the macro cell Flip-flops or other cells whose external DATA terminals (hereinafter referred to as external DATA terminals) are not connected to the data input terminals of the flip-flops (hereinafter referred to as external DATA input terminals) are represented by rectangular blocks.

In the macro cell G1, all the cells are automatically arranged so that the congestion degree of the wiring connecting the cells and the length of the wiring connecting the cells become shorter. At this time, the flip-flop 1, the flip-flop 2, and the flip-flop 3, in which the external CLK terminal and the external DATA terminal as the macro cell G1 are connected to the DATA input terminal of the flip-flop, are not specially recognized yet.

Automatic wiring processing is performed on the flip-flops 1, 2, 3 arranged so as to shorten the wiring congestion degree and the wiring length between cells, other flip-flops and other cells. The result of the automatic wiring is shown as a macro cell G2 in FIG.

In the prior art described above, referring to FIG. 7, when performing automatic placement, there are basically two factors to consider: the degree of congestion of wiring connecting cells and the length of wiring connecting cells. .

Therefore, in the flip-flops 1, 2, and 3 in which the external terminal as the macro cell is connected to the DATA input terminal of the flip-flop, it is determined to which terminal coordinates of the macro cell the CLK input terminal of the flip-flop is assigned. Similarly, it does not know to which external terminal coordinates of the macro cell the DATA input terminal of the flip-flop is assigned.

Therefore, as shown in the macro cell G2 of FIG. 7, the flip-flops 1, 2, and 3 are connected to the external CLK terminal of the macro cell from the CLK terminal of each flip-flop.
The wiring length of the wiring to the input terminal (shown by a thick solid line in the figure) is equal to the distance from the terminal of the macro cell to the data input terminal of the corresponding flip-flop (shown by the thin solid line in the figure) No.

Here, referring to FIG. 8, which shows a state of a timing change in which the delay time of the data wiring with respect to the clock CLK wiring affects the setup (Setup) time and the hold (Hold) time of the flip-flop, as described above. As a result, the wiring length of the wiring to the CLK input terminal of the flip-flop and the distance from the terminal of the macro cell to the data input terminal of the corresponding flip-flop are no longer equal. When the delay time from the external DATA terminal of the macro cell to the DATA input terminal of the flip-flop is longer than the delay time from the external DATA terminal of the macro cell to the flip-flop, as shown in FIG. Than setup time Between tc as long as it can be seen that there is a need to set.

Further, the delay time from the external CLK terminal of the macro cell to the CLK input terminal of the flip-flop is changed from the external DATA terminal of the macro cell to the flip-flop D signal.
When the delay time is shorter than the delay time to the ATA input terminal, the hold time of the macro cell needs to be set longer than the hold time of the flip-flop by the time tb as shown in FIG. Is worsening.

When the original setup time and hold time of the flip-flop cell used for the macro cell are used as the specifications of the macro, the wiring path from the external terminal of the macro cell to the CLK input terminal of the flip-flop and the external DATA terminal of the macro cell Cell for delay adjustment is arranged on the wiring path from the macro cell to the DATA input terminal of the flip-flop, and the delay time from the external CLK terminal of the macro cell to the CLK input terminal of the flip-flop, and the data input of the flip-flop from the external DATA terminal of the macro cell. It is necessary to make the delay time equal to the delay time to the terminal, which is a factor that causes an increase in the arrangement area of the macro cell and an increase in power consumption.

Further, as a technique for improving the delay time to the CLK input terminal of the flip-flop and the delay time to the DATA input terminal of the flip-flop, which is a problem of the conventional technique, for example, Japanese Patent Application Laid-Open No. 10-74842 is known. Have been.

A description will be given with reference to FIG. 9 showing a flow chart of the layout design and FIG. 10 showing a layout diagram based on the design flow chart.

First, referring to FIG. 9, a layout is started in a process S21, and after inputting circuit connection information from a predetermined storage means (process 22), a flip-flop (FF) for generating a netlist of flip-flops is provided. A net list generation process is performed (process S23).

At this time, referring to FIGS. 10A and 10B, the other cells related to the flip-flop are clustered, and the area information is associated with the flip-flop in the netlist. The clustering is a method of selecting another cell that is strongly coupled to an already arranged cell, and integrating the temporary wiring length and area to perform grouping.

Subsequently, in the flow of FIG. 9, a flip-flop (FF) area determining process for determining an area where the flip-flop is arranged is executed (processing S24).

Subsequently, initial placement processing of flip-flops is performed on the determined placement area (step S25). Referring to FIG. 10C corresponding to this processing, the flip-flops are arranged so that the timing is optimized based on the inter-flip-flop netlist to which the area information is added and the area information. However, only the wiring length between flip-flops is considered here.

Subsequently, in the flow of FIG. 9, the layout improvement processing is performed on the flip-flops which are initially placed (process S26). Referring to FIG. 10C corresponding to this processing, based on the inter-flip-flop netlist and the area information, the cell arrangement is improved in the entire arrangement area so that the timing is further optimized, and the clustered flip-flops are thereafter obtained. Cells other than flip-flops are arranged in each flip-flop arrangement area (FIG. 10D).

[0027]

As described above, the technique disclosed in Japanese Patent Application Laid-Open No. H10-74842 optimizes only between flip-flops in the flip-flop area determination processing (processing S24) shown in FIG. .

In the optimization, since the optimization is performed by using the clustered area information, the moving range is limited if the clustered area is large.

Further, during the optimization, the flip-flop cannot move out of the clustering area. Therefore Figure 1
As shown in the layout diagram (d) of FIG. 10, in all of the flip-flops 1, 2, and 3 whose terminals as macro cells are connected to the DATA input terminals of the flip-flops, the flip-flops of the flip-flops are connected from the external CLK terminal of the macro cell. The wiring length from the CLK input terminal to the CLK input terminal is longer than the wiring length from the external DATA terminal of the macro cell to the DATA input terminal of the flip-flop.

Therefore, the delay time from the external CLK terminal of the macro cell to the CLK input terminal of the flip-flop is changed from the terminal of the macro cell to the DATA of the flip-flop.
As shown in FIG. 8D, it is necessary to set the setup time of the macro cell longer than the setup time of the flip-flop cell by the time C, which deteriorates the performance of the macro cell. I have.

When the original setup time and hold time of the used flip-flop cell are used as the specifications of the macro, the wiring path from the external terminal of the macro cell to the CLK input terminal of the flip-flop and the flip-flop from the external terminal of the macro cell are used. DAT
A cell for delay adjustment is arranged on each of the wiring paths to the A input terminal, the delay time from the external CLK terminal of the macro cell to the CLK input terminal of the flip-flop, and the delay time from the external DATA terminal of the macro cell to the DATA of the flip-flop.
It is necessary to make the delay times to the input terminals equal, which is a factor that causes an increase in the arrangement area of the macro cells and an increase in power consumption.

An object of the present invention has been made in view of the above-mentioned drawbacks of the related art.
It is an object of the present invention to provide an automatic flip-flop arranging method in a macro cell in which a clock wiring delay and a data wiring delay of a flip-flop in a standard cell system of C are improved.

[0033]

A feature of the method for automatically arranging flip-flops in a macro cell according to the present invention is that it has an automatic arrangement and wiring process for arranging and wiring various cells including flip-flops in a standard cell system of a semiconductor integrated circuit. In an automatic layout design apparatus, a method for automatically arranging flip-flops inside a macro cell applied to the automatic layout and wiring processing, wherein one external clock terminal allocated to one side of the macro cell and a plurality of external clock terminals allocated to another side are provided. Of the external data terminals, the external clock terminal and any one of the external data terminals are used as one set of units, and the midpoint of a virtual straight line connecting the one set of terminals by the calculation processing of the automatic layout design device is defined as At an arbitrary position on a virtual vertical bisector that vertically intersects the And a process of arranging one of the terminal-designated flip-flops is repeated until a predetermined number of terminal-designated flip-flops are arranged. A flip-flop automatic arrangement process for making the wiring length between the external clock terminal and the clock input terminal substantially equal to the wiring length between the external data terminal and the data input terminal.

Further, prior to the processing step of arranging other flip-flops and other function cells other than the terminal-designated flip-flop, the flip-flop automatic arrangement processing can be prioritized.

Further, the automatic flip-flop placement processing refers to a circuit connection information file in which an instance name is written in addition to all the cell names in the macro cell stored in advance in the storage means of the automatic layout design apparatus. The flip-flop extraction and storage process of extracting information of all the flip-flops from the various cells and storing the information in the flip-flop information file, and automatically activating the macro cell based on the circuit connection information read from the circuit connection information file. A layout area setting process for setting layout areas of all the various cells when laying out, and assigning the positions of all external terminals to arbitrary sides of the macro cell, and externally assigning the position information of the assigned external terminals. External terminal position setting processing to be stored in the terminal information file; Extracting the coordinate information of only the terminal that matches the net name of the data input terminal of the terminal-designated flip-flop stored in the flip-flop information file from among the terminal names of the macro cell stored in the An external data terminal coordinate extraction process to be stored in an external data terminal coordinate file; and a terminal-designated flip-flop stored in the flip-flop information file from terminal names of the macro cells stored in the external terminal information file. External clock terminal coordinate extraction processing for extracting only the terminal that matches the net name of the clock input terminal of the external clock terminal and storing the extracted terminal in the external clock terminal coordinate file; Calculation of the automatic layout design device from the terminal coordinates Wherein the virtual of the vertical bisector obtained in management with an automatic position determination process of the flip-flop arranged to be terminal designation flip-flop, the processing steps consisting.

Further, the flip-flop extraction processing includes, using the cell name of the terminal-designated flip-flop from the circuit connection information file as a keyword, the cell name and the instance name of the terminal-designated flip-flop and the flip-flop. The net names of the data input terminal and the clock input terminal can be extracted.

The position information of the external terminal may be information obtained by extracting a terminal name of the macro cell and coordinates of its arrangement position from the external terminal information file.

Further, the flip-flop automatic arrangement processing extracts external data terminal coordinates from the external data terminal coordinates, and stores the coordinates in an external data terminal coordinate file. An external clock terminal coordinate extracting and storing process of extracting the coordinates of the one external clock terminal from the external clock terminal coordinates stored in the external clock terminal coordinate file and storing the extracted coordinates in the external clock terminal coordinate file; The virtual straight line connecting two points between the external data terminal stored in the terminal coordinate file and the external clock terminal stored in the external clock terminal coordinate file is calculated by a calculation process of the automatic layout design device. A straight line between the points is calculated, and a line segment passing through the middle point of the calculated straight line and intersecting vertically in the horizontal direction is set in front of A vertical bisector calculation process of storing the virtual vertical bisector data obtained in the calculation process of the automatic layout design device in a vertical bisector file, and calculating the straight line and the vertical bisector An external terminal connection flip-flop extraction process of extracting the terminal-designated flip-flop using the external data terminal name and the external clock terminal name used from the flip-flop information file; If it exists in the flip-flop information file and can be extracted, it is arranged at an arbitrary position on the vertical bisector, the arrangement information is stored in the flip-flop arrangement information file, and the external data terminal coordinate extraction and storage processing is performed again. And the flip-flop on the vertical bisector returning to the external clock terminal coordinate extraction and storage processing, respectively. If the terminal-designated flip-flop does not exist in the flip-flop information file and cannot be extracted, nothing is arranged on the vertical bisector, and the external data terminal coordinate extraction and storage process is performed again. And flip-flop non-arrangement processing returning to the external clock terminal coordinate extraction and storage processing. By repeating these processings sequentially, the extraction and arrangement processing of the terminal-designated flip-flop can be performed.

Furthermore, when the terminal-designated flip-flop used for calculating the vertical bisector in the vertical bisector flip-flop arrangement processing is arranged at an arbitrary position on the vertical bisector, The arrangement may be such that a part of the cell size of the terminal-designated flip-flop to be arranged is in contact with or penetrates the vertical bisector.

When there are a plurality of the external clock terminals and the plurality of the external data terminals, the processing up to the flip-flop arrangement processing on the vertical bisector is executed for the first one of the plurality of external clock terminals. Then, a second external clock terminal is read from the external clock terminal coordinate file, and the external clock terminal is connected to an external data terminal associated with the external clock terminal with reference to the second external clock terminal. Can be repeatedly executed in the order from the external data terminal coordinate extraction and storage processing to the vertical bisector flip-flop arrangement processing.

Further, when there are a plurality of the external clock terminals and the plurality of external data terminals, respectively, the flip-flop arrangement processing on the vertical bisector based on the first of the plurality of external data terminals is first performed. Then, the second external data terminal is read from the external data terminal coordinate file, and the external clock terminal associated with the external data terminal is connected based on the second external data terminal. The extraction and placement processing of the terminal-designated flip-flops can be repeatedly executed in the order from the external data terminal coordinate extraction and storage processing to the flip-flop placement processing on the vertical bisector.

Further, when there are a plurality of the external clock terminals and the plurality of external data terminals, first, the first external data terminal is associated with the first external clock terminal of the plurality. After executing the flip-flop arrangement processing on the vertical bisector, a second external data terminal is read from the external data terminal coordinate file, and is associated with the external data terminal with reference to the second external data terminal. The extraction and placement processing of the terminal-designated flip-flop to which the external clock terminal is connected is performed according to the order from the external data terminal coordinate extraction and storage processing to the vertical bisector flip-flop placement processing. And the external clock terminal may be alternately executed with the reference as the reference.

After the external terminal position setting process,
The method further includes a cell forcible placement process for forcibly placing a part of cells other than the terminal-designated flip-flop, wherein the flip-flop placement process on the vertical bisector is forcibly placed based on the result of the cell forced placement process. When a part of the cell other than the terminal-designated flip-flop is already arranged on the vertical bisector, avoid the cell and place the straight line and the vertical bisector on the vertical bisector. The terminal-designated flip-flop used for calculating the equal line may be arranged.

Further, the cells other than the terminal-designated flip-flop and which are to be subjected to the critical path can be arranged at predetermined positions predetermined by the forced arrangement.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a flow chart of a macro cell layout design in the method for automatically arranging flip-flops inside a macro cell according to the first embodiment of the present invention. Referring to FIG. 1, there is wiring connection information for connecting the components (cells) of the entire macro cell stored in advance in the storage means, and all the cells are unique in the circuit in addition to the cell names. Reference is made to the circuit connection information file F1 in which the unique instance name is written.

Extract all the flip-flop groups among the cells used as the macro cells from the referenced circuit connection information file F1 (flip-flop extraction processing S
1). That is, the flip-flop cell name, instance name, and connection information are extracted from the circuit connection information file F1 using the flip-flop cell name as a keyword.

Here, for ease of explanation, for example, the flip-flops connected to at least one external CLK terminal and a plurality of external DATA terminals of the macro cell are called flip-flops 1, 2, and 3, respectively.
It is assumed that there are a plurality of flip-flops that are not connected to the CLK terminal and the DATA terminal, these are the other flip-flops a and b, and that there are a plurality of functional cells other than the flip-flops, and these are cells p, q, and r.

The extracted flip-flops 1, 2, 2,
3, a and b are stored in a flip-flop information file (hereinafter F
(Referred to as F information file) F2. The FF information file F2 stores the instance name of the flip-flop, the net name of the DATA input terminal of the flip-flop, and the net name of the CLK input terminal of the flip-flop.

Subsequently, from the circuit connection information read from the circuit connection information file F1, an arrangement area which is an area necessary for arranging and wiring cells when automatically laying out macro cells is set (arrangement area setting processing S2). .

Next, the positions of all the external terminals are assigned to arbitrary sides of the macro cell, and the position information of the assigned external terminals of the macro cell is stored in the external terminal information file F3 (external terminal position setting processing S3). . The external terminal information file F3 stores the terminal names of the macro cells and their coordinates.

Subsequently, the flip-flops 1, 2, 3, and 3 stored in the FF information file F2 are selected from the macro cell terminal names stored in the external terminal information file F3.
In addition to extracting the coordinate information of only the terminal corresponding to the net name of the DATA input terminal from a and b, the extracted external D
The coordinate information of the ATA terminal is stored in the external DATA terminal coordinate file (external DATA terminal coordinate extraction processing S4).

Similarly, the flip-flops 1, 2, 3, and 3 stored in the FF information file F2 are selected from the terminal names of the macro cells stored in the external terminal information file F3.
Only terminals that match the net name of the CLK input terminal are extracted from a and b and stored in the external CLK terminal coordinate file F5 (external CLK terminal coordinate extraction processing S5).

Next, flip-flop automatic arrangement processing S6
Execute Referring to FIG. 2 showing the flow of the flip-flop automatic arrangement processing S6, the coordinates of one external DATA terminal, for example, DATA1, among the external DATA terminal coordinates stored in the external DATA terminal coordinate file F4 is extracted (external). Processing S for extracting one DATA terminal coordinate
61), the extracted coordinates of DATA1 are stored in one external DATA terminal coordinate file F6.

On the other hand, one of the external CLK terminal coordinates among the external CLK terminal coordinates stored in the external CLK terminal coordinate file F5
The coordinates of the terminal, for example, CLK1, are extracted (the process of extracting one external CLK terminal coordinate S62), and the extracted coordinates of CLK1 are stored in one external CLK terminal coordinate file F7.

Subsequently, a straight line drawn between the two points of the external DATA terminal DATA1 and the external CLK terminal CLK1 extracted in steps S61 and S62 is calculated.

The straight line between these two points is an imaginary line segment which is calculated by the automatic layout design apparatus. One of the external DATA terminal coordinates in the external DATA terminal coordinates
An imaginary line passing through the midpoint of a straight line connecting the coordinates of TA1 and the coordinates of one external CLK terminal CLK1 among the external CLK terminal coordinates stored in the external CLK terminal coordinate file F5, and intersecting vertically in the horizontal direction. The component is similarly obtained by calculation processing by the automatic layout design apparatus (vertical bisector calculation processing S63 between two points). Hereinafter, this virtual line segment is referred to as a vertical bisector.

The data of the vertical bisector calculated in step S63 is stored in the vertical bisector file F8.

In the calculation of the vertical bisector in the process S63, if the external DATA terminal coordinates (x1, y1) and the external CLK terminal coordinates (x2, y2) are extracted, for example, ((x
The midpoint is extracted by (1 + x2) / 2 and (y1 + y2) / 2), and then a vertical bisector is generated therefrom.

Subsequently, a terminal-designated flip-flop 1 in which the DATA terminal name DATA1 and the CLK terminal name CLK1 used for calculating the straight line and the perpendicular bisector described above are read from the FF information file F2 (external terminal connection flip-flop). Extraction processing S64).

If there is a coincident terminal-designated flip-flop 1, it is arranged at an arbitrary position on the vertical bisector (the existence of the corresponding flip-flop S65, the flip-flop arrangement process 67 on the vertical bisector). . If there is no matching terminal-designated flip-flop 1,
Nothing is arranged on the vertical bisector, and the processing S6 is performed again.
1. Return to S62. (Process S65 for judging existence of the corresponding flip-flop, process S6 for disposing no flip-flop)
6).

To arrange at an arbitrary position on the vertical bisector in step S67, the terminal-designated flip-flop is arranged so that a part of the cell size of the terminal-designated flip-flop intersects the vertical bisector. The vertical bisector is the cell size (rectangular) of the flip-flop specified by the terminal
The terminal-designated flip-flop is arranged so as to be in contact with or penetrate through.

The cell size of the terminal-designated flip-flop is determined by the LEF of the automatic layout design apparatus for flip-flops.
(Library Exchange Format)
Is stored within.

Generally, a plurality of flip-flops to which one clock is commonly wired are arranged in a macro cell.
Different data are input to each of them, and some flip-flops are connected to the external DATA terminal of the external terminal of the macro cell.

Therefore, here, for example, one external CL
The processes from S61 to S67 are repeatedly executed with reference to the K terminal to find and arrange a terminal-designated flip-flop associated as a flip-flop to be arranged on the vertical bisector, and then return to the processes S61 and S62. If not found, the process returns to steps S61 and S62 without arrangement.

When the process of extracting and arranging the terminal-designated flip-flop associated with CLK1 is completed by repeating this process, the external designated CLK-terminal CLK2 is then used as a reference and the terminal-designated flip-flop associated with CLK2 is determined. The extraction and arrangement processing is repeatedly executed in a similar processing order.

In the above-described processing S66, the external terminal as the macro cell is set to the DA of the terminal-designated flip-flop.
The arrangement information of the flip-flop connected to the TA input terminal is stored in the flip-flop arrangement information file F9.

This flip-flop arrangement information is for extracting, from the circuit connection information, a flip-flop in which the name of the net connected to the external DATA terminal is the same as the name of the net connected to the DATA input terminal of the flip-flop.

When the processes up to the storage process are completed, the process returns to the processes S61 and S62, and the process S6 is also performed for the extraction and arrangement of the remaining terminal-designated flip-flops 2 and 3.
Repeat up to 7.

In the above-described example, the terminal-designated flip-flop to which the external DATA terminal associated with the external CLK terminal is connected and extracted is extracted and arranged. A terminal-designated flip-flop connected to the external CLK terminal associated therewith may be extracted and arranged.

For example, when there are a plurality of external clock terminals and a plurality of external data terminals, respectively, the flip-flop arranging process S67 on the vertical bisector based on the first external data terminal DATA1 of the plurality is first performed. After execution, the second external DATA terminal DATA2 is read from the external DATA terminal coordinate file F4, and the second
Extraction and placement processing of a terminal-designated flip-flop to which an external CLK terminal associated with this external DATA terminal is connected with reference to the external DATA terminal
The processing may be repeatedly executed in the order from the A terminal coordinate extraction storage processing S61 to the flip-flop arrangement processing S67 on the vertical bisector.

Further, an external CLK terminal and an external DAT
The terminal-designated flip-flops to which the associated external CLK terminals are connected may be extracted and arranged alternately with the A terminal as a reference.

For example, an external CLK terminal and an external DAT
When there are a plurality of A terminals, respectively, first, the first external DATA terminal DATA1 is associated with the first external clock terminal CLK1 of the plurality of terminals and the flip-flop arrangement processing on the vertical bisector is performed. After execution,
Next, a second external DATA terminal DATA2 is read from the external DATA terminal coordinate file F4, and a terminal-designated flip-flop to which an external CLK terminal associated with the external DATA terminal is connected with reference to the second external data terminal May be repeatedly executed based on the external DATA terminal and the external CLK terminal alternately in accordance with the order from the external DATA terminal coordinate extraction and storage processing S61 to the vertical bisector flip-flop arrangement processing S67.

Which processing method is to be selected is set in advance by software using a processing program of an automatic layout design apparatus to which this arrangement processing is applied.

The information relating to File 2, File 3, File 4, File 5, File 6, File 7, File 8, and File 9 is based on keyword (instance name, cell name) based on circuit connection information or Placement and wiring information (DEF: Design Excha)
nFormat).

Referring again to FIG. 1, after performing the above-described flip-flop automatic placement processing S6, the automatic placement processing S7 is performed. In the automatic arrangement processing S7, the external DATA terminal as a macro cell is connected to the flip-flop DA.
Other flip-flops not connected to the TA input terminal and functional cells other than flip-flops are automatically arranged.

In the automatic arrangement, as in the conventional case, the cells are arranged in consideration of the degree of congestion of the wiring connecting the cells, and the cells are rearranged at locations exceeding the congestion degree given by the parameters. Also, the wiring is arranged so that the wiring length connecting the cells becomes short.

By executing the above-described processing up to S7, all the cells are arranged. Thereafter, the automatic wiring processing S8 is executed.

Automatic placement processing S7. And automatic wiring processing S
Reference numeral 8 denotes a generally performed process of the automatic layout design apparatus, and details thereof will be omitted.

Hereinafter, the flow of the macro cell layout design according to the present invention shown in FIG. 1 and the detailed flow of the flip-flop automatic arrangement processing S6 of the present invention shown in FIG. 2, and FIG.
The operation of the embodiment of the present invention will be described with reference to the layout diagram obtained by applying the present invention shown in FIG.

First, referring to FIG. 3, which shows a schematic diagram of a macro cell arranged and wired based on each of the above-mentioned processes, FIG. 3 shows a terminal designation when the processes S6 to S8 shown in FIG. 1 are executed. External D of flip-flop and macrocell
It clarifies the positional relationship between the ATA terminal and the external CLK terminal.

Here, as an example, a terminal-designated flip-flop to which an external CLK terminal associated with each external CLK terminal and an external DATA terminal are connected is extracted and arranged alternately with reference to an external CLK terminal and an external DATA terminal.

Also, in FIG. 3, in the rectangular diagram showing the terminal-designated flip-flop associated with the external CLK terminal and the external DATA terminal of the macro cell,
A few numbers are indicated. Other flip-flops not associated with the external CLK terminal and the external DATA terminal are denoted by a and b, and the other functional cells are denoted by p, q, and r. Further, the above-mentioned virtual straight line is shown by a solid line, and the virtual vertical bisector is shown by a dotted line.

In FIG. 3A, DATA1 is extracted from the external DATA terminal coordinate file F4 and CLK1 is extracted from the external CLK terminal coordinate file F5, and a straight line between the two points and a middle point of the straight line intersect vertically in the horizontal direction. 3 schematically shows that the perpendicular bisector of the above is calculated.

From the FF information file F2, the net names of the DATA input terminal of the flip-flop and the CLK input terminal of the flip-flop are DATA1 and CLK.
Since the terminal-designated flip-flop 1 associated with 1 is extracted, the terminal-designated flip-flop 1 is arranged on a vertical bisector.

Similarly, referring to FIG. 3B, the processing S
When processing from step 61 to processing A63, DATA2 is extracted from the external DATA terminal coordinate file F4, and CLK2 is extracted from the external CLK terminal coordinate file F5, and the external DATA terminal DATA2 and external CLK terminal CLK2 are extracted.
A virtual vertical bisector between the two points is calculated.

Next, the FF information file F2 is searched for flip-flops whose net names of DATA input terminals of flip-flops and CLK input terminals of flip-flops are DATA2 and CLK2. Since there is no flip-flop, no flip-flop is arranged on the calculated virtual vertical bisector.

Next, referring to FIG. 3C, the external DA
DATA3, external CLK from TA terminal coordinate file F4
CLK1 is extracted from the terminal coordinate file F5, and the external DATA terminal DATA3 and the external CLK terminal CLK1 are extracted.
A virtual vertical bisector between the two points is calculated.

Next, from the FF information file F2, the terminal-designated flip-flop 3 whose net names of the DATA input terminal of the flip-flop and the CLK input terminals of the flip-flop are DATA3 and CLK1 are placed on a virtual vertical bisector. To place.

Next, referring to FIG. 3D, after the terminal-designated flip-flops 1 and 3 are arranged, the external DATA terminal as a macrocell is not connected to the DATA input terminal of the flip-flop. Function cells are placed, and external CLK
The effects of the present invention become apparent when individual wiring is performed from the terminals to the terminal-designated flip-flops 1 and 3, respectively.

As can be seen from FIG. 3D, the external DATA terminal as the macro cell is connected to the flip-flop DATA.
In each of the terminal-designated flip-flops 1 and 3 connected to the input terminal, the wiring length from the external CLK terminal CLK1 to the CLK input terminal of the terminal-designated flip-flop and the external DATA
The wiring length from the terminal to the DATA input terminal designated by the flip-flop terminal is almost equal, therefore, the external CLK
Since the delay time from the terminal to the CLK input terminal of the specified flip-flop is almost equal to the delay time from the external DATA terminal to the DATA input terminal of the specified flip-flop, the delay time is used as shown in FIG. The original setup time and hold time of the flip-flop cell can be used as the specifications of the macro cell.

Therefore, it is not necessary to arrange delay adjustment cells in the wiring path from the external CLK terminal to the flip-flop and in the wiring path from the external DATA terminal to the flip-flop. The effect that power consumption can be reduced as much as the cell becomes unnecessary is obtained.

Next, FIG. 4 shows a flow of the placement method according to the second embodiment of the present invention, and FIG. 5 shows a flow of automatic placement and wiring of macro cells and a layout diagram thereof according to the present invention.
The second embodiment will be described with reference to FIG.

Referring to FIG. 4, the difference from FIG. 1 in the first embodiment is that the circuit connection information file F
That is, after the external terminal position setting processing S3 for reading the external terminal position information from No. 1, a forced arrangement processing S9 for forcibly arranging a part of the cell is further added.

The method for arranging flip-flops according to the present embodiment will be described below. In this embodiment, the processing S1
Steps S5 to S5 are performed in the same manner as in the first embodiment. That is, the flip-flop used in the macro cell is extracted from the circuit connection information file F1, and the flip-flop is used.
The information is stored in the information file F2 (process S1).

The FF information file F2 stores the instance names of all the flip-flops used, the net names of the DATA input terminals of the flip-flops, and the net names of the CLK input terminals of the flip-flops.

Subsequently, a cell arrangement area for automatically laying out a macro cell is set based on information from the circuit connection information file F1 (step S2), and external terminals of the macro cell are assigned to this area (step S3). ), The terminal name of the macro cell and its coordinates are stored in the external terminal information file F3 as all the external terminal information of the macro cell.

Subsequently, among the flip-flops stored in the FF information file F2, DATs are selected from the macro cell terminal names stored in the external terminal information file F3.
Only the terminal that matches the net name of the A input terminal is extracted and stored in the external DATA terminal coordinate file F4.

Similarly, from among the terminal names of the macro cells stored in the external terminal information file F3, CLK among the flip-flops stored in the FF information file F2 are selected.
Only the terminal that matches the net name of the input terminal is extracted and stored in the external CLK terminal coordinate file F5.

Further, after the above-described processing S3 for assigning the external terminals of the macro cell, a processing S9 for forcibly disposing a part of the cell, which is a feature of the present embodiment, is executed.

The forced placement of a part of the cells is added because it is necessary that the cells other than the terminal-designated flip-flop, which are to be subjected to the critical path, must be placed at a desired position in advance. Things.

Next, in the automatic arrangement processing S6, the external DA
One coordinate in the TA terminal coordinate file F4 and the external CLK
A virtual vertical bisector between one coordinates in the terminal coordinate file F5 is calculated by the automatic layout design device.

Subsequently, from the FF information file F2, a terminal-designated flip-flop whose DATA terminal name and CLK terminal name used for calculating the vertical bisector are arranged on a virtual vertical bisector.

At this time, if some of the cells that have been forcibly arranged in step S9 are already arranged on the vertical bisector, the cells are avoided and arranged on the vertical bisector.

After the flip-flop automatic arrangement processing S6,
In the automatic placement processing S7, other flip-flops whose external terminals are not connected to the DATA input terminals of the flip-flops and functional cells other than the flip-flops are placed.

After all the cells are arranged, the automatic wiring processing S8 is executed.

Referring to FIG. 5, which shows a schematic diagram of the macro cells arranged and wired based on the processing of the above-described second embodiment, FIG. 5 is newly added with processing S6 to processing S8 shown in FIG. 9 clarifies the positional relationship between the terminal-designated flip-flop and the external DATA terminal and external CLK terminal of the macro cell when the processing 9 is executed.

Here, as an example, external DATA terminals DATA1, DATA2,
The terminal-designated flip-flops respectively associated with DATA3 are extracted and arranged.

In FIG. 5, the cells forcibly arranged in the added process 9 are indicated by X1, X2, and X3, and a terminal-designated flip-flop associated with the external CLK terminal and the external DATA terminal of the macro cell. Numbers 1, 2, and 3 are described in the rectangular diagram showing the loops. Also,
Other flip-flops not associated with the external CLK terminal and the external DATA terminal are denoted by a and b, and functional cells other than the flip-flops are denoted by p, q, and r. Further, a virtual straight line is shown by a solid line, and a virtual vertical bisector is shown by a dotted line.

In FIG. 5A, DATA1 is extracted from the external DATA terminal coordinate file F4 and CLK is extracted from the external CLK terminal coordinate file F5, and a virtual straight line between the two points and a middle point of the straight line intersect vertically in the horizontal direction. This schematically shows that a virtual vertical bisector is calculated.

First, the cells X1, X2, and X3 that have been forcibly arranged by the process 9 have already been arranged. In this state,
From the FF information file F2, the DAT of the flip-flop
A input terminal net name and flip-flop CLK
Since the terminal-designated flip-flop 1 whose input terminal net name is associated with DATA1 and CLK is extracted,
This terminal-designated flip-flop 1 is forcibly placed in cell X
It is arranged below, for example, the center on the vertical bisector of the location excluding 1, X2, and X3.

Similarly, referring to FIG. 5B, the processing S
When processing from step S61 to step S63, DATA2 is extracted from the external DATA terminal coordinate file F4 and CLK is extracted from the external CLK terminal coordinate file F5, and a vertical bisector between the two points of the external DATA terminal DATA2 and the external CLK terminal CLK is extracted. calculate.

Next, the FF information file F2 is searched for a flip-flop in which the net name of the DATA input terminal of the flip-flop and the net name of the CLK input terminal of the flip-flop are DATA2 and CLK. Since the terminal-designated flip-flop 2 exists and has been extracted, the forcibly arranged cells X1 and X2 on the calculated virtual vertical bisector are calculated.
2, the terminal-designated flip-flop 2 is arranged at a position other than X3, for example, at the upper left position.

Next, referring to FIG. 5C, the external DA
DATA3, external CLK from TA terminal coordinate file F4
CLK is extracted from the terminal coordinate file F5.
ATA terminal DATA3 and external CLK terminal CLK2
Compute a virtual vertical bisector between points.

Next, from the FF information file F2, the terminal-designated flip-flop 3, whose net names of the DATA input terminals of the flip-flops and the CLK input terminals of the flip-flops are DATA3 and CLK, are forcibly placed in the cell X1 , X3 and a little lower left than the center on the vertical bisector.

Next, referring to FIG. 5D, after the terminal-designated flip-flops 1, 2, and 3, the external terminal as a macro cell is not connected to the DATA input terminal of the flip-flop in step S7. In addition, the flip-flops a and b and the functional cells p, q, and r other than the flip-flops are respectively arranged, and individual wirings are respectively connected from the external CLK terminal CLK to the terminal-designated flip-flops 1, 2, and 3 by automatic wiring in step S8. The effect of the second embodiment becomes apparent when the operation is performed.

As can be seen from FIG. 5 (d), even when there is a forced placement cell, the external terminal as a macro cell excluding the forced placement cell region is connected to the DATA input terminal of the flip-flop. Flip-flop 1,
In 2.3, the wiring length from the external CLK terminal CLK to the CLK input terminals of the terminal-designated flip-flops 1, 2, and 3, and the wiring length from the external DATA terminal to the DATA input terminals of the terminal-designated flip-flops 1, 2, and 3 The corresponding wiring lengths are substantially equal, and therefore, the delay time from the external CLK terminal to the CLK input terminal of the terminal-designated flip-flop is almost equal to the delay time from the external DATA terminal to the DATA input terminal of the designated flip-flop. Therefore, as shown in FIG. 8C, the original setup time and hold time of the flip-flop to be used can be used as the specifications of the macro cell.

Therefore, similarly to the first embodiment, the external C
There is no need to arrange cells for delay adjustment in the wiring path from the LK terminal to the flip-flop and in the wiring path from the external DATA terminal to the flip-flop. This reduces the area for arranging macro cells and eliminates the need for cells for delay adjustment. Thus, the effect of reducing power consumption can be obtained.

[0118]

As described above, the method for automatically arranging flip-flops inside a macro cell according to the present invention is an automatic flip-flop having an automatic arrangement and wiring process for arranging and wiring various cells including flip-flops in a standard cell system of a semiconductor integrated circuit. An automatic placement method for flip-flops inside a macro cell, which is applied to an automatic placement and routing process for a layout design device, wherein one external clock terminal assigned to one side of the macro cell and a plurality of external clock terminals assigned to another side are provided. Of the data terminals, the external clock terminal and any one of the external data terminals are taken as one set of units, and the horizontal direction passes through the middle point of a virtual straight line connecting the set of terminals by the calculation processing of the automatic layout design device. At any position on an imaginary perpendicular bisector that intersects vertically, one of the terminals previously associated with a set of terminals And the process of arranging the terminal-designated flip-flop is repeated until the arrangement is completed for a predetermined number of terminal-designated flip-flops, and between the external clock terminal and the clock input terminal. Since the flip-flop automatic arrangement processing for making the wiring length of the external data terminal and the wiring length between the data input terminal substantially equal to each other,
The terminal as the macro cell is the DATA of the flip-flop.
Regarding, for example, the terminal-designated flip-flop 1, the terminal-designated flip-flop 2, and the terminal-designated flip-flop 3 connected to the input terminals, the external CLK of the macro cell
Since the distance from the terminal is almost equal to the distance from the external DATA terminal, and the delay time from the external CLK terminal to the flip-flop is almost equal to the delay time from the external DATA terminal to the flip-flop, as shown in FIG. To
The original setup time and hold time of the used flip-flop cell can be used as the specifications of the macro cell.

Further, after the external terminal position setting processing, there is further provided a cell forced arrangement processing for forcibly arranging a part of the cells other than the terminal-designated flip-flop. If some of the cells other than the pin-designated flip-flops that have been forcibly placed based on the result of the cell forcible placement have already been placed on the vertical bisector, avoid that cell and place it on the vertical bisector. Because the specified flip-flops used for calculating the straight line and the vertical bisector are placed, even if there are forced placement cells, the flip-flops are placed on the virtual vertical bisector excluding the area of the forced placement cells. Can be arranged.

Therefore, it is not necessary to arrange delay adjustment cells in the wiring path from the external CLK terminal to the terminal-designated flip-flop and in the wiring path from the external DATA terminal to the terminal-designated flip-flop, and to reduce the macro cell arrangement area. And power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart of a method for automatically arranging flip-flops in a macro cell according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a flip-flop automatic arrangement process S6.

FIG. 3 is a schematic diagram of a macro cell arranged and wired based on processing in the first embodiment.

FIG. 4 is a flowchart of a method for automatically arranging flip-flops inside a macro cell according to a second embodiment of the present invention.

FIG. 5 is a schematic layout diagram of macro cells arranged and wired based on the processing of the second embodiment.

FIG. 6 is a flowchart of a conventional macro cell layout design.

FIG. 7 is a schematic view showing a layout of a conventional macro cell layout design flow.

FIG. 8 shows a delay time of DATA of a flip-flop Se.
9 is a timing chart showing a state of a timing change that affects the up time and the Hold time.

FIG. 9 is a flowchart of another conventional layout design.

FIG. 10 is a schematic layout diagram based on a conventional design flowchart.

[Explanation of symbols]

S1 flip-flop extraction processing S2 arrangement area setting processing S3 external terminal position setting processing S4 external DATA terminal coordinate extraction processing S5 external CLK terminal coordinate extraction processing S6 flip-flop automatic arrangement processing S7 other cell automatic arrangement processing S8 automatic wiring processing S9 forced arrangement Processing S61 Processing for extracting one external DATA terminal coordinate S62 Processing for extracting one external CLK terminal coordinate S63 Vertical bisector calculation processing between two points S64 External terminal connection flip-flop extraction processing S65 Judgment of existence of the corresponding flip-flop Processing S66 Processing without arranging flip-flops S67 Processing for arranging flip-flops on the vertical bisector F1 Circuit connection information file F2 FF information file F3 External terminal information file F4 External DATA terminal coordinate file F5 External CLK terminal coordinate file F6 1 one external DATA terminal coordinate file F7 1 one external CLK terminal coordinate file F8 perpendicular bisector file F9 flip flop arrangement information file CLK, CLK1, CLK2 macrocell external CL
K terminal DATA1, DATA2, DATA3 External DATA terminal of macro cell

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA05 5F064 BB19 DD02 DD25 EE02 EE08 EE15 EE54 HH06 HH10 HH11 HH12

Claims (12)

[Claims] An automatic layout design apparatus having an automatic placement and routing process for arranging and routing various cells including flip-flops in a standard cell system of a semiconductor integrated circuit. In the automatic flip-flop arrangement method, the external clock terminal and any one of the external data terminals among one external clock terminal allocated to one side of the macro cell and a plurality of external data terminals allocated to the other side are Is a set of units, an arbitrary position on a virtual vertical bisector that passes through the midpoint of a virtual straight line connecting the set of terminals in the calculation processing of the automatic layout design apparatus and intersects vertically in the horizontal direction. And a terminal-designated flip-flop previously associated with the set of terminals, The process of arranging the terminal-designated flip-flops is repeated until the arrangement is completed for a predetermined number of the terminal-designated flip-flops, and the wiring length between the external clock terminal and the clock input terminal and the external data terminal And a flip-flop automatic placement method for making the wiring length between the data input terminals substantially equal to each other. 2. The automatic flip-flop inside the macro cell according to claim 1, wherein prioritizing the automatic flip-flop placement processing before a processing step of arranging other flip-flops and other functional cells other than the terminal-designated flip-flop. Placement method. 3. The automatic flip-flop placement processing includes:
By referring to a circuit connection information file in which an instance name is written in addition to all the cell names in the macro cell stored in advance in the storage means of the automatic layout design device, all the flip-flops of the various cells are referred to. A flip-flop extraction and storage process for extracting information and storing the information in a flip-flop information file, and arranging all the various cell arrangement areas when automatically laying out the macro cells based on the circuit connection information read from the circuit connection information file. An arrangement area setting process to be set, and an external terminal position setting process of assigning the positions of all the external terminals to arbitrary sides of the macro cell and storing the assigned external terminal position information in an external terminal information file, From the terminal names of the macro cell stored in the external terminal information file, External data terminal coordinate extraction processing for extracting coordinate information of only the terminal that matches the net name of the data input terminal of the terminal-designated flip-flop stored in the flip-flop information file and storing the coordinate information in the external data terminal coordinate file; Extracting, from the terminal names of the macro cell stored in the external terminal information file, only those terminals that match the net names of the clock input terminals of the terminal-designated flip-flops stored in the flip-flop information file. External clock terminal coordinate extraction processing to be stored in an external clock terminal coordinate file, and the automatic layout design apparatus calculated from the external clock terminal coordinates and the external data input terminal coordinates for the terminal-designated flip-flop. The terminal-designated flip is placed on the virtual vertical bisector. An automatic position determination process of the flip-flop placing flop, flip-flop automatic placement method within the macrocell according to claim 1, further comprising a processing step consisting of. 4. The flip-flop extracting process includes, using the cell name of the terminal-designated flip-flop from the circuit connection information file as a keyword, the cell name and instance name of the terminal-designated flip-flop, and the data of the flip-flop. 4. The method according to claim 3, wherein the input terminal and the net name of the clock input terminal are extracted. 5. The method for automatically arranging flip-flops inside a macro cell according to claim 3, wherein the position information of the external terminal is information obtained by extracting a terminal name of the macro cell and coordinates of its arrangement position from the external terminal information file. . 6. The automatic flip-flop placement processing includes:
An external data terminal coordinate extraction and storage process for extracting coordinates of one of the external data terminal coordinates from the external data terminal coordinates and storing the same in an external data terminal coordinate file; and an external clock terminal stored in the external clock terminal coordinate file. Extracting the coordinates of the one external clock terminal from the coordinates,
External clock terminal coordinate extraction and storage processing to be stored in the external clock terminal coordinate file; and two points: the external data terminal stored in the external data terminal coordinate file and the external clock terminal stored in the external clock terminal coordinate file. Calculating a straight line between two points, which calculates the virtual straight line connecting the two in the calculation processing of the automatic layout design device,
The data of the virtual vertical bisector obtained by the calculation process of the automatic layout design device is stored in a vertical bisector file, the line segment passing through the calculated midpoint of the straight line and intersecting vertically in the horizontal direction. A vertical bisector calculation process, and the terminal-designated flip-flop using the external data terminal name and the external clock terminal name used for the calculation of the straight line and the vertical bisector, External terminal connection flip-flop extraction processing to extract from a file, and, if the terminal-designated flip-flop exists in the flip-flop information file and can be extracted, arrange it at an arbitrary position on the vertical bisector, and then arrange it Information is stored in the flip-flop arrangement information file, and the external data terminal coordinate extraction and storage process and the external clock are stored again. Returning to the child coordinate extraction storage processing, the flip-flop arrangement processing on the vertical bisector is performed. If the terminal-designated flip-flop does not exist in the flip-flop information file and cannot be extracted, nothing is displayed on the vertical bisector. A flip-flop non-arrangement process that returns to the external data terminal coordinate extraction and storage process and the external clock terminal coordinate extraction and storage process again without disposing the terminal device. 4. The method for automatically arranging flip-flops in a macro cell according to claim 3, wherein the flip-flops are extracted and arranged. 7. When the terminal-designated flip-flop used for calculating the vertical bisector in the vertical bisector flip-flop arrangement processing is arranged at an arbitrary position on the vertical bisector, 7. The automatic flip-flop arranging method according to claim 6, wherein a part of the cell size of the terminal-designated flip-flop is arranged so as to be in contact with or penetrate the vertical bisector. 8. When there are a plurality of the external clock terminals and the plurality of external data terminals, respectively, up to the flip-flop arrangement processing on the vertical bisector for the first external clock terminal of the plurality of external clock terminals and the external data terminals Then, a second external clock terminal is read from the external clock terminal coordinate file, and the external clock terminal is connected to an external data terminal associated with the external clock terminal with reference to the second external clock terminal. 7. A method for automatically arranging flip-flops inside a macro cell according to claim 6, wherein the extraction and arrangement processing of the flip-flops in the macro cell are repeatedly executed in the order from the external data terminal coordinate extraction and storage processing to the flip-flop arrangement processing on the vertical bisector. 9. When there are a plurality of said external clock terminals and said plurality of external data terminals, respectively, the flip-flop arrangement processing on the vertical bisector based on a first external data terminal among these plurality of terminals first. Then, a second external data terminal is read from the external data terminal coordinate file, and the external clock terminal associated with the external data terminal is connected with reference to the second external data terminal. 7. The automatic flip-flop arranging method according to claim 6, wherein the extraction and arrangement processing of the terminal-designated flip-flop is repeatedly executed in the order from the external data terminal coordinate extraction and storage processing to the flip-flop arrangement processing on the vertical bisector. . 10. When there are a plurality of said external clock terminals and said plurality of external data terminals, respectively, first, a first external data terminal is associated with a first external clock terminal of the plurality of external clock terminals. After executing the flip-flop arrangement processing on the vertical bisector, a second external data terminal is read from the external data terminal coordinate file, and the second external data terminal is associated with the external data terminal with reference to the second external data terminal. Extracting and arranging the terminal-designated flip-flop to which the external clock terminal is connected, according to the order from the external data terminal coordinate extraction and storage processing to the vertical bisector flip-flop arranging processing; 7. The method according to claim 6, wherein the external clock terminal is alternately and repeatedly executed based on the reference.
A method for automatically arranging flip-flops inside a macro cell as described above. 11. A cell forced placement process for forcibly placing a part of cells other than the terminal-designated flip-flop after the external terminal position setting process, wherein the flip-flop placement on the vertical bisector is further provided. When a part of the cells other than the terminal-designated flip-flop forcibly arranged based on the result of the cell forcible arrangement is already arranged on the vertical bisector, the cell is avoided, and 7. The automatic flip-flop arranging method according to claim 6, wherein the terminal-designated flip-flop used for calculating the straight line and the vertical bisector is arranged on the vertical bisector. 12. A method according to claim 11, wherein a cell to be subjected to a critical path among cells other than the terminal-designated flip-flop is arranged at a predetermined position determined by the forced arrangement. .